tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: Add headers for NVDEC on Tegra234

Add clock, memory controller, powergate and reset dt-binding headers
necessary for NVDEC.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Mikko Perttunen and committed by
Thierry Reding 0e2b014e 9abf2313

+9
+4
include/dt-bindings/clock/tegra234-clock.h
··· 82 82 #define TEGRA234_CLK_I2S6 66U 83 83 /** @brief clock recovered from I2S6 input */ 84 84 #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 85 + /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 86 + #define TEGRA234_CLK_NVDEC 83U 85 87 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 86 88 #define TEGRA234_CLK_PLLA 93U 87 89 /** @brief PLLP clk output */ ··· 132 130 #define TEGRA234_CLK_SYNC_I2S5 149U 133 131 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 134 132 #define TEGRA234_CLK_SYNC_I2S6 150U 133 + /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ 134 + #define TEGRA234_CLK_TSEC_PKA 154U 135 135 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 136 136 #define TEGRA234_CLK_UARTA 155U 137 137 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
+3
include/dt-bindings/memory/tegra234-mc.h
··· 32 32 #define TEGRA234_SID_PCIE10 0x0b 33 33 #define TEGRA234_SID_BPMP 0x10 34 34 #define TEGRA234_SID_HOST1X 0x27 35 + #define TEGRA234_SID_NVDEC 0x29 35 36 #define TEGRA234_SID_VIC 0x34 36 37 37 38 /* Shared stream IDs */ ··· 102 101 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 103 102 #define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c 104 103 #define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d 104 + #define TEGRA234_MEMORY_CLIENT_NVDECSRD 0x78 105 + #define TEGRA234_MEMORY_CLIENT_NVDECSWR 0x79 105 106 /* BPMP read client */ 106 107 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 107 108 /* BPMP write client */
+1
include/dt-bindings/power/tegra234-powergate.h
··· 19 19 #define TEGRA234_POWER_DOMAIN_MGBEB 18U 20 20 #define TEGRA234_POWER_DOMAIN_MGBEC 19U 21 21 #define TEGRA234_POWER_DOMAIN_MGBED 20U 22 + #define TEGRA234_POWER_DOMAIN_NVDEC 23U 22 23 #define TEGRA234_POWER_DOMAIN_VIC 29U 23 24 24 25 #endif
+1
include/dt-bindings/reset/tegra234-reset.h
··· 30 30 #define TEGRA234_RESET_I2C7 33U 31 31 #define TEGRA234_RESET_I2C8 34U 32 32 #define TEGRA234_RESET_I2C9 35U 33 + #define TEGRA234_RESET_NVDEC 44U 33 34 #define TEGRA234_RESET_MGBE0_PCS 45U 34 35 #define TEGRA234_RESET_MGBE0_MAC 46U 35 36 #define TEGRA234_RESET_MGBE1_PCS 49U