Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-08-02-1' of git://anongit.freedesktop.org/drm/drm
Pull more drm fixes from Daniel Vetter:
"Dave sends his pull, everyone realizes they've been asleep at the
wheel and hits send on their own pulls :-/
Normally I'd just ignore these all because w/e for me and Dave. But
this time around the latecomers also included drm-intel-fixes, which
failed to send out a -fixes pull thus far for this release (screwed up
vacation coverage, despite that 2/3 maintainers were around ... they
all look appropriately guilty), and that really is overdue to get
landed.
And since I had to do a pull request anyway I pulled the other two
late ones too.
intel fixes (didn't have any ever since the main merge window pull):
- gvt fixes (2 cc: stable)
- fix gpu reset vs mm-shrinker vs wakeup fun (needed a few patches)
- two gem locking fixes (one cc: stable)
- pile of misc fixes all over with minor impact, 6 cc: stable, others
from this window
exynos:
- misc minor fixes
misc:
- some build/Kconfig fixes
- regression fix for vm scalability perf test which seems to mostly
exercise dmesg/console logging ...
- the vgem cache flush fix for arm64 broke the world on x86, so
that's reverted again
* tag 'drm-fixes-2019-08-02-1' of git://anongit.freedesktop.org/drm/drm: (42 commits)
Revert "drm/vgem: fix cache synchronization on arm/arm64"
drm/exynos: fix missing decrement of retry counter
drm/exynos: add CONFIG_MMU dependency
drm/exynos: remove redundant assignment to pointer 'node'
drm/exynos: using dev_get_drvdata directly
drm/bochs: Use shadow buffer for bochs framebuffer console
drm/fb-helper: Instanciate shadow FB if configured in device's mode_config
drm/fb-helper: Map DRM client buffer only when required
drm/client: Support unmapping of DRM client buffers
drm/i915: Only recover active engines
drm/i915: Add a wakeref getter for iff the wakeref is already active
drm/i915: Lift intel_engines_resume() to callers
drm/vgem: fix cache synchronization on arm/arm64
drm/i810: Use CONFIG_PREEMPTION
drm/bridge: tc358764: Fix build error
drm/bridge: lvds-encoder: Fix build error while CONFIG_DRM_KMS_HELPER=m
drm/i915/gvt: Adding ppgtt to GVT GEM context after shadow pdps settled.
drm/i915/gvt: grab runtime pm first for forcewake use
drm/i915/gvt: fix incorrect cache entry for guest page mapping
drm/i915/gvt: Checking workload's gma earlier
...
+527
-257
+1
-1
drivers/gpu/drm/Kconfig
+1
-1
drivers/gpu/drm/Kconfig
···
394
394
config DRM_I810
395
395
tristate "Intel I810"
396
396
# !PREEMPT because of missing ioctl locking
397
-
depends on DRM && AGP && AGP_INTEL && (!PREEMPT || BROKEN)
397
+
depends on DRM && AGP && AGP_INTEL && (!PREEMPTION || BROKEN)
398
398
help
399
399
Choose this option if you have an Intel I810 graphics card. If M is
400
400
selected, the module will be called i810. AGP support is required
+1
drivers/gpu/drm/bochs/bochs_kms.c
+1
drivers/gpu/drm/bochs/bochs_kms.c
···
191
191
bochs->dev->mode_config.fb_base = bochs->fb_base;
192
192
bochs->dev->mode_config.preferred_depth = 24;
193
193
bochs->dev->mode_config.prefer_shadow = 0;
194
+
bochs->dev->mode_config.prefer_shadow_fbdev = 1;
194
195
bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
195
196
196
197
bochs->dev->mode_config.funcs = &bochs_mode_funcs;
+3
-1
drivers/gpu/drm/bridge/Kconfig
+3
-1
drivers/gpu/drm/bridge/Kconfig
···
48
48
config DRM_LVDS_ENCODER
49
49
tristate "Transparent parallel to LVDS encoder support"
50
50
depends on OF
51
+
select DRM_KMS_HELPER
51
52
select DRM_PANEL_BRIDGE
52
53
help
53
54
Support for transparent parallel to LVDS encoders that don't require
···
117
116
118
117
config DRM_TOSHIBA_TC358764
119
118
tristate "TC358764 DSI/LVDS bridge"
120
-
depends on DRM && DRM_PANEL
121
119
depends on OF
122
120
select DRM_MIPI_DSI
121
+
select DRM_KMS_HELPER
122
+
select DRM_PANEL
123
123
help
124
124
Toshiba TC358764 DSI/LVDS bridge driver.
125
125
+50
-12
drivers/gpu/drm/drm_client.c
+50
-12
drivers/gpu/drm/drm_client.c
···
254
254
struct drm_device *dev = client->dev;
255
255
struct drm_client_buffer *buffer;
256
256
struct drm_gem_object *obj;
257
-
void *vaddr;
258
257
int ret;
259
258
260
259
buffer = kzalloc(sizeof(*buffer), GFP_KERNEL);
···
280
281
281
282
buffer->gem = obj;
282
283
284
+
return buffer;
285
+
286
+
err_delete:
287
+
drm_client_buffer_delete(buffer);
288
+
289
+
return ERR_PTR(ret);
290
+
}
291
+
292
+
/**
293
+
* drm_client_buffer_vmap - Map DRM client buffer into address space
294
+
* @buffer: DRM client buffer
295
+
*
296
+
* This function maps a client buffer into kernel address space. If the
297
+
* buffer is already mapped, it returns the mapping's address.
298
+
*
299
+
* Client buffer mappings are not ref'counted. Each call to
300
+
* drm_client_buffer_vmap() should be followed by a call to
301
+
* drm_client_buffer_vunmap(); or the client buffer should be mapped
302
+
* throughout its lifetime.
303
+
*
304
+
* Returns:
305
+
* The mapped memory's address
306
+
*/
307
+
void *drm_client_buffer_vmap(struct drm_client_buffer *buffer)
308
+
{
309
+
void *vaddr;
310
+
311
+
if (buffer->vaddr)
312
+
return buffer->vaddr;
313
+
283
314
/*
284
315
* FIXME: The dependency on GEM here isn't required, we could
285
316
* convert the driver handle to a dma-buf instead and use the
···
318
289
* fd_install step out of the driver backend hooks, to make that
319
290
* final step optional for internal users.
320
291
*/
321
-
vaddr = drm_gem_vmap(obj);
322
-
if (IS_ERR(vaddr)) {
323
-
ret = PTR_ERR(vaddr);
324
-
goto err_delete;
325
-
}
292
+
vaddr = drm_gem_vmap(buffer->gem);
293
+
if (IS_ERR(vaddr))
294
+
return vaddr;
326
295
327
296
buffer->vaddr = vaddr;
328
297
329
-
return buffer;
330
-
331
-
err_delete:
332
-
drm_client_buffer_delete(buffer);
333
-
334
-
return ERR_PTR(ret);
298
+
return vaddr;
335
299
}
300
+
EXPORT_SYMBOL(drm_client_buffer_vmap);
301
+
302
+
/**
303
+
* drm_client_buffer_vunmap - Unmap DRM client buffer
304
+
* @buffer: DRM client buffer
305
+
*
306
+
* This function removes a client buffer's memory mapping. Calling this
307
+
* function is only required by clients that manage their buffer mappings
308
+
* by themselves.
309
+
*/
310
+
void drm_client_buffer_vunmap(struct drm_client_buffer *buffer)
311
+
{
312
+
drm_gem_vunmap(buffer->gem, buffer->vaddr);
313
+
buffer->vaddr = NULL;
314
+
}
315
+
EXPORT_SYMBOL(drm_client_buffer_vunmap);
336
316
337
317
static void drm_client_buffer_rmfb(struct drm_client_buffer *buffer)
338
318
{
+40
-11
drivers/gpu/drm/drm_fb_helper.c
+40
-11
drivers/gpu/drm/drm_fb_helper.c
···
403
403
struct drm_clip_rect *clip = &helper->dirty_clip;
404
404
struct drm_clip_rect clip_copy;
405
405
unsigned long flags;
406
+
void *vaddr;
406
407
407
408
spin_lock_irqsave(&helper->dirty_lock, flags);
408
409
clip_copy = *clip;
···
413
412
414
413
/* call dirty callback only when it has been really touched */
415
414
if (clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2) {
415
+
416
416
/* Generic fbdev uses a shadow buffer */
417
-
if (helper->buffer)
417
+
if (helper->buffer) {
418
+
vaddr = drm_client_buffer_vmap(helper->buffer);
419
+
if (IS_ERR(vaddr))
420
+
return;
418
421
drm_fb_helper_dirty_blit_real(helper, &clip_copy);
419
-
helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1);
422
+
}
423
+
if (helper->fb->funcs->dirty)
424
+
helper->fb->funcs->dirty(helper->fb, NULL, 0, 0,
425
+
&clip_copy, 1);
426
+
427
+
if (helper->buffer)
428
+
drm_client_buffer_vunmap(helper->buffer);
420
429
}
421
430
}
422
431
···
615
604
}
616
605
EXPORT_SYMBOL(drm_fb_helper_unlink_fbi);
617
606
607
+
static bool drm_fbdev_use_shadow_fb(struct drm_fb_helper *fb_helper)
608
+
{
609
+
struct drm_device *dev = fb_helper->dev;
610
+
struct drm_framebuffer *fb = fb_helper->fb;
611
+
612
+
return dev->mode_config.prefer_shadow_fbdev ||
613
+
dev->mode_config.prefer_shadow ||
614
+
fb->funcs->dirty;
615
+
}
616
+
618
617
static void drm_fb_helper_dirty(struct fb_info *info, u32 x, u32 y,
619
618
u32 width, u32 height)
620
619
{
···
632
611
struct drm_clip_rect *clip = &helper->dirty_clip;
633
612
unsigned long flags;
634
613
635
-
if (!helper->fb->funcs->dirty)
614
+
if (!drm_fbdev_use_shadow_fb(helper))
636
615
return;
637
616
638
617
spin_lock_irqsave(&helper->dirty_lock, flags);
···
2199
2178
struct drm_framebuffer *fb;
2200
2179
struct fb_info *fbi;
2201
2180
u32 format;
2181
+
void *vaddr;
2202
2182
2203
2183
DRM_DEBUG_KMS("surface width(%d), height(%d) and bpp(%d)\n",
2204
2184
sizes->surface_width, sizes->surface_height,
···
2222
2200
fbi->fbops = &drm_fbdev_fb_ops;
2223
2201
fbi->screen_size = fb->height * fb->pitches[0];
2224
2202
fbi->fix.smem_len = fbi->screen_size;
2225
-
fbi->screen_buffer = buffer->vaddr;
2226
-
/* Shamelessly leak the physical address to user-space */
2227
-
#if IS_ENABLED(CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM)
2228
-
if (drm_leak_fbdev_smem && fbi->fix.smem_start == 0)
2229
-
fbi->fix.smem_start =
2230
-
page_to_phys(virt_to_page(fbi->screen_buffer));
2231
-
#endif
2203
+
2232
2204
drm_fb_helper_fill_info(fbi, fb_helper, sizes);
2233
2205
2234
-
if (fb->funcs->dirty) {
2206
+
if (drm_fbdev_use_shadow_fb(fb_helper)) {
2235
2207
struct fb_ops *fbops;
2236
2208
void *shadow;
2237
2209
···
2247
2231
fbi->fbdefio = &drm_fbdev_defio;
2248
2232
2249
2233
fb_deferred_io_init(fbi);
2234
+
} else {
2235
+
/* buffer is mapped for HW framebuffer */
2236
+
vaddr = drm_client_buffer_vmap(fb_helper->buffer);
2237
+
if (IS_ERR(vaddr))
2238
+
return PTR_ERR(vaddr);
2239
+
2240
+
fbi->screen_buffer = vaddr;
2241
+
/* Shamelessly leak the physical address to user-space */
2242
+
#if IS_ENABLED(CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM)
2243
+
if (drm_leak_fbdev_smem && fbi->fix.smem_start == 0)
2244
+
fbi->fix.smem_start =
2245
+
page_to_phys(virt_to_page(fbi->screen_buffer));
2246
+
#endif
2250
2247
}
2251
2248
2252
2249
return 0;
+1
drivers/gpu/drm/exynos/Kconfig
+1
drivers/gpu/drm/exynos/Kconfig
···
2
2
config DRM_EXYNOS
3
3
tristate "DRM Support for Samsung SoC EXYNOS Series"
4
4
depends on OF && DRM && (ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS || ARCH_MULTIPLATFORM || COMPILE_TEST)
5
+
depends on MMU
5
6
select DRM_KMS_HELPER
6
7
select VIDEOMODE_HELPERS
7
8
select SND_SOC_HDMI_CODEC if SND_SOC
+1
-1
drivers/gpu/drm/exynos/exynos_drm_fimc.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_fimc.c
···
44
44
module_param_named(fimc_devs, fimc_mask, uint, 0644);
45
45
MODULE_PARM_DESC(fimc_devs, "Alias mask for assigning FIMC devices to Exynos DRM");
46
46
47
-
#define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
47
+
#define get_fimc_context(dev) dev_get_drvdata(dev)
48
48
49
49
enum {
50
50
FIMC_CLK_LCLK,
+1
-1
drivers/gpu/drm/exynos/exynos_drm_g2d.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_g2d.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
+1
-1
drivers/gpu/drm/exynos/exynos_drm_gsc.c
···
58
58
#define GSC_COEF_DEPTH 3
59
59
#define GSC_AUTOSUSPEND_DELAY 2000
60
60
61
-
#define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
61
+
#define get_gsc_context(dev) dev_get_drvdata(dev)
62
62
#define gsc_read(offset) readl(ctx->regs + (offset))
63
63
#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
64
64
+2
-2
drivers/gpu/drm/exynos/exynos_drm_scaler.c
+2
-2
drivers/gpu/drm/exynos/exynos_drm_scaler.c
···
94
94
scaler_write(SCALER_CFG_SOFT_RESET, SCALER_CFG);
95
95
do {
96
96
cpu_relax();
97
-
} while (retry > 1 &&
97
+
} while (--retry > 1 &&
98
98
scaler_read(SCALER_CFG) & SCALER_CFG_SOFT_RESET);
99
99
do {
100
100
cpu_relax();
101
101
scaler_write(1, SCALER_INT_EN);
102
-
} while (retry > 0 && scaler_read(SCALER_INT_EN) != 1);
102
+
} while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1);
103
103
104
104
return retry ? 0 : -EIO;
105
105
}
+1
-1
drivers/gpu/drm/i915/display/intel_bios.c
+1
-1
drivers/gpu/drm/i915/display/intel_bios.c
+10
-5
drivers/gpu/drm/i915/display/intel_bw.c
+10
-5
drivers/gpu/drm/i915/display/intel_bw.c
···
178
178
clpchgroup = (sa->deburst * deinterleave / num_channels) << i;
179
179
bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
180
180
181
+
bi->num_qgv_points = qi.num_points;
182
+
181
183
for (j = 0; j < qi.num_points; j++) {
182
184
const struct intel_qgv_point *sp = &qi.points[j];
183
185
int ct, bw;
···
197
195
bi->deratedbw[j] = min(maxdebw,
198
196
bw * 9 / 10); /* 90% */
199
197
200
-
DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%d\n",
198
+
DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
201
199
i, j, bi->num_planes, bi->deratedbw[j]);
202
200
}
203
201
···
213
211
{
214
212
int i;
215
213
216
-
/* Did we initialize the bw limits successfully? */
217
-
if (dev_priv->max_bw[0].num_planes == 0)
218
-
return UINT_MAX;
219
-
220
214
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
221
215
const struct intel_bw_info *bi =
222
216
&dev_priv->max_bw[i];
217
+
218
+
/*
219
+
* Pcode will not expose all QGV points when
220
+
* SAGV is forced to off/min/med/max.
221
+
*/
222
+
if (qgv_point >= bi->num_qgv_points)
223
+
return UINT_MAX;
223
224
224
225
if (num_planes >= bi->num_planes)
225
226
return bi->deratedbw[qgv_point];
+11
drivers/gpu/drm/i915/display/intel_cdclk.c
+11
drivers/gpu/drm/i915/display/intel_cdclk.c
···
2240
2240
min_cdclk = max(2 * 96000, min_cdclk);
2241
2241
2242
2242
/*
2243
+
* "For DP audio configuration, cdclk frequency shall be set to
2244
+
* meet the following requirements:
2245
+
* DP Link Frequency(MHz) | Cdclk frequency(MHz)
2246
+
* 270 | 320 or higher
2247
+
* 162 | 200 or higher"
2248
+
*/
2249
+
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2250
+
intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2251
+
min_cdclk = max(crtc_state->port_clock, min_cdclk);
2252
+
2253
+
/*
2243
2254
* On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2244
2255
* than 320000KHz.
2245
2256
*/
+2
-2
drivers/gpu/drm/i915/display/intel_display.c
+2
-2
drivers/gpu/drm/i915/display/intel_display.c
···
1839
1839
/* FIXME: assert CPU port conditions for SNB+ */
1840
1840
}
1841
1841
1842
-
trace_intel_pipe_enable(dev_priv, pipe);
1842
+
trace_intel_pipe_enable(crtc);
1843
1843
1844
1844
reg = PIPECONF(cpu_transcoder);
1845
1845
val = I915_READ(reg);
···
1880
1880
*/
1881
1881
assert_planes_disabled(crtc);
1882
1882
1883
-
trace_intel_pipe_disable(dev_priv, pipe);
1883
+
trace_intel_pipe_disable(crtc);
1884
1884
1885
1885
reg = PIPECONF(cpu_transcoder);
1886
1886
val = I915_READ(reg);
+9
-2
drivers/gpu/drm/i915/display/intel_display_power.c
+9
-2
drivers/gpu/drm/i915/display/intel_display_power.c
···
438
438
#define ICL_AUX_PW_TO_CH(pw_idx) \
439
439
((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
440
440
441
+
#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
442
+
((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
443
+
441
444
static void
442
445
icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
443
446
struct i915_power_well *power_well)
444
447
{
445
-
enum aux_ch aux_ch = ICL_AUX_PW_TO_CH(power_well->desc->hsw.idx);
448
+
int pw_idx = power_well->desc->hsw.idx;
449
+
bool is_tbt = power_well->desc->hsw.is_tc_tbt;
450
+
enum aux_ch aux_ch;
446
451
u32 val;
447
452
453
+
aux_ch = is_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
454
+
ICL_AUX_PW_TO_CH(pw_idx);
448
455
val = I915_READ(DP_AUX_CH_CTL(aux_ch));
449
456
val &= ~DP_AUX_CH_CTL_TBT_IO;
450
-
if (power_well->desc->hsw.is_tc_tbt)
457
+
if (is_tbt)
451
458
val |= DP_AUX_CH_CTL_TBT_IO;
452
459
I915_WRITE(DP_AUX_CH_CTL(aux_ch), val);
453
460
+3
-3
drivers/gpu/drm/i915/display/intel_vbt_defs.h
+3
-3
drivers/gpu/drm/i915/display/intel_vbt_defs.h
···
478
478
/* TP wake up time in multiple of 100 */
479
479
u16 tp1_wakeup_time;
480
480
u16 tp2_tp3_wakeup_time;
481
-
482
-
/* PSR2 TP2/TP3 wakeup time for 16 panels */
483
-
u32 psr2_tp2_tp3_wakeup_time;
484
481
} __packed;
485
482
486
483
struct bdb_psr {
487
484
struct psr_table psr_table[16];
485
+
486
+
/* PSR2 TP2/TP3 wakeup time for 16 panels */
487
+
u32 psr2_tp2_tp3_wakeup_time;
488
488
} __packed;
489
489
490
490
/*
+4
-3
drivers/gpu/drm/i915/gem/i915_gem_pm.c
+4
-3
drivers/gpu/drm/i915/gem/i915_gem_pm.c
···
253
253
i915_gem_restore_gtt_mappings(i915);
254
254
i915_gem_restore_fences(i915);
255
255
256
+
if (i915_gem_init_hw(i915))
257
+
goto err_wedged;
258
+
256
259
/*
257
260
* As we didn't flush the kernel context before suspend, we cannot
258
261
* guarantee that the context image is complete. So let's just reset
259
262
* it and start again.
260
263
*/
261
-
intel_gt_resume(i915);
262
-
263
-
if (i915_gem_init_hw(i915))
264
+
if (intel_gt_resume(i915))
264
265
goto err_wedged;
265
266
266
267
intel_uc_resume(i915);
+9
-1
drivers/gpu/drm/i915/gem/i915_gem_userptr.c
+9
-1
drivers/gpu/drm/i915/gem/i915_gem_userptr.c
···
664
664
665
665
for_each_sgt_page(page, sgt_iter, pages) {
666
666
if (obj->mm.dirty)
667
-
set_page_dirty(page);
667
+
/*
668
+
* As this may not be anonymous memory (e.g. shmem)
669
+
* but exist on a real mapping, we have to lock
670
+
* the page in order to dirty it -- holding
671
+
* the page reference is not sufficient to
672
+
* prevent the inode from being truncated.
673
+
* Play safe and take the lock.
674
+
*/
675
+
set_page_dirty_lock(page);
668
676
669
677
mark_page_accessed(page);
670
678
put_page(page);
+18
-9
drivers/gpu/drm/i915/gt/intel_context.c
+18
-9
drivers/gpu/drm/i915/gt/intel_context.c
···
126
126
if (ce->state)
127
127
__context_unpin_state(ce->state);
128
128
129
+
intel_ring_unpin(ce->ring);
129
130
intel_context_put(ce);
130
131
}
131
132
···
161
160
162
161
intel_context_get(ce);
163
162
163
+
err = intel_ring_pin(ce->ring);
164
+
if (err)
165
+
goto err_put;
166
+
164
167
if (!ce->state)
165
168
return 0;
166
169
167
170
err = __context_pin_state(ce->state, flags);
168
-
if (err) {
169
-
i915_active_cancel(&ce->active);
170
-
intel_context_put(ce);
171
-
return err;
172
-
}
171
+
if (err)
172
+
goto err_ring;
173
173
174
174
/* Preallocate tracking nodes */
175
175
if (!i915_gem_context_is_kernel(ce->gem_context)) {
176
176
err = i915_active_acquire_preallocate_barrier(&ce->active,
177
177
ce->engine);
178
-
if (err) {
179
-
i915_active_release(&ce->active);
180
-
return err;
181
-
}
178
+
if (err)
179
+
goto err_state;
182
180
}
183
181
184
182
return 0;
183
+
184
+
err_state:
185
+
__context_unpin_state(ce->state);
186
+
err_ring:
187
+
intel_ring_unpin(ce->ring);
188
+
err_put:
189
+
intel_context_put(ce);
190
+
i915_active_cancel(&ce->active);
191
+
return err;
185
192
}
186
193
187
194
void intel_context_active_release(struct intel_context *ce)
+11
-9
drivers/gpu/drm/i915/gt/intel_engine_cs.c
+11
-9
drivers/gpu/drm/i915/gt/intel_engine_cs.c
···
969
969
u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv)
970
970
{
971
971
const struct sseu_dev_info *sseu = &RUNTIME_INFO(dev_priv)->sseu;
972
+
unsigned int slice = fls(sseu->slice_mask) - 1;
973
+
unsigned int subslice;
972
974
u32 mcr_s_ss_select;
973
-
u32 slice = fls(sseu->slice_mask);
974
-
u32 subslice = fls(sseu->subslice_mask[slice]);
975
+
976
+
GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask));
977
+
subslice = fls(sseu->subslice_mask[slice]);
978
+
GEM_BUG_ON(!subslice);
979
+
subslice--;
975
980
976
981
if (IS_GEN(dev_priv, 10))
977
982
mcr_s_ss_select = GEN8_MCR_SLICE(slice) |
···
1476
1471
struct i915_gpu_error * const error = &engine->i915->gpu_error;
1477
1472
struct i915_request *rq;
1478
1473
intel_wakeref_t wakeref;
1474
+
unsigned long flags;
1479
1475
1480
1476
if (header) {
1481
1477
va_list ap;
···
1496
1490
i915_reset_engine_count(error, engine),
1497
1491
i915_reset_count(error));
1498
1492
1499
-
rcu_read_lock();
1500
-
1501
1493
drm_printf(m, "\tRequests:\n");
1502
1494
1495
+
spin_lock_irqsave(&engine->active.lock, flags);
1503
1496
rq = intel_engine_find_active_request(engine);
1504
1497
if (rq) {
1505
1498
print_request(m, rq, "\t\tactive ");
···
1518
1513
1519
1514
print_request_ring(m, rq);
1520
1515
}
1521
-
1522
-
rcu_read_unlock();
1516
+
spin_unlock_irqrestore(&engine->active.lock, flags);
1523
1517
1524
1518
wakeref = intel_runtime_pm_get_if_in_use(&engine->i915->runtime_pm);
1525
1519
if (wakeref) {
···
1676
1672
intel_engine_find_active_request(struct intel_engine_cs *engine)
1677
1673
{
1678
1674
struct i915_request *request, *active = NULL;
1679
-
unsigned long flags;
1680
1675
1681
1676
/*
1682
1677
* We are called by the error capture, reset and to dump engine
···
1688
1685
* At all other times, we must assume the GPU is still running, but
1689
1686
* we only care about the snapshot of this moment.
1690
1687
*/
1691
-
spin_lock_irqsave(&engine->active.lock, flags);
1688
+
lockdep_assert_held(&engine->active.lock);
1692
1689
list_for_each_entry(request, &engine->active.requests, sched.link) {
1693
1690
if (i915_request_completed(request))
1694
1691
continue;
···
1703
1700
active = request;
1704
1701
break;
1705
1702
}
1706
-
spin_unlock_irqrestore(&engine->active.lock, flags);
1707
1703
1708
1704
return active;
1709
1705
}
-24
drivers/gpu/drm/i915/gt/intel_engine_pm.c
-24
drivers/gpu/drm/i915/gt/intel_engine_pm.c
···
142
142
{
143
143
intel_wakeref_init(&engine->wakeref);
144
144
}
145
-
146
-
int intel_engines_resume(struct drm_i915_private *i915)
147
-
{
148
-
struct intel_engine_cs *engine;
149
-
enum intel_engine_id id;
150
-
int err = 0;
151
-
152
-
intel_gt_pm_get(i915);
153
-
for_each_engine(engine, i915, id) {
154
-
intel_engine_pm_get(engine);
155
-
engine->serial++; /* kernel context lost */
156
-
err = engine->resume(engine);
157
-
intel_engine_pm_put(engine);
158
-
if (err) {
159
-
dev_err(i915->drm.dev,
160
-
"Failed to restart %s (%d)\n",
161
-
engine->name, err);
162
-
break;
163
-
}
164
-
}
165
-
intel_gt_pm_put(i915);
166
-
167
-
return err;
168
-
}
+9
-3
drivers/gpu/drm/i915/gt/intel_engine_pm.h
+9
-3
drivers/gpu/drm/i915/gt/intel_engine_pm.h
···
7
7
#ifndef INTEL_ENGINE_PM_H
8
8
#define INTEL_ENGINE_PM_H
9
9
10
+
#include "intel_engine_types.h"
11
+
#include "intel_wakeref.h"
12
+
10
13
struct drm_i915_private;
11
-
struct intel_engine_cs;
12
14
13
15
void intel_engine_pm_get(struct intel_engine_cs *engine);
14
16
void intel_engine_pm_put(struct intel_engine_cs *engine);
15
17
18
+
static inline bool
19
+
intel_engine_pm_get_if_awake(struct intel_engine_cs *engine)
20
+
{
21
+
return intel_wakeref_get_if_active(&engine->wakeref);
22
+
}
23
+
16
24
void intel_engine_park(struct intel_engine_cs *engine);
17
25
18
26
void intel_engine_init__pm(struct intel_engine_cs *engine);
19
-
20
-
int intel_engines_resume(struct drm_i915_private *i915);
21
27
22
28
#endif /* INTEL_ENGINE_PM_H */
+12
drivers/gpu/drm/i915/gt/intel_engine_types.h
+12
drivers/gpu/drm/i915/gt/intel_engine_types.h
···
70
70
struct list_head request_list;
71
71
struct list_head active_link;
72
72
73
+
/*
74
+
* As we have two types of rings, one global to the engine used
75
+
* by ringbuffer submission and those that are exclusive to a
76
+
* context used by execlists, we have to play safe and allow
77
+
* atomic updates to the pin_count. However, the actual pinning
78
+
* of the context is either done during initialisation for
79
+
* ringbuffer submission or serialised as part of the context
80
+
* pinning for execlists, and so we do not need a mutex ourselves
81
+
* to serialise intel_ring_pin/intel_ring_unpin.
82
+
*/
83
+
atomic_t pin_count;
84
+
73
85
u32 head;
74
86
u32 tail;
75
87
u32 emit;
+20
-1
drivers/gpu/drm/i915/gt/intel_gt_pm.c
+20
-1
drivers/gpu/drm/i915/gt/intel_gt_pm.c
···
5
5
*/
6
6
7
7
#include "i915_drv.h"
8
+
#include "intel_engine_pm.h"
8
9
#include "intel_gt_pm.h"
9
10
#include "intel_pm.h"
10
11
#include "intel_wakeref.h"
···
119
118
intel_engine_reset(engine, false);
120
119
}
121
120
122
-
void intel_gt_resume(struct drm_i915_private *i915)
121
+
int intel_gt_resume(struct drm_i915_private *i915)
123
122
{
124
123
struct intel_engine_cs *engine;
125
124
enum intel_engine_id id;
125
+
int err = 0;
126
126
127
127
/*
128
128
* After resume, we may need to poke into the pinned kernel
···
131
129
* Only the kernel contexts should remain pinned over suspend,
132
130
* allowing us to fixup the user contexts on their first pin.
133
131
*/
132
+
intel_gt_pm_get(i915);
134
133
for_each_engine(engine, i915, id) {
135
134
struct intel_context *ce;
135
+
136
+
intel_engine_pm_get(engine);
136
137
137
138
ce = engine->kernel_context;
138
139
if (ce)
···
144
139
ce = engine->preempt_context;
145
140
if (ce)
146
141
ce->ops->reset(ce);
142
+
143
+
engine->serial++; /* kernel context lost */
144
+
err = engine->resume(engine);
145
+
146
+
intel_engine_pm_put(engine);
147
+
if (err) {
148
+
dev_err(i915->drm.dev,
149
+
"Failed to restart %s (%d)\n",
150
+
engine->name, err);
151
+
break;
152
+
}
147
153
}
154
+
intel_gt_pm_put(i915);
155
+
156
+
return err;
148
157
}
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_pm.h
+1
-1
drivers/gpu/drm/i915/gt/intel_gt_pm.h
+2
-8
drivers/gpu/drm/i915/gt/intel_lrc.c
+2
-8
drivers/gpu/drm/i915/gt/intel_lrc.c
···
1414
1414
{
1415
1415
struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1416
1416
1417
+
GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1417
1418
GEM_BUG_ON(intel_context_is_pinned(ce));
1418
1419
1419
1420
if (ce->state)
···
1427
1426
{
1428
1427
i915_gem_context_unpin_hw_id(ce->gem_context);
1429
1428
i915_gem_object_unpin_map(ce->state->obj);
1430
-
intel_ring_unpin(ce->ring);
1431
1429
}
1432
1430
1433
1431
static void
···
1478
1478
goto unpin_active;
1479
1479
}
1480
1480
1481
-
ret = intel_ring_pin(ce->ring);
1482
-
if (ret)
1483
-
goto unpin_map;
1484
-
1485
1481
ret = i915_gem_context_pin_hw_id(ce->gem_context);
1486
1482
if (ret)
1487
-
goto unpin_ring;
1483
+
goto unpin_map;
1488
1484
1489
1485
ce->lrc_desc = lrc_descriptor(ce, engine);
1490
1486
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
···
1488
1492
1489
1493
return 0;
1490
1494
1491
-
unpin_ring:
1492
-
intel_ring_unpin(ce->ring);
1493
1495
unpin_map:
1494
1496
i915_gem_object_unpin_map(ce->state->obj);
1495
1497
unpin_active:
+42
-16
drivers/gpu/drm/i915/gt/intel_reset.c
+42
-16
drivers/gpu/drm/i915/gt/intel_reset.c
···
687
687
* written to the powercontext is undefined and so we may lose
688
688
* GPU state upon resume, i.e. fail to restart after a reset.
689
689
*/
690
-
intel_engine_pm_get(engine);
691
690
intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
692
691
engine->reset.prepare(engine);
693
692
}
···
717
718
}
718
719
}
719
720
720
-
static void reset_prepare(struct drm_i915_private *i915)
721
+
static intel_engine_mask_t reset_prepare(struct drm_i915_private *i915)
721
722
{
722
723
struct intel_engine_cs *engine;
724
+
intel_engine_mask_t awake = 0;
723
725
enum intel_engine_id id;
724
726
725
-
intel_gt_pm_get(i915);
726
-
for_each_engine(engine, i915, id)
727
+
for_each_engine(engine, i915, id) {
728
+
if (intel_engine_pm_get_if_awake(engine))
729
+
awake |= engine->mask;
727
730
reset_prepare_engine(engine);
731
+
}
728
732
729
733
intel_uc_reset_prepare(i915);
734
+
735
+
return awake;
730
736
}
731
737
732
738
static void gt_revoke(struct drm_i915_private *i915)
···
765
761
static void reset_finish_engine(struct intel_engine_cs *engine)
766
762
{
767
763
engine->reset.finish(engine);
768
-
intel_engine_pm_put(engine);
769
764
intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
765
+
766
+
intel_engine_signal_breadcrumbs(engine);
770
767
}
771
768
772
-
static void reset_finish(struct drm_i915_private *i915)
769
+
static void reset_finish(struct drm_i915_private *i915,
770
+
intel_engine_mask_t awake)
773
771
{
774
772
struct intel_engine_cs *engine;
775
773
enum intel_engine_id id;
776
774
777
775
for_each_engine(engine, i915, id) {
778
776
reset_finish_engine(engine);
779
-
intel_engine_signal_breadcrumbs(engine);
777
+
if (awake & engine->mask)
778
+
intel_engine_pm_put(engine);
780
779
}
781
-
intel_gt_pm_put(i915);
782
780
}
783
781
784
782
static void nop_submit_request(struct i915_request *request)
···
804
798
{
805
799
struct i915_gpu_error *error = &i915->gpu_error;
806
800
struct intel_engine_cs *engine;
801
+
intel_engine_mask_t awake;
807
802
enum intel_engine_id id;
808
803
809
804
if (test_bit(I915_WEDGED, &error->flags))
···
824
817
* rolling the global seqno forward (since this would complete requests
825
818
* for which we haven't set the fence error to EIO yet).
826
819
*/
827
-
reset_prepare(i915);
820
+
awake = reset_prepare(i915);
828
821
829
822
/* Even if the GPU reset fails, it should still stop the engines */
830
823
if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
···
848
841
for_each_engine(engine, i915, id)
849
842
engine->cancel_requests(engine);
850
843
851
-
reset_finish(i915);
844
+
reset_finish(i915, awake);
852
845
853
846
GEM_TRACE("end\n");
854
847
}
···
958
951
return gt_reset(i915, stalled_mask);
959
952
}
960
953
954
+
static int resume(struct drm_i915_private *i915)
955
+
{
956
+
struct intel_engine_cs *engine;
957
+
enum intel_engine_id id;
958
+
int ret;
959
+
960
+
for_each_engine(engine, i915, id) {
961
+
ret = engine->resume(engine);
962
+
if (ret)
963
+
return ret;
964
+
}
965
+
966
+
return 0;
967
+
}
968
+
961
969
/**
962
970
* i915_reset - reset chip after a hang
963
971
* @i915: #drm_i915_private to reset
···
995
973
const char *reason)
996
974
{
997
975
struct i915_gpu_error *error = &i915->gpu_error;
976
+
intel_engine_mask_t awake;
998
977
int ret;
999
978
1000
979
GEM_TRACE("flags=%lx\n", error->flags);
···
1012
989
dev_notice(i915->drm.dev, "Resetting chip for %s\n", reason);
1013
990
error->reset_count++;
1014
991
1015
-
reset_prepare(i915);
992
+
awake = reset_prepare(i915);
1016
993
1017
994
if (!intel_has_gpu_reset(i915)) {
1018
995
if (i915_modparams.reset)
···
1047
1024
if (ret) {
1048
1025
DRM_ERROR("Failed to initialise HW following reset (%d)\n",
1049
1026
ret);
1050
-
goto error;
1027
+
goto taint;
1051
1028
}
1029
+
1030
+
ret = resume(i915);
1031
+
if (ret)
1032
+
goto taint;
1052
1033
1053
1034
i915_queue_hangcheck(i915);
1054
1035
1055
1036
finish:
1056
-
reset_finish(i915);
1037
+
reset_finish(i915, awake);
1057
1038
unlock:
1058
1039
mutex_unlock(&error->wedge_mutex);
1059
1040
return;
···
1108
1081
GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
1109
1082
GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
1110
1083
1111
-
if (!intel_wakeref_active(&engine->wakeref))
1084
+
if (!intel_engine_pm_get_if_awake(engine))
1112
1085
return 0;
1113
1086
1114
1087
reset_prepare_engine(engine);
···
1143
1116
* process to program RING_MODE, HWSP and re-enable submission.
1144
1117
*/
1145
1118
ret = engine->resume(engine);
1146
-
if (ret)
1147
-
goto out;
1148
1119
1149
1120
out:
1150
1121
intel_engine_cancel_stop_cs(engine);
1151
1122
reset_finish_engine(engine);
1123
+
intel_engine_pm_put(engine);
1152
1124
return ret;
1153
1125
}
1154
1126
+20
-11
drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+20
-11
drivers/gpu/drm/i915/gt/intel_ringbuffer.c
···
1149
1149
int intel_ring_pin(struct intel_ring *ring)
1150
1150
{
1151
1151
struct i915_vma *vma = ring->vma;
1152
-
enum i915_map_type map = i915_coherent_map_type(vma->vm->i915);
1153
1152
unsigned int flags;
1154
1153
void *addr;
1155
1154
int ret;
1156
1155
1157
-
GEM_BUG_ON(ring->vaddr);
1156
+
if (atomic_fetch_inc(&ring->pin_count))
1157
+
return 0;
1158
1158
1159
1159
ret = i915_timeline_pin(ring->timeline);
1160
1160
if (ret)
1161
-
return ret;
1161
+
goto err_unpin;
1162
1162
1163
1163
flags = PIN_GLOBAL;
1164
1164
···
1172
1172
1173
1173
ret = i915_vma_pin(vma, 0, 0, flags);
1174
1174
if (unlikely(ret))
1175
-
goto unpin_timeline;
1175
+
goto err_timeline;
1176
1176
1177
1177
if (i915_vma_is_map_and_fenceable(vma))
1178
1178
addr = (void __force *)i915_vma_pin_iomap(vma);
1179
1179
else
1180
-
addr = i915_gem_object_pin_map(vma->obj, map);
1180
+
addr = i915_gem_object_pin_map(vma->obj,
1181
+
i915_coherent_map_type(vma->vm->i915));
1181
1182
if (IS_ERR(addr)) {
1182
1183
ret = PTR_ERR(addr);
1183
-
goto unpin_ring;
1184
+
goto err_ring;
1184
1185
}
1185
1186
1186
1187
vma->obj->pin_global++;
1187
1188
1189
+
GEM_BUG_ON(ring->vaddr);
1188
1190
ring->vaddr = addr;
1191
+
1189
1192
return 0;
1190
1193
1191
-
unpin_ring:
1194
+
err_ring:
1192
1195
i915_vma_unpin(vma);
1193
-
unpin_timeline:
1196
+
err_timeline:
1194
1197
i915_timeline_unpin(ring->timeline);
1198
+
err_unpin:
1199
+
atomic_dec(&ring->pin_count);
1195
1200
return ret;
1196
1201
}
1197
1202
···
1212
1207
1213
1208
void intel_ring_unpin(struct intel_ring *ring)
1214
1209
{
1215
-
GEM_BUG_ON(!ring->vma);
1216
-
GEM_BUG_ON(!ring->vaddr);
1210
+
if (!atomic_dec_and_test(&ring->pin_count))
1211
+
return;
1217
1212
1218
1213
/* Discard any unused bytes beyond that submitted to hw. */
1219
1214
intel_ring_reset(ring, ring->tail);
1220
1215
1216
+
GEM_BUG_ON(!ring->vma);
1221
1217
if (i915_vma_is_map_and_fenceable(ring->vma))
1222
1218
i915_vma_unpin_iomap(ring->vma);
1223
1219
else
1224
1220
i915_gem_object_unpin_map(ring->vma->obj);
1221
+
1222
+
GEM_BUG_ON(!ring->vaddr);
1225
1223
ring->vaddr = NULL;
1226
1224
1227
1225
ring->vma->obj->pin_global--;
···
2089
2081
WARN_ON(INTEL_GEN(dev_priv) > 2 &&
2090
2082
(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
2091
2083
2084
+
intel_engine_cleanup_common(engine);
2085
+
2092
2086
intel_ring_unpin(engine->buffer);
2093
2087
intel_ring_put(engine->buffer);
2094
2088
2095
-
intel_engine_cleanup_common(engine);
2096
2089
kfree(engine);
2097
2090
}
2098
2091
+35
-3
drivers/gpu/drm/i915/gt/intel_workarounds.c
+35
-3
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
1098
1098
1099
1099
static void cfl_whitelist_build(struct intel_engine_cs *engine)
1100
1100
{
1101
+
struct i915_wa_list *w = &engine->whitelist;
1102
+
1101
1103
if (engine->class != RENDER_CLASS)
1102
1104
return;
1103
1105
1104
-
gen9_whitelist_build(&engine->whitelist);
1106
+
gen9_whitelist_build(w);
1107
+
1108
+
/*
1109
+
* WaAllowPMDepthAndInvocationCountAccessFromUMD:cfl,whl,cml,aml
1110
+
*
1111
+
* This covers 4 register which are next to one another :
1112
+
* - PS_INVOCATION_COUNT
1113
+
* - PS_INVOCATION_COUNT_UDW
1114
+
* - PS_DEPTH_COUNT
1115
+
* - PS_DEPTH_COUNT_UDW
1116
+
*/
1117
+
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1118
+
RING_FORCE_TO_NONPRIV_RD |
1119
+
RING_FORCE_TO_NONPRIV_RANGE_4);
1105
1120
}
1106
1121
1107
1122
static void cnl_whitelist_build(struct intel_engine_cs *engine)
···
1144
1129
1145
1130
/* WaEnableStateCacheRedirectToCS:icl */
1146
1131
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
1132
+
1133
+
/*
1134
+
* WaAllowPMDepthAndInvocationCountAccessFromUMD:icl
1135
+
*
1136
+
* This covers 4 register which are next to one another :
1137
+
* - PS_INVOCATION_COUNT
1138
+
* - PS_INVOCATION_COUNT_UDW
1139
+
* - PS_DEPTH_COUNT
1140
+
* - PS_DEPTH_COUNT_UDW
1141
+
*/
1142
+
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
1143
+
RING_FORCE_TO_NONPRIV_RD |
1144
+
RING_FORCE_TO_NONPRIV_RANGE_4);
1147
1145
break;
1148
1146
1149
1147
case VIDEO_DECODE_CLASS:
···
1286
1258
if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_B0))
1287
1259
wa_write_or(wal,
1288
1260
GEN7_SARCHKMD,
1289
-
GEN7_DISABLE_DEMAND_PREFETCH |
1290
-
GEN7_DISABLE_SAMPLER_PREFETCH);
1261
+
GEN7_DISABLE_DEMAND_PREFETCH);
1262
+
1263
+
/* Wa_1606682166:icl */
1264
+
wa_write_or(wal,
1265
+
GEN7_SARCHKMD,
1266
+
GEN7_DISABLE_SAMPLER_PREFETCH);
1291
1267
}
1292
1268
1293
1269
if (IS_GEN_RANGE(i915, 9, 11)) {
+1
drivers/gpu/drm/i915/gt/mock_engine.c
+1
drivers/gpu/drm/i915/gt/mock_engine.c
+4
-1
drivers/gpu/drm/i915/gt/selftest_reset.c
+4
-1
drivers/gpu/drm/i915/gt/selftest_reset.c
···
71
71
goto unlock;
72
72
73
73
for (p = igt_atomic_phases; p->name; p++) {
74
+
intel_engine_mask_t awake;
75
+
74
76
GEM_TRACE("intel_gpu_reset under %s\n", p->name);
75
77
78
+
awake = reset_prepare(i915);
76
79
p->critical_section_begin();
77
80
reset_prepare(i915);
78
81
err = intel_gpu_reset(i915, ALL_ENGINES);
79
-
reset_finish(i915);
80
82
p->critical_section_end();
83
+
reset_finish(i915, awake);
81
84
82
85
if (err) {
83
86
pr_err("intel_gpu_reset failed under %s\n", p->name);
+6
-1
drivers/gpu/drm/i915/gt/selftest_workarounds.c
+6
-1
drivers/gpu/drm/i915/gt/selftest_workarounds.c
···
925
925
926
926
err = 0;
927
927
for (i = 0; i < engine->whitelist.count; i++) {
928
-
if (!fn(engine, a[i], b[i], engine->whitelist.list[i].reg))
928
+
const struct i915_wa *wa = &engine->whitelist.list[i];
929
+
930
+
if (i915_mmio_reg_offset(wa->reg) & RING_FORCE_TO_NONPRIV_RD)
931
+
continue;
932
+
933
+
if (!fn(engine, a[i], b[i], wa->reg))
929
934
err = -EINVAL;
930
935
}
931
936
-10
drivers/gpu/drm/i915/gvt/cmd_parser.c
-10
drivers/gpu/drm/i915/gvt/cmd_parser.c
···
2674
2674
gma_head == gma_tail)
2675
2675
return 0;
2676
2676
2677
-
if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2678
-
ret = -EINVAL;
2679
-
goto out;
2680
-
}
2681
-
2682
2677
ret = ip_gma_set(&s, gma_head);
2683
2678
if (ret)
2684
2679
goto out;
···
2718
2723
s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2719
2724
s.workload = workload;
2720
2725
s.is_ctx_wa = true;
2721
-
2722
-
if (!intel_gvt_ggtt_validate_range(s.vgpu, s.ring_start, s.ring_size)) {
2723
-
ret = -EINVAL;
2724
-
goto out;
2725
-
}
2726
2726
2727
2727
ret = ip_gma_set(&s, gma_head);
2728
2728
if (ret)
+3
-3
drivers/gpu/drm/i915/gvt/fb_decoder.c
+3
-3
drivers/gpu/drm/i915/gvt/fb_decoder.c
···
245
245
plane->hw_format = fmt;
246
246
247
247
plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
248
-
if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
248
+
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
249
249
return -EINVAL;
250
250
251
251
plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
···
368
368
alpha_plane, alpha_force);
369
369
370
370
plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
371
-
if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
371
+
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
372
372
return -EINVAL;
373
373
374
374
plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
···
472
472
plane->drm_format = drm_format;
473
473
474
474
plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
475
-
if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
475
+
if (!vgpu_gmadr_is_valid(vgpu, plane->base))
476
476
return -EINVAL;
477
477
478
478
plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
+9
drivers/gpu/drm/i915/gvt/gtt.c
+9
drivers/gpu/drm/i915/gvt/gtt.c
···
2141
2141
struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2142
2142
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2143
2143
unsigned long index = off >> info->gtt_entry_size_shift;
2144
+
unsigned long gma;
2144
2145
struct intel_gvt_gtt_entry e;
2145
2146
2146
2147
if (bytes != 4 && bytes != 8)
2147
2148
return -EINVAL;
2149
+
2150
+
gma = index << I915_GTT_PAGE_SHIFT;
2151
+
if (!intel_gvt_ggtt_validate_range(vgpu,
2152
+
gma, 1 << I915_GTT_PAGE_SHIFT)) {
2153
+
gvt_dbg_mm("read invalid ggtt at 0x%lx\n", gma);
2154
+
memset(p_data, 0, bytes);
2155
+
return 0;
2156
+
}
2148
2157
2149
2158
ggtt_get_guest_entry(ggtt_mm, &e, index);
2150
2159
memcpy(p_data, (void *)&e.val64 + (off & (info->gtt_entry_size - 1)),
+12
drivers/gpu/drm/i915/gvt/kvmgt.c
+12
drivers/gpu/drm/i915/gvt/kvmgt.c
···
1911
1911
ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size);
1912
1912
if (ret)
1913
1913
goto err_unmap;
1914
+
} else if (entry->size != size) {
1915
+
/* the same gfn with different size: unmap and re-map */
1916
+
gvt_dma_unmap_page(vgpu, gfn, entry->dma_addr, entry->size);
1917
+
__gvt_cache_remove_entry(vgpu, entry);
1918
+
1919
+
ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size);
1920
+
if (ret)
1921
+
goto err_unlock;
1922
+
1923
+
ret = __gvt_cache_add(info->vgpu, gfn, *dma_addr, size);
1924
+
if (ret)
1925
+
goto err_unmap;
1914
1926
} else {
1915
1927
kref_get(&entry->ref);
1916
1928
*dma_addr = entry->dma_addr;
+44
-15
drivers/gpu/drm/i915/gvt/scheduler.c
+44
-15
drivers/gpu/drm/i915/gvt/scheduler.c
···
364
364
wa_ctx->indirect_ctx.shadow_va = NULL;
365
365
}
366
366
367
-
static int set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
368
-
struct i915_gem_context *ctx)
367
+
static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
368
+
struct i915_gem_context *ctx)
369
369
{
370
370
struct intel_vgpu_mm *mm = workload->shadow_mm;
371
371
struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ctx->vm);
372
372
int i = 0;
373
-
374
-
if (mm->type != INTEL_GVT_MM_PPGTT || !mm->ppgtt_mm.shadowed)
375
-
return -EINVAL;
376
373
377
374
if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
378
375
px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
···
381
384
px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
382
385
}
383
386
}
384
-
385
-
return 0;
386
387
}
387
388
388
389
static int
···
609
614
static int prepare_workload(struct intel_vgpu_workload *workload)
610
615
{
611
616
struct intel_vgpu *vgpu = workload->vgpu;
617
+
struct intel_vgpu_submission *s = &vgpu->submission;
618
+
int ring = workload->ring_id;
612
619
int ret = 0;
613
620
614
621
ret = intel_vgpu_pin_mm(workload->shadow_mm);
···
619
622
return ret;
620
623
}
621
624
625
+
if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
626
+
!workload->shadow_mm->ppgtt_mm.shadowed) {
627
+
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
628
+
return -EINVAL;
629
+
}
630
+
622
631
update_shadow_pdps(workload);
632
+
633
+
set_context_ppgtt_from_shadow(workload, s->shadow[ring]->gem_context);
623
634
624
635
ret = intel_vgpu_sync_oos_pages(workload->vgpu);
625
636
if (ret) {
···
679
674
{
680
675
struct intel_vgpu *vgpu = workload->vgpu;
681
676
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
682
-
struct intel_vgpu_submission *s = &vgpu->submission;
683
677
struct i915_request *rq;
684
678
int ring_id = workload->ring_id;
685
679
int ret;
···
688
684
689
685
mutex_lock(&vgpu->vgpu_lock);
690
686
mutex_lock(&dev_priv->drm.struct_mutex);
691
-
692
-
ret = set_context_ppgtt_from_shadow(workload,
693
-
s->shadow[ring_id]->gem_context);
694
-
if (ret < 0) {
695
-
gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
696
-
goto err_req;
697
-
}
698
687
699
688
ret = intel_gvt_workload_req_alloc(workload);
700
689
if (ret)
···
987
990
int ret;
988
991
bool need_force_wake = (INTEL_GEN(gvt->dev_priv) >= 9);
989
992
DEFINE_WAIT_FUNC(wait, woken_wake_function);
993
+
struct intel_runtime_pm *rpm = &gvt->dev_priv->runtime_pm;
990
994
991
995
kfree(p);
992
996
···
1010
1012
gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
1011
1013
workload->ring_id, workload,
1012
1014
workload->vgpu->id);
1015
+
1016
+
intel_runtime_pm_get(rpm);
1013
1017
1014
1018
gvt_dbg_sched("ring id %d will dispatch workload %p\n",
1015
1019
workload->ring_id, workload);
···
1042
1042
intel_uncore_forcewake_put(&gvt->dev_priv->uncore,
1043
1043
FORCEWAKE_ALL);
1044
1044
1045
+
intel_runtime_pm_put_unchecked(rpm);
1045
1046
if (ret && (vgpu_is_vm_unhealthy(ret)))
1046
1047
enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1047
1048
}
···
1493
1492
intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1494
1493
RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1495
1494
1495
+
if (!intel_gvt_ggtt_validate_range(vgpu, start,
1496
+
_RING_CTL_BUF_SIZE(ctl))) {
1497
+
gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1498
+
return ERR_PTR(-EINVAL);
1499
+
}
1500
+
1496
1501
workload = alloc_workload(vgpu);
1497
1502
if (IS_ERR(workload))
1498
1503
return workload;
···
1523
1516
workload->wa_ctx.indirect_ctx.size =
1524
1517
(indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1525
1518
CACHELINE_BYTES;
1519
+
1520
+
if (workload->wa_ctx.indirect_ctx.size != 0) {
1521
+
if (!intel_gvt_ggtt_validate_range(vgpu,
1522
+
workload->wa_ctx.indirect_ctx.guest_gma,
1523
+
workload->wa_ctx.indirect_ctx.size)) {
1524
+
kmem_cache_free(s->workloads, workload);
1525
+
gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1526
+
workload->wa_ctx.indirect_ctx.guest_gma);
1527
+
return ERR_PTR(-EINVAL);
1528
+
}
1529
+
}
1530
+
1526
1531
workload->wa_ctx.per_ctx.guest_gma =
1527
1532
per_ctx & PER_CTX_ADDR_MASK;
1528
1533
workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1534
+
if (workload->wa_ctx.per_ctx.valid) {
1535
+
if (!intel_gvt_ggtt_validate_range(vgpu,
1536
+
workload->wa_ctx.per_ctx.guest_gma,
1537
+
CACHELINE_BYTES)) {
1538
+
kmem_cache_free(s->workloads, workload);
1539
+
gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1540
+
workload->wa_ctx.per_ctx.guest_gma);
1541
+
return ERR_PTR(-EINVAL);
1542
+
}
1543
+
}
1529
1544
}
1530
1545
1531
1546
gvt_dbg_el("workload %p ring id %d head %x tail %x start %x ctl %x\n",
-2
drivers/gpu/drm/i915/gvt/trace_points.c
-2
drivers/gpu/drm/i915/gvt/trace_points.c
+3
-2
drivers/gpu/drm/i915/i915_drv.h
+3
-2
drivers/gpu/drm/i915/i915_drv.h
+11
-14
drivers/gpu/drm/i915/i915_gem.c
+11
-14
drivers/gpu/drm/i915/i915_gem.c
···
46
46
#include "gem/i915_gem_ioctls.h"
47
47
#include "gem/i915_gem_pm.h"
48
48
#include "gem/i915_gemfs.h"
49
-
#include "gt/intel_engine_pm.h"
50
49
#include "gt/intel_gt_pm.h"
51
50
#include "gt/intel_mocs.h"
52
51
#include "gt/intel_reset.h"
···
1306
1307
1307
1308
intel_mocs_init_l3cc_table(dev_priv);
1308
1309
1309
-
/* Only when the HW is re-initialised, can we replay the requests */
1310
-
ret = intel_engines_resume(dev_priv);
1311
-
if (ret)
1312
-
goto cleanup_uc;
1313
-
1314
1310
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1315
1311
1316
1312
intel_engines_set_scheduler_caps(dev_priv);
1317
1313
return 0;
1318
1314
1319
-
cleanup_uc:
1320
-
intel_uc_fini_hw(dev_priv);
1321
1315
out:
1322
1316
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1323
-
1324
1317
return ret;
1325
1318
}
1326
1319
···
1571
1580
if (ret)
1572
1581
goto err_uc_init;
1573
1582
1583
+
/* Only when the HW is re-initialised, can we replay the requests */
1584
+
ret = intel_gt_resume(dev_priv);
1585
+
if (ret)
1586
+
goto err_init_hw;
1587
+
1574
1588
/*
1575
1589
* Despite its name intel_init_clock_gating applies both display
1576
1590
* clock gating workarounds; GT mmio workarounds and the occasional
···
1589
1593
1590
1594
ret = intel_engines_verify_workarounds(dev_priv);
1591
1595
if (ret)
1592
-
goto err_init_hw;
1596
+
goto err_gt;
1593
1597
1594
1598
ret = __intel_engines_record_defaults(dev_priv);
1595
1599
if (ret)
1596
-
goto err_init_hw;
1600
+
goto err_gt;
1597
1601
1598
1602
if (i915_inject_load_failure()) {
1599
1603
ret = -ENODEV;
1600
-
goto err_init_hw;
1604
+
goto err_gt;
1601
1605
}
1602
1606
1603
1607
if (i915_inject_load_failure()) {
1604
1608
ret = -EIO;
1605
-
goto err_init_hw;
1609
+
goto err_gt;
1606
1610
}
1607
1611
1608
1612
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
···
1616
1620
* HW as irrevisibly wedged, but keep enough state around that the
1617
1621
* driver doesn't explode during runtime.
1618
1622
*/
1619
-
err_init_hw:
1623
+
err_gt:
1620
1624
mutex_unlock(&dev_priv->drm.struct_mutex);
1621
1625
1622
1626
i915_gem_set_wedged(dev_priv);
···
1626
1630
i915_gem_drain_workqueue(dev_priv);
1627
1631
1628
1632
mutex_lock(&dev_priv->drm.struct_mutex);
1633
+
err_init_hw:
1629
1634
intel_uc_fini_hw(dev_priv);
1630
1635
err_uc_init:
1631
1636
intel_uc_fini(dev_priv);
+6
-2
drivers/gpu/drm/i915/i915_gem_gtt.c
+6
-2
drivers/gpu/drm/i915/i915_gem_gtt.c
···
1444
1444
spin_lock(&pdp->lock);
1445
1445
if (atomic_dec_and_test(&pd->used)) {
1446
1446
gen8_ppgtt_set_pdpe(pdp, vm->scratch_pd, pdpe);
1447
+
pdp->entry[pdpe] = vm->scratch_pd;
1447
1448
GEM_BUG_ON(!atomic_read(&pdp->used));
1448
1449
atomic_dec(&pdp->used);
1449
-
free_pd(vm, pd);
1450
+
GEM_BUG_ON(alloc);
1451
+
alloc = pd; /* defer the free to after the lock */
1450
1452
}
1451
1453
spin_unlock(&pdp->lock);
1452
1454
unwind:
···
1517
1515
spin_lock(&pml4->lock);
1518
1516
if (atomic_dec_and_test(&pdp->used)) {
1519
1517
gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
1520
-
free_pd(vm, pdp);
1518
+
pml4->entry[pml4e] = vm->scratch_pdp;
1519
+
GEM_BUG_ON(alloc);
1520
+
alloc = pdp; /* defer the free until after the lock */
1521
1521
}
1522
1522
spin_unlock(&pml4->lock);
1523
1523
unwind:
+4
-2
drivers/gpu/drm/i915/i915_gpu_error.c
+4
-2
drivers/gpu/drm/i915/i915_gpu_error.c
···
1418
1418
struct intel_engine_cs *engine = i915->engine[i];
1419
1419
struct drm_i915_error_engine *ee = &error->engine[i];
1420
1420
struct i915_request *request;
1421
+
unsigned long flags;
1421
1422
1422
1423
ee->engine_id = -1;
1423
1424
···
1430
1429
error_record_engine_registers(error, engine, ee);
1431
1430
error_record_engine_execlists(engine, ee);
1432
1431
1432
+
spin_lock_irqsave(&engine->active.lock, flags);
1433
1433
request = intel_engine_find_active_request(engine);
1434
1434
if (request) {
1435
1435
struct i915_gem_context *ctx = request->gem_context;
1436
-
struct intel_ring *ring;
1436
+
struct intel_ring *ring = request->ring;
1437
1437
1438
1438
ee->vm = ctx->vm ?: &ggtt->vm;
1439
1439
···
1464
1462
ee->rq_post = request->postfix;
1465
1463
ee->rq_tail = request->tail;
1466
1464
1467
-
ring = request->ring;
1468
1465
ee->cpu_ring_head = ring->head;
1469
1466
ee->cpu_ring_tail = ring->tail;
1470
1467
ee->ringbuffer =
···
1471
1470
1472
1471
engine_record_requests(engine, request, ee);
1473
1472
}
1473
+
spin_unlock_irqrestore(&engine->active.lock, flags);
1474
1474
1475
1475
ee->hws_page =
1476
1476
i915_error_object_create(i915,
+43
-24
drivers/gpu/drm/i915/i915_perf.c
+43
-24
drivers/gpu/drm/i915/i915_perf.c
···
1567
1567
}
1568
1568
}
1569
1569
1570
-
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
1570
+
static void delay_after_mux(void)
1571
1571
{
1572
-
struct drm_i915_private *dev_priv = stream->dev_priv;
1573
-
const struct i915_oa_config *oa_config = stream->oa_config;
1574
-
1575
-
/* PRM:
1576
-
*
1577
-
* OA unit is using “crclk” for its functionality. When trunk
1578
-
* level clock gating takes place, OA clock would be gated,
1579
-
* unable to count the events from non-render clock domain.
1580
-
* Render clock gating must be disabled when OA is enabled to
1581
-
* count the events from non-render domain. Unit level clock
1582
-
* gating for RCS should also be disabled.
1583
-
*/
1584
-
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1585
-
~GEN7_DOP_CLOCK_GATE_ENABLE));
1586
-
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
1587
-
GEN6_CSUNIT_CLOCK_GATE_DISABLE));
1588
-
1589
-
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
1590
-
1591
-
/* It apparently takes a fairly long time for a new MUX
1572
+
/*
1573
+
* It apparently takes a fairly long time for a new MUX
1592
1574
* configuration to be be applied after these register writes.
1593
1575
* This delay duration was derived empirically based on the
1594
1576
* render_basic config but hopefully it covers the maximum
···
1592
1610
* a delay at this location would mitigate any invalid reports.
1593
1611
*/
1594
1612
usleep_range(15000, 20000);
1613
+
}
1614
+
1615
+
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
1616
+
{
1617
+
struct drm_i915_private *dev_priv = stream->dev_priv;
1618
+
const struct i915_oa_config *oa_config = stream->oa_config;
1619
+
1620
+
/*
1621
+
* PRM:
1622
+
*
1623
+
* OA unit is using “crclk” for its functionality. When trunk
1624
+
* level clock gating takes place, OA clock would be gated,
1625
+
* unable to count the events from non-render clock domain.
1626
+
* Render clock gating must be disabled when OA is enabled to
1627
+
* count the events from non-render domain. Unit level clock
1628
+
* gating for RCS should also be disabled.
1629
+
*/
1630
+
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1631
+
~GEN7_DOP_CLOCK_GATE_ENABLE));
1632
+
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
1633
+
GEN6_CSUNIT_CLOCK_GATE_DISABLE));
1634
+
1635
+
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
1636
+
delay_after_mux();
1595
1637
1596
1638
config_oa_regs(dev_priv, oa_config->b_counter_regs,
1597
1639
oa_config->b_counter_regs_len);
···
1841
1835
return ret;
1842
1836
1843
1837
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
1838
+
delay_after_mux();
1844
1839
1845
1840
config_oa_regs(dev_priv, oa_config->b_counter_regs,
1846
1841
oa_config->b_counter_regs_len);
···
2522
2515
i915_perf_destroy_locked(stream);
2523
2516
mutex_unlock(&dev_priv->perf.lock);
2524
2517
2518
+
/* Release the reference the perf stream kept on the driver. */
2519
+
drm_dev_put(&dev_priv->drm);
2520
+
2525
2521
return 0;
2526
2522
}
2527
2523
···
2659
2649
2660
2650
if (!(param->flags & I915_PERF_FLAG_DISABLED))
2661
2651
i915_perf_enable_locked(stream);
2652
+
2653
+
/* Take a reference on the driver that will be kept with stream_fd
2654
+
* until its release.
2655
+
*/
2656
+
drm_dev_get(&dev_priv->drm);
2662
2657
2663
2658
return stream_fd;
2664
2659
···
3492
3477
dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
3493
3478
dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;
3494
3479
3495
-
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
3496
-
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
3497
-
3480
+
if (IS_GEN(dev_priv, 10)) {
3481
+
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
3482
+
dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
3483
+
} else {
3484
+
dev_priv->perf.oa.ctx_oactxctrl_offset = 0x124;
3485
+
dev_priv->perf.oa.ctx_flexeu0_offset = 0x78e;
3486
+
}
3498
3487
dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
3499
3488
}
3500
3489
}
+33
-43
drivers/gpu/drm/i915/i915_trace.h
+33
-43
drivers/gpu/drm/i915/i915_trace.h
···
21
21
/* watermark/fifo updates */
22
22
23
23
TRACE_EVENT(intel_pipe_enable,
24
-
TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe),
25
-
TP_ARGS(dev_priv, pipe),
24
+
TP_PROTO(struct intel_crtc *crtc),
25
+
TP_ARGS(crtc),
26
26
27
27
TP_STRUCT__entry(
28
28
__array(u32, frame, 3)
29
29
__array(u32, scanline, 3)
30
30
__field(enum pipe, pipe)
31
31
),
32
-
33
32
TP_fast_assign(
34
-
enum pipe _pipe;
35
-
for_each_pipe(dev_priv, _pipe) {
36
-
__entry->frame[_pipe] =
37
-
dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, _pipe);
38
-
__entry->scanline[_pipe] =
39
-
intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, _pipe));
33
+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
34
+
struct intel_crtc *it__;
35
+
for_each_intel_crtc(&dev_priv->drm, it__) {
36
+
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
37
+
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
40
38
}
41
-
__entry->pipe = pipe;
39
+
__entry->pipe = crtc->pipe;
42
40
),
43
41
44
42
TP_printk("pipe %c enable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
···
47
49
);
48
50
49
51
TRACE_EVENT(intel_pipe_disable,
50
-
TP_PROTO(struct drm_i915_private *dev_priv, enum pipe pipe),
51
-
TP_ARGS(dev_priv, pipe),
52
+
TP_PROTO(struct intel_crtc *crtc),
53
+
TP_ARGS(crtc),
52
54
53
55
TP_STRUCT__entry(
54
56
__array(u32, frame, 3)
···
57
59
),
58
60
59
61
TP_fast_assign(
60
-
enum pipe _pipe;
61
-
for_each_pipe(dev_priv, _pipe) {
62
-
__entry->frame[_pipe] =
63
-
dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, _pipe);
64
-
__entry->scanline[_pipe] =
65
-
intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, _pipe));
62
+
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
63
+
struct intel_crtc *it__;
64
+
for_each_intel_crtc(&dev_priv->drm, it__) {
65
+
__entry->frame[it__->pipe] = intel_crtc_get_vblank_counter(it__);
66
+
__entry->scanline[it__->pipe] = intel_get_crtc_scanline(it__);
66
67
}
67
-
__entry->pipe = pipe;
68
+
__entry->pipe = crtc->pipe;
68
69
),
69
70
70
71
TP_printk("pipe %c disable, pipe A: frame=%u, scanline=%u, pipe B: frame=%u, scanline=%u, pipe C: frame=%u, scanline=%u",
···
86
89
87
90
TP_fast_assign(
88
91
__entry->pipe = crtc->pipe;
89
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
90
-
crtc->pipe);
92
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
91
93
__entry->scanline = intel_get_crtc_scanline(crtc);
92
94
memcpy(__entry->crcs, crcs, sizeof(__entry->crcs));
93
95
),
···
108
112
),
109
113
110
114
TP_fast_assign(
115
+
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
111
116
__entry->pipe = pipe;
112
-
__entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);
113
-
__entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));
117
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
118
+
__entry->scanline = intel_get_crtc_scanline(crtc);
114
119
),
115
120
116
121
TP_printk("pipe %c, frame=%u, scanline=%u",
···
131
134
132
135
TP_fast_assign(
133
136
enum pipe pipe = pch_transcoder;
137
+
struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
134
138
__entry->pipe = pipe;
135
-
__entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);
136
-
__entry->scanline = intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));
139
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
140
+
__entry->scanline = intel_get_crtc_scanline(crtc);
137
141
),
138
142
139
143
TP_printk("pch transcoder %c, frame=%u, scanline=%u",
···
154
156
),
155
157
156
158
TP_fast_assign(
157
-
enum pipe pipe;
158
-
for_each_pipe(dev_priv, pipe) {
159
-
__entry->frame[pipe] =
160
-
dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm, pipe);
161
-
__entry->scanline[pipe] =
162
-
intel_get_crtc_scanline(intel_get_crtc_for_pipe(dev_priv, pipe));
159
+
struct intel_crtc *crtc;
160
+
for_each_intel_crtc(&dev_priv->drm, crtc) {
161
+
__entry->frame[crtc->pipe] = intel_crtc_get_vblank_counter(crtc);
162
+
__entry->scanline[crtc->pipe] = intel_get_crtc_scanline(crtc);
163
163
}
164
164
__entry->old = old;
165
165
__entry->new = new;
···
194
198
195
199
TP_fast_assign(
196
200
__entry->pipe = crtc->pipe;
197
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
198
-
crtc->pipe);
201
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
199
202
__entry->scanline = intel_get_crtc_scanline(crtc);
200
203
__entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY];
201
204
__entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0];
···
238
243
239
244
TP_fast_assign(
240
245
__entry->pipe = crtc->pipe;
241
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
242
-
crtc->pipe);
246
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
243
247
__entry->scanline = intel_get_crtc_scanline(crtc);
244
248
__entry->level = wm->level;
245
249
__entry->cxsr = wm->cxsr;
···
272
278
273
279
TP_fast_assign(
274
280
__entry->pipe = crtc->pipe;
275
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
276
-
crtc->pipe);
281
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
277
282
__entry->scanline = intel_get_crtc_scanline(crtc);
278
283
__entry->sprite0_start = sprite0_start;
279
284
__entry->sprite1_start = sprite1_start;
···
303
310
TP_fast_assign(
304
311
__entry->pipe = crtc->pipe;
305
312
__entry->name = plane->name;
306
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
307
-
crtc->pipe);
313
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
308
314
__entry->scanline = intel_get_crtc_scanline(crtc);
309
315
memcpy(__entry->src, &plane->state->src, sizeof(__entry->src));
310
316
memcpy(__entry->dst, &plane->state->dst, sizeof(__entry->dst));
···
330
338
TP_fast_assign(
331
339
__entry->pipe = crtc->pipe;
332
340
__entry->name = plane->name;
333
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
334
-
crtc->pipe);
341
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
335
342
__entry->scanline = intel_get_crtc_scanline(crtc);
336
343
),
337
344
···
355
364
356
365
TP_fast_assign(
357
366
__entry->pipe = crtc->pipe;
358
-
__entry->frame = crtc->base.dev->driver->get_vblank_counter(crtc->base.dev,
359
-
crtc->pipe);
367
+
__entry->frame = intel_crtc_get_vblank_counter(crtc);
360
368
__entry->scanline = intel_get_crtc_scanline(crtc);
361
369
__entry->min = crtc->debug.min_vbl;
362
370
__entry->max = crtc->debug.max_vbl;
+4
-6
drivers/gpu/drm/i915/intel_runtime_pm.c
+4
-6
drivers/gpu/drm/i915/intel_runtime_pm.c
···
221
221
static void
222
222
dump_and_free_wakeref_tracking(struct intel_runtime_pm_debug *debug)
223
223
{
224
-
struct drm_printer p;
224
+
if (debug->count) {
225
+
struct drm_printer p = drm_debug_printer("i915");
225
226
226
-
if (!debug->count)
227
-
return;
228
-
229
-
p = drm_debug_printer("i915");
230
-
__print_intel_runtime_pm_wakeref(&p, debug);
227
+
__print_intel_runtime_pm_wakeref(&p, debug);
228
+
}
231
229
232
230
kfree(debug->owners);
233
231
}
+15
drivers/gpu/drm/i915/intel_wakeref.h
+15
drivers/gpu/drm/i915/intel_wakeref.h
···
66
66
}
67
67
68
68
/**
69
+
* intel_wakeref_get_if_in_use: Acquire the wakeref
70
+
* @wf: the wakeref
71
+
*
72
+
* Acquire a hold on the wakeref, but only if the wakeref is already
73
+
* active.
74
+
*
75
+
* Returns: true if the wakeref was acquired, false otherwise.
76
+
*/
77
+
static inline bool
78
+
intel_wakeref_get_if_active(struct intel_wakeref *wf)
79
+
{
80
+
return atomic_inc_not_zero(&wf->count);
81
+
}
82
+
83
+
/**
69
84
* intel_wakeref_put: Release the wakeref
70
85
* @i915: the drm_i915_private device
71
86
* @wf: the wakeref
+2
include/drm/drm_client.h
+2
include/drm/drm_client.h
···
149
149
struct drm_client_buffer *
150
150
drm_client_framebuffer_create(struct drm_client_dev *client, u32 width, u32 height, u32 format);
151
151
void drm_client_framebuffer_delete(struct drm_client_buffer *buffer);
152
+
void *drm_client_buffer_vmap(struct drm_client_buffer *buffer);
153
+
void drm_client_buffer_vunmap(struct drm_client_buffer *buffer);
152
154
153
155
int drm_client_modeset_create(struct drm_client_dev *client);
154
156
void drm_client_modeset_free(struct drm_client_dev *client);
+7
include/drm/drm_mode_config.h
+7
include/drm/drm_mode_config.h
···
853
853
uint32_t preferred_depth, prefer_shadow;
854
854
855
855
/**
856
+
* @prefer_shadow_fbdev:
857
+
*
858
+
* Hint to framebuffer emulation to prefer shadow-fb rendering.
859
+
*/
860
+
bool prefer_shadow_fbdev;
861
+
862
+
/**
856
863
* @quirk_addfb_prefer_xbgr_30bpp:
857
864
*
858
865
* Special hack for legacy ADDFB to keep nouveau userspace happy. Should