Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Mostly bugfixes and a few small code removals. Worth pointing out is:
- A handful of more fixes to get DT enablement working properly on
OMAP, finding new breakage of things that don't work quite right
yet without the traditional board files. I expect a bit more of
this to come in this release as people test on their hardware.
- Implementation of power_down_finish() on vexpress, to make kexec
work and to stop the MCPM core to produce a warning (the warning
was new to 3.13-rc1).
- A handful of minor fixes for various platforms"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: bcm2835: add missing #xxx-cells to I2C nodes
ARM: dts: Add max77686 RTC interrupt to cros5250-common
ARM: vexpress/TC2: Implement MCPM power_down_finish()
ARM: tegra: Provide dummy powergate implementation
ARM: omap: fix warning with LPAE build
ARM: OMAP2+: Remove legacy omap4_twl6030_hsmmc_init
ARM: OMAP2+: Remove legacy mux code for display.c
ARM: OMAP2+: Fix undefined reference to set_cntfreq
gpio: twl4030: Fix passing of pdata in the device tree case
gpio: twl4030: Fix regression for twl gpio output
ARM: OMAP2+: More randconfig fixes for reconfigure_io_chain
ARM: dts: imx6qdl: disable spdif "rxtx5" clock option
ARM: dts: Fix omap2 specific dtsi files by adding the missing entries
ARM: OMAP2+: Fix GPMC and simplify bootloader timings for 8250 and smc91x
i2c: omap: Fix missing device tree flags for omap2
+379
-192
+2
-1
Documentation/devicetree/bindings/i2c/i2c-omap.txt
+2
-1
Documentation/devicetree/bindings/i2c/i2c-omap.txt
···
1
1
I2C for OMAP platforms
2
2
3
3
Required properties :
4
-
- compatible : Must be "ti,omap3-i2c" or "ti,omap4-i2c"
4
+
- compatible : Must be "ti,omap2420-i2c", "ti,omap2430-i2c", "ti,omap3-i2c"
5
+
or "ti,omap4-i2c"
5
6
- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
6
7
- #address-cells = <1>;
7
8
- #size-cells = <0>;
+4
arch/arm/boot/dts/bcm2835.dtsi
+4
arch/arm/boot/dts/bcm2835.dtsi
···
85
85
reg = <0x7e205000 0x1000>;
86
86
interrupts = <2 21>;
87
87
clocks = <&clk_i2c>;
88
+
#address-cells = <1>;
89
+
#size-cells = <0>;
88
90
status = "disabled";
89
91
};
90
92
···
95
93
reg = <0x7e804000 0x1000>;
96
94
interrupts = <2 21>;
97
95
clocks = <&clk_i2c>;
96
+
#address-cells = <1>;
97
+
#size-cells = <0>;
98
98
status = "disabled";
99
99
};
100
100
+12
arch/arm/boot/dts/cros5250-common.dtsi
+12
arch/arm/boot/dts/cros5250-common.dtsi
···
27
27
i2c2_bus: i2c2-bus {
28
28
samsung,pin-pud = <0>;
29
29
};
30
+
31
+
max77686_irq: max77686-irq {
32
+
samsung,pins = "gpx3-2";
33
+
samsung,pin-function = <0>;
34
+
samsung,pin-pud = <0>;
35
+
samsung,pin-drv = <0>;
36
+
};
30
37
};
31
38
32
39
i2c@12C60000 {
···
42
35
43
36
max77686@09 {
44
37
compatible = "maxim,max77686";
38
+
interrupt-parent = <&gpx3>;
39
+
interrupts = <2 0>;
40
+
pinctrl-names = "default";
41
+
pinctrl-0 = <&max77686_irq>;
42
+
wakeup-source;
45
43
reg = <0x09>;
46
44
47
45
voltage-regulators {
+1
-1
arch/arm/boot/dts/imx6qdl.dtsi
+1
-1
arch/arm/boot/dts/imx6qdl.dtsi
+1
-1
arch/arm/boot/dts/omap-zoom-common.dtsi
+1
-1
arch/arm/boot/dts/omap-zoom-common.dtsi
+96
arch/arm/boot/dts/omap2.dtsi
+96
arch/arm/boot/dts/omap2.dtsi
···
9
9
*/
10
10
11
11
#include <dt-bindings/gpio/gpio.h>
12
+
#include <dt-bindings/interrupt-controller/irq.h>
12
13
#include <dt-bindings/pinctrl/omap.h>
13
14
14
15
#include "skeleton.dtsi"
···
22
21
serial0 = &uart1;
23
22
serial1 = &uart2;
24
23
serial2 = &uart3;
24
+
i2c0 = &i2c1;
25
+
i2c1 = &i2c2;
25
26
};
26
27
27
28
cpus {
···
56
53
ranges;
57
54
ti,hwmods = "l3_main";
58
55
56
+
aes: aes@480a6000 {
57
+
compatible = "ti,omap2-aes";
58
+
ti,hwmods = "aes";
59
+
reg = <0x480a6000 0x50>;
60
+
dmas = <&sdma 9 &sdma 10>;
61
+
dma-names = "tx", "rx";
62
+
};
63
+
64
+
hdq1w: 1w@480b2000 {
65
+
compatible = "ti,omap2420-1w";
66
+
ti,hwmods = "hdq1w";
67
+
reg = <0x480b2000 0x1000>;
68
+
interrupts = <58>;
69
+
};
70
+
71
+
mailbox: mailbox@48094000 {
72
+
compatible = "ti,omap2-mailbox";
73
+
ti,hwmods = "mailbox";
74
+
reg = <0x48094000 0x200>;
75
+
interrupts = <26>;
76
+
};
77
+
59
78
intc: interrupt-controller@1 {
60
79
compatible = "ti,omap2-intc";
61
80
interrupt-controller;
···
88
63
89
64
sdma: dma-controller@48056000 {
90
65
compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
66
+
ti,hwmods = "dma";
91
67
reg = <0x48056000 0x1000>;
92
68
interrupts = <12>,
93
69
<13>,
···
99
73
#dma-requests = <64>;
100
74
};
101
75
76
+
i2c1: i2c@48070000 {
77
+
compatible = "ti,omap2-i2c";
78
+
ti,hwmods = "i2c1";
79
+
reg = <0x48070000 0x80>;
80
+
#address-cells = <1>;
81
+
#size-cells = <0>;
82
+
interrupts = <56>;
83
+
dmas = <&sdma 27 &sdma 28>;
84
+
dma-names = "tx", "rx";
85
+
};
86
+
87
+
i2c2: i2c@48072000 {
88
+
compatible = "ti,omap2-i2c";
89
+
ti,hwmods = "i2c2";
90
+
reg = <0x48072000 0x80>;
91
+
#address-cells = <1>;
92
+
#size-cells = <0>;
93
+
interrupts = <57>;
94
+
dmas = <&sdma 29 &sdma 30>;
95
+
dma-names = "tx", "rx";
96
+
};
97
+
98
+
mcspi1: mcspi@48098000 {
99
+
compatible = "ti,omap2-mcspi";
100
+
ti,hwmods = "mcspi1";
101
+
reg = <0x48098000 0x100>;
102
+
interrupts = <65>;
103
+
dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38
104
+
&sdma 39 &sdma 40 &sdma 41 &sdma 42>;
105
+
dma-names = "tx0", "rx0", "tx1", "rx1",
106
+
"tx2", "rx2", "tx3", "rx3";
107
+
};
108
+
109
+
mcspi2: mcspi@4809a000 {
110
+
compatible = "ti,omap2-mcspi";
111
+
ti,hwmods = "mcspi2";
112
+
reg = <0x4809a000 0x100>;
113
+
interrupts = <66>;
114
+
dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>;
115
+
dma-names = "tx0", "rx0", "tx1", "rx1";
116
+
};
117
+
118
+
rng: rng@480a0000 {
119
+
compatible = "ti,omap2-rng";
120
+
ti,hwmods = "rng";
121
+
reg = <0x480a0000 0x50>;
122
+
interrupts = <36>;
123
+
};
124
+
125
+
sham: sham@480a4000 {
126
+
compatible = "ti,omap2-sham";
127
+
ti,hwmods = "sham";
128
+
reg = <0x480a4000 0x64>;
129
+
interrupts = <51>;
130
+
dmas = <&sdma 13>;
131
+
dma-names = "rx";
132
+
};
133
+
102
134
uart1: serial@4806a000 {
103
135
compatible = "ti,omap2-uart";
104
136
ti,hwmods = "uart1";
137
+
reg = <0x4806a000 0x2000>;
138
+
interrupts = <72>;
139
+
dmas = <&sdma 49 &sdma 50>;
140
+
dma-names = "tx", "rx";
105
141
clock-frequency = <48000000>;
106
142
};
107
143
108
144
uart2: serial@4806c000 {
109
145
compatible = "ti,omap2-uart";
110
146
ti,hwmods = "uart2";
147
+
reg = <0x4806c000 0x400>;
148
+
interrupts = <73>;
149
+
dmas = <&sdma 51 &sdma 52>;
150
+
dma-names = "tx", "rx";
111
151
clock-frequency = <48000000>;
112
152
};
113
153
114
154
uart3: serial@4806e000 {
115
155
compatible = "ti,omap2-uart";
116
156
ti,hwmods = "uart3";
157
+
reg = <0x4806e000 0x400>;
158
+
interrupts = <74>;
159
+
dmas = <&sdma 53 &sdma 54>;
160
+
dma-names = "tx", "rx";
117
161
clock-frequency = <48000000>;
118
162
};
119
163
+23
arch/arm/boot/dts/omap2420.dtsi
+23
arch/arm/boot/dts/omap2420.dtsi
···
114
114
dma-names = "tx", "rx";
115
115
};
116
116
117
+
msdi1: mmc@4809c000 {
118
+
compatible = "ti,omap2420-mmc";
119
+
ti,hwmods = "msdi1";
120
+
reg = <0x4809c000 0x80>;
121
+
interrupts = <83>;
122
+
dmas = <&sdma 61 &sdma 62>;
123
+
dma-names = "tx", "rx";
124
+
};
125
+
117
126
timer1: timer@48028000 {
118
127
compatible = "ti,omap2420-timer";
119
128
reg = <0x48028000 0x400>;
···
130
121
ti,hwmods = "timer1";
131
122
ti,timer-alwon;
132
123
};
124
+
125
+
wd_timer2: wdt@48022000 {
126
+
compatible = "ti,omap2-wdt";
127
+
ti,hwmods = "wd_timer2";
128
+
reg = <0x48022000 0x80>;
129
+
};
133
130
};
131
+
};
132
+
133
+
&i2c1 {
134
+
compatible = "ti,omap2420-i2c";
135
+
};
136
+
137
+
&i2c2 {
138
+
compatible = "ti,omap2420-i2c";
134
139
};
+49
arch/arm/boot/dts/omap2430.dtsi
+49
arch/arm/boot/dts/omap2430.dtsi
···
175
175
dma-names = "tx", "rx";
176
176
};
177
177
178
+
mmc1: mmc@4809c000 {
179
+
compatible = "ti,omap2-hsmmc";
180
+
reg = <0x4809c000 0x200>;
181
+
interrupts = <83>;
182
+
ti,hwmods = "mmc1";
183
+
ti,dual-volt;
184
+
dmas = <&sdma 61>, <&sdma 62>;
185
+
dma-names = "tx", "rx";
186
+
};
187
+
188
+
mmc2: mmc@480b4000 {
189
+
compatible = "ti,omap2-hsmmc";
190
+
reg = <0x480b4000 0x200>;
191
+
interrupts = <86>;
192
+
ti,hwmods = "mmc2";
193
+
dmas = <&sdma 47>, <&sdma 48>;
194
+
dma-names = "tx", "rx";
195
+
};
196
+
178
197
timer1: timer@49018000 {
179
198
compatible = "ti,omap2420-timer";
180
199
reg = <0x49018000 0x400>;
···
201
182
ti,hwmods = "timer1";
202
183
ti,timer-alwon;
203
184
};
185
+
186
+
mcspi3: mcspi@480b8000 {
187
+
compatible = "ti,omap2-mcspi";
188
+
ti,hwmods = "mcspi3";
189
+
reg = <0x480b8000 0x100>;
190
+
interrupts = <91>;
191
+
dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>;
192
+
dma-names = "tx0", "rx0", "tx1", "rx1";
193
+
};
194
+
195
+
usb_otg_hs: usb_otg_hs@480ac000 {
196
+
compatible = "ti,omap2-musb";
197
+
ti,hwmods = "usb_otg_hs";
198
+
reg = <0x480ac000 0x1000>;
199
+
interrupts = <93>;
200
+
};
201
+
202
+
wd_timer2: wdt@49016000 {
203
+
compatible = "ti,omap2-wdt";
204
+
ti,hwmods = "wd_timer2";
205
+
reg = <0x49016000 0x80>;
206
+
};
204
207
};
208
+
};
209
+
210
+
&i2c1 {
211
+
compatible = "ti,omap2430-i2c";
212
+
};
213
+
214
+
&i2c2 {
215
+
compatible = "ti,omap2430-i2c";
205
216
};
+3
-3
arch/arm/mach-omap2/Makefile
+3
-3
arch/arm/mach-omap2/Makefile
···
19
19
20
20
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
21
21
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
22
-
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
22
+
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
23
23
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24
-
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
24
+
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
25
25
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26
-
obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
26
+
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
27
27
28
28
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
29
29
obj-y += mcbsp.o
-1
arch/arm/mach-omap2/common.h
-1
arch/arm/mach-omap2/common.h
···
299
299
extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
300
300
struct omap_sdrc_params *sdrc_cs1);
301
301
struct omap2_hsmmc_info;
302
-
extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
303
302
extern void omap_reserve(void);
304
303
305
304
struct omap_hwmod;
-78
arch/arm/mach-omap2/display.c
-78
arch/arm/mach-omap2/display.c
···
32
32
33
33
#include "soc.h"
34
34
#include "iomap.h"
35
-
#include "mux.h"
36
35
#include "control.h"
37
36
#include "display.h"
38
37
#include "prm.h"
···
101
102
{ "dss_hdmi", "omapdss_hdmi", -1 },
102
103
};
103
104
104
-
static void __init omap4_tpd12s015_mux_pads(void)
105
-
{
106
-
omap_mux_init_signal("hdmi_cec",
107
-
OMAP_PIN_INPUT_PULLUP);
108
-
omap_mux_init_signal("hdmi_ddc_scl",
109
-
OMAP_PIN_INPUT_PULLUP);
110
-
omap_mux_init_signal("hdmi_ddc_sda",
111
-
OMAP_PIN_INPUT_PULLUP);
112
-
}
113
-
114
-
static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
115
-
{
116
-
u32 reg;
117
-
u16 control_i2c_1;
118
-
119
-
/*
120
-
* CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
121
-
* HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
122
-
* internal pull up resistor.
123
-
*/
124
-
if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
125
-
control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
126
-
reg = omap4_ctrl_pad_readl(control_i2c_1);
127
-
reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
128
-
OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
129
-
omap4_ctrl_pad_writel(reg, control_i2c_1);
130
-
}
131
-
}
132
-
133
-
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
134
-
{
135
-
u32 enable_mask, enable_shift;
136
-
u32 pipd_mask, pipd_shift;
137
-
u32 reg;
138
-
139
-
if (dsi_id == 0) {
140
-
enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
141
-
enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
142
-
pipd_mask = OMAP4_DSI1_PIPD_MASK;
143
-
pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
144
-
} else if (dsi_id == 1) {
145
-
enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
146
-
enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
147
-
pipd_mask = OMAP4_DSI2_PIPD_MASK;
148
-
pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
149
-
} else {
150
-
return -ENODEV;
151
-
}
152
-
153
-
reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
154
-
155
-
reg &= ~enable_mask;
156
-
reg &= ~pipd_mask;
157
-
158
-
reg |= (lanes << enable_shift) & enable_mask;
159
-
reg |= (lanes << pipd_shift) & pipd_mask;
160
-
161
-
omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
162
-
163
-
return 0;
164
-
}
165
-
166
-
int __init omap_hdmi_init(enum omap_hdmi_flags flags)
167
-
{
168
-
if (cpu_is_omap44xx()) {
169
-
omap4_hdmi_mux_pads(flags);
170
-
omap4_tpd12s015_mux_pads();
171
-
}
172
-
173
-
return 0;
174
-
}
175
-
176
105
static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
177
106
{
178
-
if (cpu_is_omap44xx())
179
-
return omap4_dsi_mux_pads(dsi_id, lane_mask);
180
-
181
107
return 0;
182
108
}
183
109
184
110
static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
185
111
{
186
-
if (cpu_is_omap44xx())
187
-
omap4_dsi_mux_pads(dsi_id, 0);
188
112
}
189
113
190
114
static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
+19
-39
arch/arm/mach-omap2/gpmc.c
+19
-39
arch/arm/mach-omap2/gpmc.c
···
1502
1502
}
1503
1503
1504
1504
/*
1505
+
* For some GPMC devices we still need to rely on the bootloader
1506
+
* timings because the devices can be connected via FPGA. So far
1507
+
* the list is smc91x on the omap2 SDP boards, and 8250 on zooms.
1508
+
* REVISIT: Add timing support from slls644g.pdf and from the
1509
+
* lan91c96 manual.
1510
+
*/
1511
+
if (of_device_is_compatible(child, "ns16550a") ||
1512
+
of_device_is_compatible(child, "smsc,lan91c94") ||
1513
+
of_device_is_compatible(child, "smsc,lan91c111")) {
1514
+
dev_warn(&pdev->dev,
1515
+
"%s using bootloader timings on CS%d\n",
1516
+
child->name, cs);
1517
+
goto no_timings;
1518
+
}
1519
+
1520
+
/*
1505
1521
* FIXME: gpmc_cs_request() will map the CS to an arbitary
1506
1522
* location in the gpmc address space. When booting with
1507
1523
* device-tree we want the NOR flash to be mapped to the
···
1545
1529
gpmc_read_timings_dt(child, &gpmc_t);
1546
1530
gpmc_cs_set_timings(cs, &gpmc_t);
1547
1531
1532
+
no_timings:
1548
1533
if (of_platform_device_create(child, NULL, &pdev->dev))
1549
1534
return 0;
1550
1535
···
1556
1539
gpmc_cs_free(cs);
1557
1540
1558
1541
return ret;
1559
-
}
1560
-
1561
-
/*
1562
-
* REVISIT: Add timing support from slls644g.pdf
1563
-
*/
1564
-
static int gpmc_probe_8250(struct platform_device *pdev,
1565
-
struct device_node *child)
1566
-
{
1567
-
struct resource res;
1568
-
unsigned long base;
1569
-
int ret, cs;
1570
-
1571
-
if (of_property_read_u32(child, "reg", &cs) < 0) {
1572
-
dev_err(&pdev->dev, "%s has no 'reg' property\n",
1573
-
child->full_name);
1574
-
return -ENODEV;
1575
-
}
1576
-
1577
-
if (of_address_to_resource(child, 0, &res) < 0) {
1578
-
dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
1579
-
child->full_name);
1580
-
return -ENODEV;
1581
-
}
1582
-
1583
-
ret = gpmc_cs_request(cs, resource_size(&res), &base);
1584
-
if (ret < 0) {
1585
-
dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1586
-
return ret;
1587
-
}
1588
-
1589
-
if (of_platform_device_create(child, NULL, &pdev->dev))
1590
-
return 0;
1591
-
1592
-
dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
1593
-
1594
-
return -ENODEV;
1595
1542
}
1596
1543
1597
1544
static int gpmc_probe_dt(struct platform_device *pdev)
···
1599
1618
else if (of_node_cmp(child->name, "onenand") == 0)
1600
1619
ret = gpmc_probe_onenand_child(pdev, child);
1601
1620
else if (of_node_cmp(child->name, "ethernet") == 0 ||
1602
-
of_node_cmp(child->name, "nor") == 0)
1621
+
of_node_cmp(child->name, "nor") == 0 ||
1622
+
of_node_cmp(child->name, "uart") == 0)
1603
1623
ret = gpmc_probe_generic_child(pdev, child);
1604
-
else if (of_node_cmp(child->name, "8250") == 0)
1605
-
ret = gpmc_probe_8250(pdev, child);
1606
1624
1607
1625
if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
1608
1626
__func__, child->full_name))
+7
arch/arm/mach-omap2/omap-secure.h
+7
arch/arm/mach-omap2/omap-secure.h
-57
arch/arm/mach-omap2/omap4-common.c
-57
arch/arm/mach-omap2/omap4-common.c
···
35
35
#include "iomap.h"
36
36
#include "common.h"
37
37
#include "mmc.h"
38
-
#include "hsmmc.h"
39
38
#include "prminst44xx.h"
40
39
#include "prcm_mpu44xx.h"
41
40
#include "omap4-sar-layout.h"
···
283
284
omap_wakeupgen_init();
284
285
irqchip_init();
285
286
}
286
-
287
-
#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
288
-
static int omap4_twl6030_hsmmc_late_init(struct device *dev)
289
-
{
290
-
int irq = 0;
291
-
struct platform_device *pdev = container_of(dev,
292
-
struct platform_device, dev);
293
-
struct omap_mmc_platform_data *pdata = dev->platform_data;
294
-
295
-
/* Setting MMC1 Card detect Irq */
296
-
if (pdev->id == 0) {
297
-
irq = twl6030_mmc_card_detect_config();
298
-
if (irq < 0) {
299
-
dev_err(dev, "%s: Error card detect config(%d)\n",
300
-
__func__, irq);
301
-
return irq;
302
-
}
303
-
pdata->slots[0].card_detect_irq = irq;
304
-
pdata->slots[0].card_detect = twl6030_mmc_card_detect;
305
-
}
306
-
return 0;
307
-
}
308
-
309
-
static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev)
310
-
{
311
-
struct omap_mmc_platform_data *pdata;
312
-
313
-
/* dev can be null if CONFIG_MMC_OMAP_HS is not set */
314
-
if (!dev) {
315
-
pr_err("Failed %s\n", __func__);
316
-
return;
317
-
}
318
-
pdata = dev->platform_data;
319
-
pdata->init = omap4_twl6030_hsmmc_late_init;
320
-
}
321
-
322
-
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
323
-
{
324
-
struct omap2_hsmmc_info *c;
325
-
326
-
omap_hsmmc_init(controllers);
327
-
for (c = controllers; c->mmc; c++) {
328
-
/* pdev can be null if CONFIG_MMC_OMAP_HS is not set */
329
-
if (!c->pdev)
330
-
continue;
331
-
omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev);
332
-
}
333
-
334
-
return 0;
335
-
}
336
-
#else
337
-
int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
338
-
{
339
-
return 0;
340
-
}
341
-
#endif
+1
-1
arch/arm/mach-omap2/pm34xx.c
+1
-1
arch/arm/mach-omap2/pm34xx.c
···
120
120
* will hang the system.
121
121
*/
122
122
pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123
-
ret = _omap_save_secure_sram((u32 *)
123
+
ret = _omap_save_secure_sram((u32 *)(unsigned long)
124
124
__pa(omap3_secure_ram_storage));
125
125
pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
126
126
/* Following is for error tracking, it should not happen */
+1
-1
arch/arm/mach-omap2/prm44xx_54xx.h
+1
-1
arch/arm/mach-omap2/prm44xx_54xx.h
···
43
43
extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
44
44
45
45
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
46
-
defined(CONFIG_SOC_DRA7XX)
46
+
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
47
47
void omap44xx_prm_reconfigure_io_chain(void);
48
48
#else
49
49
static inline void omap44xx_prm_reconfigure_io_chain(void)
+40
arch/arm/mach-vexpress/spc.c
+40
arch/arm/mach-vexpress/spc.c
···
53
53
#define A15_BX_ADDR0 0x68
54
54
#define A7_BX_ADDR0 0x78
55
55
56
+
/* SPC CPU/cluster reset statue */
57
+
#define STANDBYWFI_STAT 0x3c
58
+
#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
59
+
#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
60
+
56
61
/* SPC system config interface registers */
57
62
#define SYSCFG_WDATA 0x70
58
63
#define SYSCFG_RDATA 0x74
···
216
211
217
212
pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
218
213
writel_relaxed(enable, info->baseaddr + pwdrn_reg);
214
+
}
215
+
216
+
static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster)
217
+
{
218
+
return cluster_is_a15(cluster) ?
219
+
STANDBYWFI_STAT_A15_CPU_MASK(cpu)
220
+
: STANDBYWFI_STAT_A7_CPU_MASK(cpu);
221
+
}
222
+
223
+
/**
224
+
* ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
225
+
*
226
+
* @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster
227
+
* @cluster: mpidr[15:8] bitfield describing cluster affinity level
228
+
*
229
+
* @return: non-zero if and only if the specified CPU is in WFI
230
+
*
231
+
* Take care when interpreting the result of this function: a CPU might
232
+
* be in WFI temporarily due to idle, and is not necessarily safely
233
+
* parked.
234
+
*/
235
+
int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster)
236
+
{
237
+
int ret;
238
+
u32 mask = standbywfi_cpu_mask(cpu, cluster);
239
+
240
+
if (cluster >= MAX_CLUSTERS)
241
+
return 1;
242
+
243
+
ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT);
244
+
245
+
pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n",
246
+
__func__, STANDBYWFI_STAT, ret, mask);
247
+
248
+
return ret & mask;
219
249
}
220
250
221
251
static int ve_spc_get_performance(int cluster, u32 *freq)
+1
arch/arm/mach-vexpress/spc.h
+1
arch/arm/mach-vexpress/spc.h
+61
-5
arch/arm/mach-vexpress/tc2_pm.c
+61
-5
arch/arm/mach-vexpress/tc2_pm.c
···
12
12
* published by the Free Software Foundation.
13
13
*/
14
14
15
+
#include <linux/delay.h>
15
16
#include <linux/init.h>
16
17
#include <linux/io.h>
17
18
#include <linux/kernel.h>
···
33
32
#include "spc.h"
34
33
35
34
/* SCC conf registers */
35
+
#define RESET_CTRL 0x018
36
+
#define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu)))
37
+
#define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu)))
38
+
36
39
#define A15_CONF 0x400
37
40
#define A7_CONF 0x500
38
41
#define SYS_INFO 0x700
39
42
#define SPC_BASE 0xb00
43
+
44
+
static void __iomem *scc;
40
45
41
46
/*
42
47
* We can't use regular spinlocks. In the switcher case, it is possible
···
197
190
tc2_pm_down(0);
198
191
}
199
192
193
+
static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
194
+
{
195
+
u32 mask = cluster ?
196
+
RESET_A7_NCORERESET(cpu)
197
+
: RESET_A15_NCORERESET(cpu);
198
+
199
+
return !(readl_relaxed(scc + RESET_CTRL) & mask);
200
+
}
201
+
202
+
#define POLL_MSEC 10
203
+
#define TIMEOUT_MSEC 1000
204
+
205
+
static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster)
206
+
{
207
+
unsigned tries;
208
+
209
+
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
210
+
BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
211
+
212
+
for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) {
213
+
/*
214
+
* Only examine the hardware state if the target CPU has
215
+
* caught up at least as far as tc2_pm_down():
216
+
*/
217
+
if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) {
218
+
pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n",
219
+
__func__, cpu, cluster,
220
+
readl_relaxed(scc + RESET_CTRL));
221
+
222
+
/*
223
+
* We need the CPU to reach WFI, but the power
224
+
* controller may put the cluster in reset and
225
+
* power it off as soon as that happens, before
226
+
* we have a chance to see STANDBYWFI.
227
+
*
228
+
* So we need to check for both conditions:
229
+
*/
230
+
if (tc2_core_in_reset(cpu, cluster) ||
231
+
ve_spc_cpu_in_wfi(cpu, cluster))
232
+
return 0; /* success: the CPU is halted */
233
+
}
234
+
235
+
/* Otherwise, wait and retry: */
236
+
msleep(POLL_MSEC);
237
+
}
238
+
239
+
return -ETIMEDOUT; /* timeout */
240
+
}
241
+
200
242
static void tc2_pm_suspend(u64 residency)
201
243
{
202
244
unsigned int mpidr, cpu, cluster;
···
288
232
}
289
233
290
234
static const struct mcpm_platform_ops tc2_pm_power_ops = {
291
-
.power_up = tc2_pm_power_up,
292
-
.power_down = tc2_pm_power_down,
293
-
.suspend = tc2_pm_suspend,
294
-
.powered_up = tc2_pm_powered_up,
235
+
.power_up = tc2_pm_power_up,
236
+
.power_down = tc2_pm_power_down,
237
+
.power_down_finish = tc2_pm_power_down_finish,
238
+
.suspend = tc2_pm_suspend,
239
+
.powered_up = tc2_pm_powered_up,
295
240
};
296
241
297
242
static bool __init tc2_pm_usage_count_init(void)
···
326
269
static int __init tc2_pm_init(void)
327
270
{
328
271
int ret, irq;
329
-
void __iomem *scc;
330
272
u32 a15_cluster_id, a7_cluster_id, sys_info;
331
273
struct device_node *np;
332
274
+9
-4
drivers/gpio/gpio-twl4030.c
+9
-4
drivers/gpio/gpio-twl4030.c
···
354
354
static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
355
355
{
356
356
struct gpio_twl4030_priv *priv = to_gpio_twl4030(chip);
357
+
int ret = -EINVAL;
357
358
358
359
mutex_lock(&priv->mutex);
359
360
if (offset < TWL4030_GPIO_MAX)
360
-
twl4030_set_gpio_dataout(offset, value);
361
+
ret = twl4030_set_gpio_direction(offset, 0);
361
362
362
363
priv->direction |= BIT(offset);
363
364
mutex_unlock(&priv->mutex);
364
365
365
366
twl_set(chip, offset, value);
366
367
367
-
return 0;
368
+
return ret;
368
369
}
369
370
370
371
static int twl_to_irq(struct gpio_chip *chip, unsigned offset)
···
436
435
437
436
static int gpio_twl4030_remove(struct platform_device *pdev);
438
437
439
-
static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
438
+
static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev,
439
+
struct twl4030_gpio_platform_data *pdata)
440
440
{
441
441
struct twl4030_gpio_platform_data *omap_twl_info;
442
442
443
443
omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
444
444
if (!omap_twl_info)
445
445
return NULL;
446
+
447
+
if (pdata)
448
+
*omap_twl_info = *pdata;
446
449
447
450
omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
448
451
"ti,use-leds");
···
505
500
mutex_init(&priv->mutex);
506
501
507
502
if (node)
508
-
pdata = of_gpio_twl4030(&pdev->dev);
503
+
pdata = of_gpio_twl4030(&pdev->dev, pdata);
509
504
510
505
if (pdata == NULL) {
511
506
dev_err(&pdev->dev, "Platform data is missing\n");
+22
drivers/i2c/busses/i2c-omap.c
+22
drivers/i2c/busses/i2c-omap.c
···
1037
1037
};
1038
1038
1039
1039
#ifdef CONFIG_OF
1040
+
static struct omap_i2c_bus_platform_data omap2420_pdata = {
1041
+
.rev = OMAP_I2C_IP_VERSION_1,
1042
+
.flags = OMAP_I2C_FLAG_NO_FIFO |
1043
+
OMAP_I2C_FLAG_SIMPLE_CLOCK |
1044
+
OMAP_I2C_FLAG_16BIT_DATA_REG |
1045
+
OMAP_I2C_FLAG_BUS_SHIFT_2,
1046
+
};
1047
+
1048
+
static struct omap_i2c_bus_platform_data omap2430_pdata = {
1049
+
.rev = OMAP_I2C_IP_VERSION_1,
1050
+
.flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1051
+
OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1052
+
};
1053
+
1040
1054
static struct omap_i2c_bus_platform_data omap3_pdata = {
1041
1055
.rev = OMAP_I2C_IP_VERSION_1,
1042
1056
.flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
···
1068
1054
{
1069
1055
.compatible = "ti,omap3-i2c",
1070
1056
.data = &omap3_pdata,
1057
+
},
1058
+
{
1059
+
.compatible = "ti,omap2430-i2c",
1060
+
.data = &omap2430_pdata,
1061
+
},
1062
+
{
1063
+
.compatible = "ti,omap2420-i2c",
1064
+
.data = &omap2420_pdata,
1071
1065
},
1072
1066
{ },
1073
1067
};
+27
include/linux/tegra-powergate.h
+27
include/linux/tegra-powergate.h
···
45
45
46
46
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
47
47
48
+
#ifdef CONFIG_ARCH_TEGRA
48
49
int tegra_powergate_is_powered(int id);
49
50
int tegra_powergate_power_on(int id);
50
51
int tegra_powergate_power_off(int id);
···
53
52
54
53
/* Must be called with clk disabled, and returns with clk enabled */
55
54
int tegra_powergate_sequence_power_up(int id, struct clk *clk);
55
+
#else
56
+
static inline int tegra_powergate_is_powered(int id)
57
+
{
58
+
return -ENOSYS;
59
+
}
60
+
61
+
static inline int tegra_powergate_power_on(int id)
62
+
{
63
+
return -ENOSYS;
64
+
}
65
+
66
+
static inline int tegra_powergate_power_off(int id)
67
+
{
68
+
return -ENOSYS;
69
+
}
70
+
71
+
static inline int tegra_powergate_remove_clamping(int id)
72
+
{
73
+
return -ENOSYS;
74
+
}
75
+
76
+
static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk)
77
+
{
78
+
return -ENOSYS;
79
+
}
80
+
#endif
56
81
57
82
#endif /* _MACH_TEGRA_POWERGATE_H_ */