Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
scsi: firmware: xilinx: Add APIs for UFS PHY initialization
- Add APIs for UFS PHY initialization.
- Verify M-PHY TX-RX configuration readiness.
- Confirm SRAM initialization and Set SRAM bypass.
- Retrieve UFS calibration values.
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Acked-by: Bart Van Assche <bvanassche@acm.org>
Link: https://patch.msgid.link/20251021113003.13650-4-ajay.neeli@amd.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
authored by
Ajay Neeli
and committed by
Martin K. Petersen
0e4d26f7
00b3e848
+158
-1
+1
-1
drivers/firmware/xilinx/Makefile
+1
-1
drivers/firmware/xilinx/Makefile
+118
drivers/firmware/xilinx/zynqmp-ufs.c
+118
drivers/firmware/xilinx/zynqmp-ufs.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Firmware Layer for UFS APIs
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*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*/
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#include <linux/firmware/xlnx-zynqmp.h>
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#include <linux/module.h>
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/* Register Node IDs */
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#define PM_REGNODE_PMC_IOU_SLCR 0x30000002 /* PMC IOU SLCR */
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#define PM_REGNODE_EFUSE_CACHE 0x30000003 /* EFUSE Cache */
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/* Register Offsets for PMC IOU SLCR */
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#define SRAM_CSR_OFFSET 0x104C /* SRAM Control and Status */
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#define TXRX_CFGRDY_OFFSET 0x1054 /* M-PHY TX-RX Config ready */
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/* Masks for SRAM Control and Status Register */
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#define SRAM_CSR_INIT_DONE_MASK BIT(0) /* SRAM initialization done */
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#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1) /* SRAM External load done */
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#define SRAM_CSR_BYPASS_MASK BIT(2) /* Bypass SRAM interface */
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/* Mask to check M-PHY TX-RX configuration readiness */
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#define TX_RX_CFG_RDY_MASK GENMASK(3, 0)
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/* Register Offsets for EFUSE Cache */
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#define UFS_CAL_1_OFFSET 0xBE8 /* UFS Calibration Value */
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/**
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* zynqmp_pm_is_mphy_tx_rx_config_ready - check M-PHY TX-RX config readiness
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* @is_ready: Store output status (true/false)
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready)
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{
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u32 regval;
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int ret;
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if (!is_ready)
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return -EINVAL;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, TXRX_CFGRDY_OFFSET, ®val);
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if (ret)
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return ret;
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regval &= TX_RX_CFG_RDY_MASK;
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if (regval)
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*is_ready = true;
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else
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*is_ready = false;
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_is_mphy_tx_rx_config_ready);
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/**
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* zynqmp_pm_is_sram_init_done - check SRAM initialization
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* @is_done: Store output status (true/false)
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_is_sram_init_done(bool *is_done)
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{
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u32 regval;
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int ret;
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if (!is_done)
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return -EINVAL;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, ®val);
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if (ret)
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return ret;
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regval &= SRAM_CSR_INIT_DONE_MASK;
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if (regval)
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*is_done = true;
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else
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*is_done = false;
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return ret;
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_is_sram_init_done);
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/**
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* zynqmp_pm_set_sram_bypass - Set SRAM bypass Control
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_set_sram_bypass(void)
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{
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u32 sram_csr;
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int ret;
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ret = zynqmp_pm_sec_read_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET, &sram_csr);
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if (ret)
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return ret;
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sram_csr &= ~SRAM_CSR_EXT_LD_DONE_MASK;
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sram_csr |= SRAM_CSR_BYPASS_MASK;
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return zynqmp_pm_sec_mask_write_reg(PM_REGNODE_PMC_IOU_SLCR, SRAM_CSR_OFFSET,
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GENMASK(2, 1), sram_csr);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_set_sram_bypass);
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/**
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* zynqmp_pm_get_ufs_calibration_values - Read UFS calibration values
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* @val: Store the calibration value
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*
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* Return: Returns 0 on success or error value on failure.
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*/
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int zynqmp_pm_get_ufs_calibration_values(u32 *val)
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{
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return zynqmp_pm_sec_read_reg(PM_REGNODE_EFUSE_CACHE, UFS_CAL_1_OFFSET, val);
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}
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EXPORT_SYMBOL_GPL(zynqmp_pm_get_ufs_calibration_values);
+38
include/linux/firmware/xlnx-zynqmp-ufs.h
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include/linux/firmware/xlnx-zynqmp-ufs.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Firmware layer for UFS APIs.
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*
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* Copyright (c) 2025 Advanced Micro Devices, Inc.
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*/
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#ifndef __FIRMWARE_XLNX_ZYNQMP_UFS_H__
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#define __FIRMWARE_XLNX_ZYNQMP_UFS_H__
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#if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
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int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready);
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int zynqmp_pm_is_sram_init_done(bool *is_done);
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int zynqmp_pm_set_sram_bypass(void);
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int zynqmp_pm_get_ufs_calibration_values(u32 *val);
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#else
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static inline int zynqmp_pm_is_mphy_tx_rx_config_ready(bool *is_ready)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_is_sram_init_done(bool *is_done)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_set_sram_bypass(void)
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{
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return -ENODEV;
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}
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static inline int zynqmp_pm_get_ufs_calibration_values(u32 *val)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __FIRMWARE_XLNX_ZYNQMP_UFS_H__ */