Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtf fixes from Miquel Raynal:
- Fix the memory organization structure of a Macronix SPI-NAND chip.
- Fix a build dependency wrongly described.
- Fix the sunxi NAND driver for A23/A33 SoCs by (a) reverting the
faulty commit introducing broken DMA support and (b) applying another
commit bringing working DMA support.
* tag 'mtd/fixes-for-5.2-final' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: rawnand: sunxi: Add A23/A33 DMA support with extra MBUS configuration
Revert "mtd: rawnand: sunxi: Add A23/A33 DMA support"
mtd: rawnand: ingenic: Fix ingenic_ecc dependency
mtd: spinand: Fix max_bad_eraseblocks_per_lun info in memorg
+22
-39
+1
-1
drivers/mtd/nand/raw/ingenic/Kconfig
+1
-1
drivers/mtd/nand/raw/ingenic/Kconfig
+3
-1
drivers/mtd/nand/raw/ingenic/Makefile
+3
-1
drivers/mtd/nand/raw/ingenic/Makefile
···
2
2
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
3
3
obj-$(CONFIG_MTD_NAND_JZ4780) += ingenic_nand.o
4
4
5
-
obj-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
5
+
ingenic_nand-y += ingenic_nand_drv.o
6
+
ingenic_nand-$(CONFIG_MTD_NAND_INGENIC_ECC) += ingenic_ecc.o
7
+
6
8
obj-$(CONFIG_MTD_NAND_JZ4740_ECC) += jz4740_ecc.o
7
9
obj-$(CONFIG_MTD_NAND_JZ4725B_BCH) += jz4725b_bch.o
8
10
obj-$(CONFIG_MTD_NAND_JZ4780_BCH) += jz4780_bch.o
-9
drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
-9
drivers/mtd/nand/raw/ingenic/ingenic_ecc.c
···
30
30
{
31
31
return ecc->ops->calculate(ecc, params, buf, ecc_code);
32
32
}
33
-
EXPORT_SYMBOL(ingenic_ecc_calculate);
34
33
35
34
/**
36
35
* ingenic_ecc_correct() - detect and correct bit errors
···
50
51
{
51
52
return ecc->ops->correct(ecc, params, buf, ecc_code);
52
53
}
53
-
EXPORT_SYMBOL(ingenic_ecc_correct);
54
54
55
55
/**
56
56
* ingenic_ecc_get() - get the ECC controller device
···
109
111
}
110
112
return ecc;
111
113
}
112
-
EXPORT_SYMBOL(of_ingenic_ecc_get);
113
114
114
115
/**
115
116
* ingenic_ecc_release() - release the ECC controller device
···
119
122
clk_disable_unprepare(ecc->clk);
120
123
put_device(ecc->dev);
121
124
}
122
-
EXPORT_SYMBOL(ingenic_ecc_release);
123
125
124
126
int ingenic_ecc_probe(struct platform_device *pdev)
125
127
{
···
155
159
return 0;
156
160
}
157
161
EXPORT_SYMBOL(ingenic_ecc_probe);
158
-
159
-
MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
160
-
MODULE_AUTHOR("Harvey Hunt <harveyhuntnexus@gmail.com>");
161
-
MODULE_DESCRIPTION("Ingenic ECC common driver");
162
-
MODULE_LICENSE("GPL v2");
drivers/mtd/nand/raw/ingenic/ingenic_nand.c
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
drivers/mtd/nand/raw/ingenic/ingenic_nand.c
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+15
-25
drivers/mtd/nand/raw/sunxi_nand.c
+15
-25
drivers/mtd/nand/raw/sunxi_nand.c
···
51
51
#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4))
52
52
#define NFC_REG_SPARE_AREA 0x00A0
53
53
#define NFC_REG_PAT_ID 0x00A4
54
+
#define NFC_REG_MDMA_CNT 0x00C4
54
55
#define NFC_RAM0_BASE 0x0400
55
56
#define NFC_RAM1_BASE 0x0800
56
57
···
70
69
#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
71
70
#define NFC_SAM BIT(12)
72
71
#define NFC_RAM_METHOD BIT(14)
72
+
#define NFC_DMA_TYPE_NORMAL BIT(15)
73
73
#define NFC_DEBUG_CTL BIT(31)
74
74
75
75
/* define bit use in NFC_ST */
···
207
205
* NAND Controller capabilities structure: stores NAND controller capabilities
208
206
* for distinction between compatible strings.
209
207
*
210
-
* @sram_through_ahb: On A23, we choose to access the internal RAM through AHB
211
-
* instead of MBUS (less configuration). A10, A10s, A13 and
212
-
* A20 use the MBUS but no extra configuration is needed.
208
+
* @extra_mbus_conf: Contrary to A10, A10s and A13, accessing internal RAM
209
+
* through MBUS on A23/A33 needs extra configuration.
213
210
* @reg_io_data: I/O data register
214
211
* @dma_maxburst: DMA maxburst
215
212
*/
216
213
struct sunxi_nfc_caps {
217
-
bool sram_through_ahb;
214
+
bool extra_mbus_conf;
218
215
unsigned int reg_io_data;
219
216
unsigned int dma_maxburst;
220
217
};
···
369
368
goto err_unmap_buf;
370
369
}
371
370
372
-
/*
373
-
* On A23, we suppose the "internal RAM" (p.12 of the NFC user manual)
374
-
* refers to the NAND controller's internal SRAM. This memory is mapped
375
-
* and so is accessible from the AHB. It seems that it can also be
376
-
* accessed by the MBUS. MBUS accesses are mandatory when using the
377
-
* internal DMA instead of the external DMA engine.
378
-
*
379
-
* During DMA I/O operation, either we access this memory from the AHB
380
-
* by clearing the NFC_RAM_METHOD bit, or we set the bit and use the
381
-
* MBUS. In this case, we should also configure the MBUS DMA length
382
-
* NFC_REG_MDMA_CNT(0xC4) to be chunksize * nchunks. NAND I/O over MBUS
383
-
* are also limited to 32kiB pages.
384
-
*/
385
-
if (nfc->caps->sram_through_ahb)
386
-
writel(readl(nfc->regs + NFC_REG_CTL) & ~NFC_RAM_METHOD,
387
-
nfc->regs + NFC_REG_CTL);
388
-
else
389
-
writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
390
-
nfc->regs + NFC_REG_CTL);
391
-
371
+
writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RAM_METHOD,
372
+
nfc->regs + NFC_REG_CTL);
392
373
writel(nchunks, nfc->regs + NFC_REG_SECTOR_NUM);
393
374
writel(chunksize, nfc->regs + NFC_REG_CNT);
375
+
if (nfc->caps->extra_mbus_conf)
376
+
writel(chunksize * nchunks, nfc->regs + NFC_REG_MDMA_CNT);
394
377
395
378
dmat = dmaengine_submit(dmad);
396
379
···
2136
2151
dmac_cfg.src_maxburst = nfc->caps->dma_maxburst;
2137
2152
dmac_cfg.dst_maxburst = nfc->caps->dma_maxburst;
2138
2153
dmaengine_slave_config(nfc->dmac, &dmac_cfg);
2154
+
2155
+
if (nfc->caps->extra_mbus_conf)
2156
+
writel(readl(nfc->regs + NFC_REG_CTL) |
2157
+
NFC_DMA_TYPE_NORMAL, nfc->regs + NFC_REG_CTL);
2158
+
2139
2159
} else {
2140
2160
dev_warn(dev, "failed to request rxtx DMA channel\n");
2141
2161
}
···
2190
2200
};
2191
2201
2192
2202
static const struct sunxi_nfc_caps sunxi_nfc_a23_caps = {
2193
-
.sram_through_ahb = true,
2203
+
.extra_mbus_conf = true,
2194
2204
.reg_io_data = NFC_REG_A23_IO_DATA,
2195
2205
.dma_maxburst = 8,
2196
2206
};
+1
-1
drivers/mtd/nand/spi/gigadevice.c
+1
-1
drivers/mtd/nand/spi/gigadevice.c
···
180
180
SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
181
181
gd5fxgq4xa_ecc_get_status)),
182
182
SPINAND_INFO("GD5F4GQ4xA", 0xF4,
183
-
NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1),
183
+
NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),
184
184
NAND_ECCREQ(8, 512),
185
185
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
186
186
&write_cache_variants,
+2
-2
drivers/mtd/nand/spi/macronix.c
+2
-2
drivers/mtd/nand/spi/macronix.c
···
100
100
101
101
static const struct spinand_info macronix_spinand_table[] = {
102
102
SPINAND_INFO("MX35LF1GE4AB", 0x12,
103
-
NAND_MEMORG(1, 2048, 64, 64, 1024, 40, 1, 1, 1),
103
+
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
104
104
NAND_ECCREQ(4, 512),
105
105
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
106
106
&write_cache_variants,
···
109
109
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
110
110
mx35lf1ge4ab_ecc_get_status)),
111
111
SPINAND_INFO("MX35LF2GE4AB", 0x22,
112
-
NAND_MEMORG(1, 2048, 64, 64, 2048, 20, 2, 1, 1),
112
+
NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 2, 1, 1),
113
113
NAND_ECCREQ(4, 512),
114
114
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
115
115
&write_cache_variants,