tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amdgpu: Add CU mask support for MQD properties

Add new fields to the amdgpu_mqd_prop structure to track CU (Compute Unit)
mask information, including the mask itself, count, flags, and a flag to
indicate if user-specified CU masking is active.

v2: Create a generic function amdgpu_gfx_mqd_symmetrically_map_cu_mask()

Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <jesse.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Jesse.Zhang and committed by
Alex Deucher 0ea55604 c26ad36d

+61
+10
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 791 791 (rid == 0x01) || \ 792 792 (rid == 0x10)))) 793 793 794 + enum amdgpu_mqd_update_flag { 795 + AMDGPU_UPDATE_FLAG_DBG_WA_ENABLE = 1, 796 + AMDGPU_UPDATE_FLAG_DBG_WA_DISABLE = 2, 797 + AMDGPU_UPDATE_FLAG_IS_GWS = 4, /* quirk for gfx9 IP */ 798 + }; 799 + 794 800 struct amdgpu_mqd_prop { 795 801 uint64_t mqd_gpu_addr; 796 802 uint64_t hqd_base_gpu_addr; ··· 817 811 uint64_t fence_address; 818 812 bool tmz_queue; 819 813 bool kernel_queue; 814 + uint32_t *cu_mask; 815 + uint32_t cu_mask_count; 816 + uint32_t cu_flags; 817 + bool is_user_cu_masked; 820 818 }; 821 819 822 820 struct amdgpu_mqd {
+49
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
··· 503 503 &ring->mqd_ptr); 504 504 } 505 505 506 + void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, 507 + uint32_t cu_mask_count, uint32_t *se_mask) 508 + { 509 + struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 510 + struct amdgpu_gfx_config *gfx_info = &adev->gfx.config; 511 + uint32_t cu_per_sh[8][4] = {0}; 512 + int i, se, sh, cu, cu_bitmap_sh_mul; 513 + int xcc_inst = ffs(adev->gfx.xcc_mask) - 1; 514 + bool wgp_mode_req = amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(10, 0, 0); 515 + int cu_inc = wgp_mode_req ? 2 : 1; 516 + uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; 517 + int num_xcc, inc, inst = 0; 518 + 519 + if (xcc_inst < 0) 520 + xcc_inst = 0; 521 + 522 + num_xcc = hweight16(adev->gfx.xcc_mask); 523 + if (!num_xcc) 524 + num_xcc = 1; 525 + 526 + inc = cu_inc * num_xcc; 527 + 528 + cu_bitmap_sh_mul = 2; 529 + 530 + for (se = 0; se < gfx_info->max_shader_engines; se++) 531 + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) 532 + cu_per_sh[se][sh] = hweight32( 533 + cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * 534 + cu_bitmap_sh_mul]); 535 + 536 + for (i = 0; i < gfx_info->max_shader_engines; i++) 537 + se_mask[i] = 0; 538 + 539 + i = inst; 540 + for (cu = 0; cu < 16; cu += cu_inc) { 541 + for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { 542 + for (se = 0; se < gfx_info->max_shader_engines; se++) { 543 + if (cu_per_sh[se][sh] > cu) { 544 + if ((i / 32) < cu_mask_count && (cu_mask[i / 32] & (1 << (i % 32)))) 545 + se_mask[se] |= en_mask << (cu + sh * 16); 546 + i += inc; 547 + if (i >= cu_mask_count * 32) 548 + return; 549 + } 550 + } 551 + } 552 + } 553 + } 554 + 506 555 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) 507 556 { 508 557 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
··· 583 583 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 584 584 unsigned mqd_size, int xcc_id); 585 585 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id); 586 + void amdgpu_gfx_mqd_symmetrically_map_cu_mask(struct amdgpu_device *adev, const uint32_t *cu_mask, 587 + uint32_t cu_mask_count, uint32_t *se_mask); 586 588 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id); 587 589 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id); 588 590 int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id);