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drm/amdgpu: add vcn_v2_5 ip dump support

Add support of vcn ip dump in the devcoredump
for vcn_v2_5.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Sunil Khatri and committed by
Alex Deucher
0eea81ee b910cacb

+79 -1
+79 -1
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
··· 55 55 56 56 #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 57 57 58 + static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = { 59 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 60 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), 61 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), 62 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), 63 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), 64 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), 65 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), 66 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), 67 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), 68 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), 69 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), 70 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), 71 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), 72 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), 73 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), 74 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), 75 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 76 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), 77 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), 78 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), 79 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), 80 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), 81 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), 82 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), 83 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), 84 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), 85 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), 86 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), 87 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), 88 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), 89 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), 90 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), 91 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), 92 + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) 93 + }; 94 + 58 95 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); 59 96 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); 60 97 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); ··· 159 122 { 160 123 struct amdgpu_ring *ring; 161 124 int i, j, r; 125 + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 126 + uint32_t *ptr; 162 127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 163 128 164 129 for (j = 0; j < adev->vcn.num_vcn_inst; j++) { ··· 280 241 if (r) 281 242 return r; 282 243 244 + /* Allocate memory for VCN IP Dump buffer */ 245 + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); 246 + if (!ptr) { 247 + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); 248 + adev->vcn.ip_dump = NULL; 249 + } else { 250 + adev->vcn.ip_dump = ptr; 251 + } 252 + 283 253 return 0; 284 254 } 285 255 ··· 324 276 return r; 325 277 326 278 r = amdgpu_vcn_sw_fini(adev); 279 + 280 + kfree(adev->vcn.ip_dump); 327 281 328 282 return r; 329 283 } ··· 1926 1876 } 1927 1877 } 1928 1878 1879 + static void vcn_v2_5_dump_ip_state(void *handle) 1880 + { 1881 + struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1882 + int i, j; 1883 + bool is_powered; 1884 + uint32_t inst_off; 1885 + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); 1886 + 1887 + if (!adev->vcn.ip_dump) 1888 + return; 1889 + 1890 + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1891 + if (adev->vcn.harvest_config & (1 << i)) 1892 + continue; 1893 + 1894 + inst_off = i * reg_count; 1895 + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ 1896 + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); 1897 + is_powered = (adev->vcn.ip_dump[inst_off] & 1898 + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; 1899 + 1900 + if (is_powered) 1901 + for (j = 1; j < reg_count; j++) 1902 + adev->vcn.ip_dump[inst_off + j] = 1903 + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i)); 1904 + } 1905 + } 1906 + 1929 1907 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { 1930 1908 .name = "vcn_v2_5", 1931 1909 .early_init = vcn_v2_5_early_init, ··· 1972 1894 .post_soft_reset = NULL, 1973 1895 .set_clockgating_state = vcn_v2_5_set_clockgating_state, 1974 1896 .set_powergating_state = vcn_v2_5_set_powergating_state, 1975 - .dump_ip_state = NULL, 1897 + .dump_ip_state = vcn_v2_5_dump_ip_state, 1976 1898 .print_ip_state = NULL, 1977 1899 }; 1978 1900