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PCI: dwc: Disable BARs in common code instead of in each glue driver

The current EPC core design relies on an EPC driver disabling all BARs by
default. An EPF driver will then enable the BARs that it wants to enabled.

This design is there because there is no epc->ops->disable_bar().
(There is a epc->ops->clear_bar(), but that is only to disable a BAR that
has been enabled using epc->ops->set_bar() first.)

By default, an EPF driver will not be able to get/enable BARs that are
marked as BAR_RESERVED or BAR_DISABLED (see pci_epc_get_next_free_bar()).

Since the current EPC code design requires an EPC driver to disable all
BARs by default, move this to DWC common code from each glue driver.

BAR_RESERVED BARs are not disabled by default because these BARs are
hardware backed, and should only be disabled explicitly by an EPF driver
if absolutely necessary for the EPF driver to function correctly.
(This is similar to how e.g. NVMe may have vendor specific BARs outside of
the mandatory BAR0 which contains the NVMe registers.)

Note that there is currently no EPC operation to disable a BAR that has not
first been programmed using pci_epc_set_bar(). If an EPF driver ever wants
to disable a BAR marked as BAR_RESERVED, a disable_bar() operation would
have to be added first.

No functional changes intended.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested-by: Koichiro Den <den@valinux.co.jp>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260312130229.2282001-19-cassel@kernel.org

authored by

Niklas Cassel and committed by
Manivannan Sadhasivam 0f08179c 5a95fecb

+25 -89
-4
drivers/pci/controller/dwc/pci-dra7xx.c
··· 378 378 { 379 379 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 380 380 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); 381 - enum pci_barno bar; 382 - 383 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 384 - dw_pcie_ep_reset_bar(pci, bar); 385 381 386 382 dra7xx_pcie_enable_wrapper_interrupts(dra7xx); 387 383 }
-10
drivers/pci/controller/dwc/pci-imx6.c
··· 1401 1401 .stop_link = imx_pcie_stop_link, 1402 1402 }; 1403 1403 1404 - static void imx_pcie_ep_init(struct dw_pcie_ep *ep) 1405 - { 1406 - enum pci_barno bar; 1407 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1408 - 1409 - for (bar = BAR_0; bar <= BAR_5; bar++) 1410 - dw_pcie_ep_reset_bar(pci, bar); 1411 - } 1412 - 1413 1404 static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1414 1405 unsigned int type, u16 interrupt_num) 1415 1406 { ··· 1469 1478 } 1470 1479 1471 1480 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1472 - .init = imx_pcie_ep_init, 1473 1481 .raise_irq = imx_pcie_ep_raise_irq, 1474 1482 .get_features = imx_pcie_ep_get_features, 1475 1483 };
-4
drivers/pci/controller/dwc/pci-layerscape-ep.c
··· 152 152 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 153 153 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci); 154 154 struct dw_pcie_ep_func *ep_func; 155 - enum pci_barno bar; 156 155 157 156 ep_func = dw_pcie_ep_get_func_from_ep(ep, 0); 158 157 if (!ep_func) 159 158 return; 160 - 161 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 162 - dw_pcie_ep_reset_bar(pci, bar); 163 159 164 160 pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false; 165 161 pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
-4
drivers/pci/controller/dwc/pcie-artpec6.c
··· 340 340 { 341 341 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 342 342 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci); 343 - enum pci_barno bar; 344 343 345 344 artpec6_pcie_assert_core_reset(artpec6_pcie); 346 345 artpec6_pcie_init_phy(artpec6_pcie); 347 346 artpec6_pcie_deassert_core_reset(artpec6_pcie); 348 347 artpec6_pcie_wait_for_phy(artpec6_pcie); 349 - 350 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 351 - dw_pcie_ep_reset_bar(pci, bar); 352 348 } 353 349 354 350 static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+24
drivers/pci/controller/dwc/pcie-designware-ep.c
··· 1114 1114 dw_pcie_dbi_ro_wr_dis(pci); 1115 1115 } 1116 1116 1117 + static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep) 1118 + { 1119 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1120 + enum pci_epc_bar_type bar_type; 1121 + enum pci_barno bar; 1122 + 1123 + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 1124 + bar_type = dw_pcie_ep_get_bar_type(ep, bar); 1125 + 1126 + /* 1127 + * Reserved BARs should not get disabled by default. All other 1128 + * BAR types are disabled by default. 1129 + * 1130 + * This is in line with the current EPC core design, where all 1131 + * BARs are disabled by default, and then the EPF driver enables 1132 + * the BARs it wishes to use. 1133 + */ 1134 + if (bar_type != BAR_RESERVED) 1135 + dw_pcie_ep_reset_bar(pci, bar); 1136 + } 1137 + } 1138 + 1117 1139 /** 1118 1140 * dw_pcie_ep_init_registers - Initialize DWC EP specific registers 1119 1141 * @ep: DWC EP device ··· 1217 1195 1218 1196 if (ep->ops->init) 1219 1197 ep->ops->init(ep); 1198 + 1199 + dw_pcie_ep_disable_bars(ep); 1220 1200 1221 1201 /* 1222 1202 * PCIe r6.0, section 7.9.15 states that for endpoints that support
-10
drivers/pci/controller/dwc/pcie-designware-plat.c
··· 32 32 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = { 33 33 }; 34 34 35 - static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) 36 - { 37 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 38 - enum pci_barno bar; 39 - 40 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 41 - dw_pcie_ep_reset_bar(pci, bar); 42 - } 43 - 44 35 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 45 36 unsigned int type, u16 interrupt_num) 46 37 { ··· 64 73 } 65 74 66 75 static const struct dw_pcie_ep_ops pcie_ep_ops = { 67 - .init = dw_plat_pcie_ep_init, 68 76 .raise_irq = dw_plat_pcie_ep_raise_irq, 69 77 .get_features = dw_plat_pcie_get_features, 70 78 };
+1 -7
drivers/pci/controller/dwc/pcie-dw-rockchip.c
··· 361 361 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) 362 362 { 363 363 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 364 - enum pci_barno bar; 365 364 366 365 rockchip_pcie_enable_l0s(pci); 367 366 rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); 368 - 369 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 370 - dw_pcie_ep_reset_bar(pci, bar); 371 367 }; 372 368 373 369 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, ··· 411 415 /* 412 416 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of 413 417 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver, 414 - * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by 415 - * default.) If the host could write to BAR4, the iATU settings (for all other 416 - * BARs) would be overwritten, resulting in (all other BARs) no longer working. 418 + * so mark it as RESERVED. 417 419 */ 418 420 static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = { 419 421 DWC_EPC_COMMON_FEATURES,
-10
drivers/pci/controller/dwc/pcie-qcom-ep.c
··· 859 859 return &qcom_pcie_epc_features; 860 860 } 861 861 862 - static void qcom_pcie_ep_init(struct dw_pcie_ep *ep) 863 - { 864 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 865 - enum pci_barno bar; 866 - 867 - for (bar = BAR_0; bar <= BAR_5; bar++) 868 - dw_pcie_ep_reset_bar(pci, bar); 869 - } 870 - 871 862 static const struct dw_pcie_ep_ops pci_ep_ops = { 872 - .init = qcom_pcie_ep_init, 873 863 .raise_irq = qcom_pcie_ep_raise_irq, 874 864 .get_features = qcom_pcie_epc_get_features, 875 865 };
-10
drivers/pci/controller/dwc/pcie-rcar-gen4.c
··· 386 386 writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN); 387 387 } 388 388 389 - static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep) 390 - { 391 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 392 - enum pci_barno bar; 393 - 394 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 395 - dw_pcie_ep_reset_bar(pci, bar); 396 - } 397 - 398 389 static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar) 399 390 { 400 391 writel(0, rcar->base + PCIEDMAINTSTSEN); ··· 440 449 441 450 static const struct dw_pcie_ep_ops pcie_ep_ops = { 442 451 .pre_init = rcar_gen4_pcie_ep_pre_init, 443 - .init = rcar_gen4_pcie_ep_init, 444 452 .raise_irq = rcar_gen4_pcie_ep_raise_irq, 445 453 .get_features = rcar_gen4_pcie_ep_get_features, 446 454 .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
-10
drivers/pci/controller/dwc/pcie-stm32-ep.c
··· 28 28 unsigned int perst_irq; 29 29 }; 30 30 31 - static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) 32 - { 33 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 34 - enum pci_barno bar; 35 - 36 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 37 - dw_pcie_ep_reset_bar(pci, bar); 38 - } 39 - 40 31 static int stm32_pcie_start_link(struct dw_pcie *pci) 41 32 { 42 33 struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); ··· 73 82 } 74 83 75 84 static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = { 76 - .init = stm32_pcie_ep_init, 77 85 .raise_irq = stm32_pcie_raise_irq, 78 86 .get_features = stm32_pcie_get_features, 79 87 };
-10
drivers/pci/controller/dwc/pcie-tegra194.c
··· 1923 1923 return IRQ_HANDLED; 1924 1924 } 1925 1925 1926 - static void tegra_pcie_ep_init(struct dw_pcie_ep *ep) 1927 - { 1928 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1929 - enum pci_barno bar; 1930 - 1931 - for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) 1932 - dw_pcie_ep_reset_bar(pci, bar); 1933 - }; 1934 - 1935 1926 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq) 1936 1927 { 1937 1928 /* Tegra194 supports only INTA */ ··· 1998 2007 } 1999 2008 2000 2009 static const struct dw_pcie_ep_ops pcie_ep_ops = { 2001 - .init = tegra_pcie_ep_init, 2002 2010 .raise_irq = tegra_pcie_ep_raise_irq, 2003 2011 .get_features = tegra_pcie_ep_get_features, 2004 2012 };
-10
drivers/pci/controller/dwc/pcie-uniphier-ep.c
··· 203 203 uniphier_pcie_ltssm_enable(priv, false); 204 204 } 205 205 206 - static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep) 207 - { 208 - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 209 - enum pci_barno bar; 210 - 211 - for (bar = BAR_0; bar <= BAR_5; bar++) 212 - dw_pcie_ep_reset_bar(pci, bar); 213 - } 214 - 215 206 static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep) 216 207 { 217 208 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ··· 274 283 } 275 284 276 285 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = { 277 - .init = uniphier_pcie_ep_init, 278 286 .raise_irq = uniphier_pcie_ep_raise_irq, 279 287 .get_features = uniphier_pcie_get_features, 280 288 };