Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arm-fixes-6.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"The final bug fixes for Qualcomm and Rockchips came in, all of them
for devicetree files:
- Devices on Qualcomm SC7180/SC7280 that are cache coherent are now
marked so correctly to fix a regression after a change in kernel
behavior
- Rockchips has a few minor changes for correctness of regulator and
cache properties, as well as fixes for incorrect behavior of the
RK3568 PCI controller and reset pins on two boards"
* tag 'arm-fixes-6.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
arm64: dts: qcom: sc7280: Mark SCM as dma-coherent for chrome devices
arm64: dts: qcom: sc7180: Mark SCM as dma-coherent for trogdor
arm64: dts: qcom: sc7180: Mark SCM as dma-coherent for IDP
dt-bindings: firmware: qcom,scm: Document that SCM can be dma-coherent
arm64: dts: rockchip: Fix rk356x PCIe register and range mappings
arm64: dts: rockchip: fix button reset pin for nanopi r5c
arm64: dts: rockchip: fix nEXTRST on SOQuartz
arm64: dts: rockchip: add missing cache properties
arm64: dts: rockchip: fix USB regulator on ROCK64
+69
-48
+2
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+2
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+5
arch/arm64/boot/dts/qcom/sc7180-idp.dts
+5
arch/arm64/boot/dts/qcom/sc7180-idp.dts
+5
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+5
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7180.dtsi
+5
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+5
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280.dtsi
+1
-1
arch/arm64/boot/dts/qcom/sc7280.dtsi
+1
arch/arm64/boot/dts/rockchip/rk3308.dtsi
+1
arch/arm64/boot/dts/rockchip/rk3308.dtsi
+2
-12
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+2
-12
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
···
37
37
vin-supply = <&vcc_io>;
38
38
};
39
39
40
-
vcc_host_5v: vcc-host-5v-regulator {
40
+
/* Common enable line for all of the rails mentioned in the labels */
41
+
vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
41
42
compatible = "regulator-fixed";
42
43
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
43
44
pinctrl-names = "default";
44
45
pinctrl-0 = <&usb20_host_drv>;
45
46
regulator-name = "vcc_host_5v";
46
-
regulator-always-on;
47
-
regulator-boot-on;
48
-
vin-supply = <&vcc_sys>;
49
-
};
50
-
51
-
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
52
-
compatible = "regulator-fixed";
53
-
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
54
-
pinctrl-names = "default";
55
-
pinctrl-0 = <&usb20_host_drv>;
56
-
regulator-name = "vcc_host1_5v";
57
47
regulator-always-on;
58
48
regulator-boot-on;
59
49
vin-supply = <&vcc_sys>;
+1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
+1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
+11
-7
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+11
-7
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
···
28
28
regulator-max-microvolt = <5000000>;
29
29
vin-supply = <&vcc12v_dcin>;
30
30
};
31
+
32
+
vcc_sd_pwr: vcc-sd-pwr-regulator {
33
+
compatible = "regulator-fixed";
34
+
regulator-name = "vcc_sd_pwr";
35
+
regulator-always-on;
36
+
regulator-boot-on;
37
+
regulator-min-microvolt = <3300000>;
38
+
regulator-max-microvolt = <3300000>;
39
+
vin-supply = <&vcc3v3_sys>;
40
+
};
31
41
};
32
42
33
43
/* phy for pcie */
···
140
130
};
141
131
142
132
&sdmmc0 {
143
-
vmmc-supply = <&sdmmc_pwr>;
144
-
status = "okay";
145
-
};
146
-
147
-
&sdmmc_pwr {
148
-
regulator-min-microvolt = <3300000>;
149
-
regulator-max-microvolt = <3300000>;
133
+
vmmc-supply = <&vcc_sd_pwr>;
150
134
status = "okay";
151
135
};
152
136
+13
-16
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+13
-16
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
···
104
104
regulator-max-microvolt = <3300000>;
105
105
vin-supply = <&vcc5v0_sys>;
106
106
};
107
-
108
-
sdmmc_pwr: sdmmc-pwr-regulator {
109
-
compatible = "regulator-fixed";
110
-
enable-active-high;
111
-
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
112
-
pinctrl-names = "default";
113
-
pinctrl-0 = <&sdmmc_pwr_h>;
114
-
regulator-name = "sdmmc_pwr";
115
-
status = "disabled";
116
-
};
117
107
};
118
108
119
109
&cpu0 {
···
143
153
rx_delay = <0x10>;
144
154
phy-handle = <&rgmii_phy1>;
145
155
status = "disabled";
156
+
};
157
+
158
+
&gpio0 {
159
+
nextrst-hog {
160
+
gpio-hog;
161
+
/*
162
+
* GPIO_ACTIVE_LOW + output-low here means that the pin is set
163
+
* to high, because output-low decides the value pre-inversion.
164
+
*/
165
+
gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
166
+
line-name = "nEXTRST";
167
+
output-low;
168
+
};
146
169
};
147
170
148
171
&gpu {
···
539
536
sdio-pwrseq {
540
537
wifi_enable_h: wifi-enable-h {
541
538
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
542
-
};
543
-
};
544
-
545
-
sdmmc-pwr {
546
-
sdmmc_pwr_h: sdmmc-pwr-h {
547
-
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
548
539
};
549
540
};
550
541
};
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+1
-1
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+8
-6
arch/arm64/boot/dts/rockchip/rk3568.dtsi
+8
-6
arch/arm64/boot/dts/rockchip/rk3568.dtsi
···
94
94
power-domains = <&power RK3568_PD_PIPE>;
95
95
reg = <0x3 0xc0400000 0x0 0x00400000>,
96
96
<0x0 0xfe270000 0x0 0x00010000>,
97
-
<0x3 0x7f000000 0x0 0x01000000>;
98
-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
99
-
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
97
+
<0x0 0xf2000000 0x0 0x00100000>;
98
+
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
99
+
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
100
+
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
100
101
reg-names = "dbi", "apb", "config";
101
102
resets = <&cru SRST_PCIE30X1_POWERUP>;
102
103
reset-names = "pipe";
···
147
146
power-domains = <&power RK3568_PD_PIPE>;
148
147
reg = <0x3 0xc0800000 0x0 0x00400000>,
149
148
<0x0 0xfe280000 0x0 0x00010000>,
150
-
<0x3 0xbf000000 0x0 0x01000000>;
151
-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
152
-
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
149
+
<0x0 0xf0000000 0x0 0x00100000>;
150
+
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
151
+
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
152
+
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
153
153
reg-names = "dbi", "apb", "config";
154
154
resets = <&cru SRST_PCIE30X2_POWERUP>;
155
155
reset-names = "pipe";
+4
-3
arch/arm64/boot/dts/rockchip/rk356x.dtsi
+4
-3
arch/arm64/boot/dts/rockchip/rk356x.dtsi
···
952
952
compatible = "rockchip,rk3568-pcie";
953
953
reg = <0x3 0xc0000000 0x0 0x00400000>,
954
954
<0x0 0xfe260000 0x0 0x00010000>,
955
-
<0x3 0x3f000000 0x0 0x01000000>;
955
+
<0x0 0xf4000000 0x0 0x00100000>;
956
956
reg-names = "dbi", "apb", "config";
957
957
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
958
958
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
···
982
982
phys = <&combphy2 PHY_TYPE_PCIE>;
983
983
phy-names = "pcie-phy";
984
984
power-domains = <&power RK3568_PD_PIPE>;
985
-
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
986
-
0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
985
+
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
986
+
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
987
+
<0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
987
988
resets = <&cru SRST_PCIE20_POWERUP>;
988
989
reset-names = "pipe";
989
990
#address-cells = <3>;
+9
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+9
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
···
229
229
cache-line-size = <64>;
230
230
cache-sets = <512>;
231
231
cache-level = <2>;
232
+
cache-unified;
232
233
next-level-cache = <&l3_cache>;
233
234
};
234
235
···
239
238
cache-line-size = <64>;
240
239
cache-sets = <512>;
241
240
cache-level = <2>;
241
+
cache-unified;
242
242
next-level-cache = <&l3_cache>;
243
243
};
244
244
···
249
247
cache-line-size = <64>;
250
248
cache-sets = <512>;
251
249
cache-level = <2>;
250
+
cache-unified;
252
251
next-level-cache = <&l3_cache>;
253
252
};
254
253
···
259
256
cache-line-size = <64>;
260
257
cache-sets = <512>;
261
258
cache-level = <2>;
259
+
cache-unified;
262
260
next-level-cache = <&l3_cache>;
263
261
};
264
262
···
269
265
cache-line-size = <64>;
270
266
cache-sets = <1024>;
271
267
cache-level = <2>;
268
+
cache-unified;
272
269
next-level-cache = <&l3_cache>;
273
270
};
274
271
···
279
274
cache-line-size = <64>;
280
275
cache-sets = <1024>;
281
276
cache-level = <2>;
277
+
cache-unified;
282
278
next-level-cache = <&l3_cache>;
283
279
};
284
280
···
289
283
cache-line-size = <64>;
290
284
cache-sets = <1024>;
291
285
cache-level = <2>;
286
+
cache-unified;
292
287
next-level-cache = <&l3_cache>;
293
288
};
294
289
···
299
292
cache-line-size = <64>;
300
293
cache-sets = <1024>;
301
294
cache-level = <2>;
295
+
cache-unified;
302
296
next-level-cache = <&l3_cache>;
303
297
};
304
298
···
309
301
cache-line-size = <64>;
310
302
cache-sets = <4096>;
311
303
cache-level = <3>;
304
+
cache-unified;
312
305
};
313
306
};
314
307