clk: qcom: clk-alpha-pll: Add support for common PLL configuration function

To properly configure the PLLs on recent chipsets, it often requires more
than one power domain to be kept ON. The support to enable multiple power
domains is being added in qcom_cc_really_probe() and PLLs should be
configured post all the required power domains are enabled.

Hence integrate PLL configuration into clk_alpha_pll structure and add
support for qcom_clk_alpha_pll_configure() function which can be called
from qcom_cc_really_probe() to configure the clock controller PLLs after
all required power domains are enabled.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-4-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by

Bjorn Andersson 1 year ago 0f698c16 842fa748

+60

2 changed files

expand all

drivers

clk

qcom

clk-alpha-pll.c

clk-alpha-pll.h

+57

drivers/clk/qcom/clk-alpha-pll.c

··· 63 63 #define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 64 64 #define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 65 65 66 + #define GET_PLL_TYPE(pll) (((pll)->regs - clk_alpha_pll_regs[0]) / PLL_OFF_MAX_REGS) 67 + 66 68 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 67 69 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 68 70 [PLL_OFF_L_VAL] = 0x04, ··· 2962 2960 .set_rate = clk_zonda_pll_set_rate, 2963 2961 }; 2964 2962 EXPORT_SYMBOL_GPL(clk_alpha_pll_regera_ops); 2963 + 2964 + void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap) 2965 + { 2966 + const struct clk_init_data *init = pll->clkr.hw.init; 2967 + 2968 + switch (GET_PLL_TYPE(pll)) { 2969 + case CLK_ALPHA_PLL_TYPE_LUCID_OLE: 2970 + clk_lucid_ole_pll_configure(pll, regmap, pll->config); 2971 + break; 2972 + case CLK_ALPHA_PLL_TYPE_LUCID_EVO: 2973 + clk_lucid_evo_pll_configure(pll, regmap, pll->config); 2974 + break; 2975 + case CLK_ALPHA_PLL_TYPE_TAYCAN_ELU: 2976 + clk_taycan_elu_pll_configure(pll, regmap, pll->config); 2977 + break; 2978 + case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO: 2979 + clk_rivian_evo_pll_configure(pll, regmap, pll->config); 2980 + break; 2981 + case CLK_ALPHA_PLL_TYPE_TRION: 2982 + clk_trion_pll_configure(pll, regmap, pll->config); 2983 + break; 2984 + case CLK_ALPHA_PLL_TYPE_HUAYRA_2290: 2985 + clk_huayra_2290_pll_configure(pll, regmap, pll->config); 2986 + break; 2987 + case CLK_ALPHA_PLL_TYPE_FABIA: 2988 + clk_fabia_pll_configure(pll, regmap, pll->config); 2989 + break; 2990 + case CLK_ALPHA_PLL_TYPE_AGERA: 2991 + clk_agera_pll_configure(pll, regmap, pll->config); 2992 + break; 2993 + case CLK_ALPHA_PLL_TYPE_PONGO_ELU: 2994 + clk_pongo_elu_pll_configure(pll, regmap, pll->config); 2995 + break; 2996 + case CLK_ALPHA_PLL_TYPE_ZONDA: 2997 + case CLK_ALPHA_PLL_TYPE_ZONDA_OLE: 2998 + clk_zonda_pll_configure(pll, regmap, pll->config); 2999 + break; 3000 + case CLK_ALPHA_PLL_TYPE_STROMER: 3001 + case CLK_ALPHA_PLL_TYPE_STROMER_PLUS: 3002 + clk_stromer_pll_configure(pll, regmap, pll->config); 3003 + break; 3004 + case CLK_ALPHA_PLL_TYPE_DEFAULT: 3005 + case CLK_ALPHA_PLL_TYPE_DEFAULT_EVO: 3006 + case CLK_ALPHA_PLL_TYPE_HUAYRA: 3007 + case CLK_ALPHA_PLL_TYPE_HUAYRA_APSS: 3008 + case CLK_ALPHA_PLL_TYPE_BRAMMO: 3009 + case CLK_ALPHA_PLL_TYPE_BRAMMO_EVO: 3010 + clk_alpha_pll_configure(pll, regmap, pll->config); 3011 + break; 3012 + default: 3013 + WARN(1, "%s: invalid pll type\n", init->name); 3014 + break; 3015 + } 3016 + } 3017 + EXPORT_SYMBOL_GPL(qcom_clk_alpha_pll_configure);

drivers/clk/qcom/clk-alpha-pll.h

··· 81 81 * struct clk_alpha_pll - phase locked loop (PLL) 82 82 * @offset: base address of registers 83 83 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 84 + * @config: array of pll settings 84 85 * @vco_table: array of VCO settings 85 86 * @num_vco: number of VCO settings in @vco_table 86 87 * @flags: bitmask to indicate features supported by the hardware ··· 91 90 u32 offset; 92 91 const u8 *regs; 93 92 93 + const struct alpha_pll_config *config; 94 94 const struct pll_vco *vco_table; 95 95 size_t num_vco; 96 96 #define SUPPORTS_OFFLINE_REQ BIT(0) ··· 239 237 const struct alpha_pll_config *config); 240 238 void clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 241 239 const struct alpha_pll_config *config); 240 + void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap); 242 241 243 242 #endif

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