tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clock controller fixes from Michael Turquette:
"Two small fixes for the Zynq clock controller introduced in 3.11-rc1
and another Exynos clock patch which fixes a regression that prevents
the video pipeline from functioning on that platform"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
clk: exynos4: Add CLK_GET_RATE_NOCACHE flag for the Exynos4x12 ISP clocks
clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes
clk/zynq/clkc: Add dedicated spinlock for the SWDT

Linus Torvalds 0f7dd1aa 2d2843e6

+42 -35
+34 -30
drivers/clk/samsung/clk-exynos4.c
··· 581 581 DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 582 582 DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 583 583 DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 584 - DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), 585 - DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), 584 + DIV_F(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 585 + CLK_GET_RATE_NOCACHE, 0), 586 + DIV_F(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 587 + CLK_GET_RATE_NOCACHE, 0), 586 588 DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), 587 - DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), 588 - DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), 589 + DIV_F(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 590 + 4, 3, CLK_GET_RATE_NOCACHE, 0), 591 + DIV_F(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 592 + 8, 3, CLK_GET_RATE_NOCACHE, 0), 589 593 DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), 590 594 }; 591 595 ··· 867 863 GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", 868 864 E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), 869 865 GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, 870 - CLK_IGNORE_UNUSED, 0), 866 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 871 867 GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, 872 - CLK_IGNORE_UNUSED, 0), 868 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 873 869 GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, 874 - CLK_IGNORE_UNUSED, 0), 870 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 875 871 GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 876 - CLK_IGNORE_UNUSED, 0), 872 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 877 873 GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 878 - CLK_IGNORE_UNUSED, 0), 874 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 879 875 GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 880 - CLK_IGNORE_UNUSED, 0), 876 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 881 877 GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 882 - CLK_IGNORE_UNUSED, 0), 878 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 883 879 GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 884 - CLK_IGNORE_UNUSED, 0), 880 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 885 881 GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 886 - CLK_IGNORE_UNUSED, 0), 882 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 887 883 GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 888 - CLK_IGNORE_UNUSED, 0), 884 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 889 885 GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, 890 - CLK_IGNORE_UNUSED, 0), 886 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 891 887 GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, 892 - CLK_IGNORE_UNUSED, 0), 888 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 893 889 GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, 894 - CLK_IGNORE_UNUSED, 0), 890 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 895 891 GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, 896 - CLK_IGNORE_UNUSED, 0), 892 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 897 893 GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, 898 - CLK_IGNORE_UNUSED, 0), 894 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 899 895 GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, 900 - CLK_IGNORE_UNUSED, 0), 896 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 901 897 GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, 902 - CLK_IGNORE_UNUSED, 0), 898 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 903 899 GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, 904 - CLK_IGNORE_UNUSED, 0), 900 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 905 901 GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, 906 - CLK_IGNORE_UNUSED, 0), 902 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 907 903 GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 908 - CLK_IGNORE_UNUSED, 0), 904 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 909 905 GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 910 - CLK_IGNORE_UNUSED, 0), 906 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 911 907 GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, 912 - CLK_IGNORE_UNUSED, 0), 908 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 913 909 GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, 914 - CLK_IGNORE_UNUSED, 0), 910 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 915 911 GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, 916 - CLK_IGNORE_UNUSED, 0), 912 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 917 913 GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, 918 - CLK_IGNORE_UNUSED, 0), 914 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 919 915 GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 920 - CLK_IGNORE_UNUSED, 0), 916 + CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 921 917 GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), 922 918 }; 923 919
+8 -5
drivers/clk/zynq/clkc.c
··· 71 71 static DEFINE_SPINLOCK(ddrpll_lock); 72 72 static DEFINE_SPINLOCK(iopll_lock); 73 73 static DEFINE_SPINLOCK(armclk_lock); 74 + static DEFINE_SPINLOCK(swdtclk_lock); 74 75 static DEFINE_SPINLOCK(ddrclk_lock); 75 76 static DEFINE_SPINLOCK(dciclk_lock); 76 77 static DEFINE_SPINLOCK(gem0clk_lock); ··· 294 293 } 295 294 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 296 295 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, 297 - SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); 296 + SLCR_SWDT_CLK_SEL, 0, 1, 0, &swdtclk_lock); 298 297 299 298 /* DDR clocks */ 300 299 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, ··· 365 364 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 366 365 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 367 366 &gem0clk_lock); 368 - clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0, 369 - SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); 367 + clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 368 + CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0, 369 + &gem0clk_lock); 370 370 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 371 371 "gem0_emio_mux", CLK_SET_RATE_PARENT, 372 372 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); ··· 388 386 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 389 387 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 390 388 &gem1clk_lock); 391 - clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0, 392 - SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); 389 + clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 390 + CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0, 391 + &gem1clk_lock); 393 392 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 394 393 "gem1_emio_mux", CLK_SET_RATE_PARENT, 395 394 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);