Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.17-rc3' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Pretty run of the mill for this stage in the cycle: msm, i915, amdgpu,
qxl, virtio-gpu, sun4i fixes.
i915:
- Black screen fixes
- Display w/a fix
- HDA codec interop fix
sun4i:
- tbsa711 tablet regression fix
qxl:
- Regression fixes due to changes in TTM
virtio:
- Fix wait event condition
msm:
- DSI display fixes
amdgpu:
- fix hang on Carrizo
- DP MST hang fixes
- irq handling deadlock in DC.
amdkfd:
- Fix Kconfig issue
- Clock retrieval fix
- Sparse fixes"
* tag 'drm-fixes-for-v4.17-rc3' of git://people.freedesktop.org/~airlied/linux: (27 commits)
drm/edid: Reset more of the display info
drm/virtio: fix vq wait_event condition
qxl: keep separate release_bo pointer
qxl: fix qxl_release_{map,unmap}
Revert "drm/sun4i: add lvds mode_valid function"
drm/amd/display: Check dc_sink every time in MST hotplug
drm/amd/display: Update MST edid property every time
drm/amd/display: Don't read EDID in atomic_check
drm/amd/display: Disallow enabling CRTC without primary plane with FB
drm/amd/display: Fix deadlock when flushing irq
drm/i915/fbdev: Enable late fbdev initial configuration
drm/i915: Use ktime on wait_for
drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders
drm/amdkfd: fix build, select MMU_NOTIFIER
drm/amdkfd: fix clock counter retrieval for node without GPU
drm/amdkfd: Fix the error return code in kfd_ioctl_unmap_memory_from_gpu()
drm/amdkfd: kfd_dev_is_large_bar() can be static
drm/i915: Enable display WA#1183 from its correct spot
drm/i915/audio: set minimum CD clock to twice the BCLK
drm/msm: don't deref error pointer in the msm_fbdev_create error path
...
+237
-190
+5
-2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+5
-2
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
1459
1459
static const u32 vgpr_init_regs[] =
1460
1460
{
1461
1461
mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff,
1462
-
mmCOMPUTE_RESOURCE_LIMITS, 0,
1462
+
mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1463
1463
mmCOMPUTE_NUM_THREAD_X, 256*4,
1464
1464
mmCOMPUTE_NUM_THREAD_Y, 1,
1465
1465
mmCOMPUTE_NUM_THREAD_Z, 1,
1466
+
mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1466
1467
mmCOMPUTE_PGM_RSRC2, 20,
1467
1468
mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1468
1469
mmCOMPUTE_USER_DATA_1, 0xedcedc01,
···
1480
1479
static const u32 sgpr1_init_regs[] =
1481
1480
{
1482
1481
mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f,
1483
-
mmCOMPUTE_RESOURCE_LIMITS, 0x1000000,
1482
+
mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */
1484
1483
mmCOMPUTE_NUM_THREAD_X, 256*5,
1485
1484
mmCOMPUTE_NUM_THREAD_Y, 1,
1486
1485
mmCOMPUTE_NUM_THREAD_Z, 1,
1486
+
mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1487
1487
mmCOMPUTE_PGM_RSRC2, 20,
1488
1488
mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1489
1489
mmCOMPUTE_USER_DATA_1, 0xedcedc01,
···
1505
1503
mmCOMPUTE_NUM_THREAD_X, 256*5,
1506
1504
mmCOMPUTE_NUM_THREAD_Y, 1,
1507
1505
mmCOMPUTE_NUM_THREAD_Z, 1,
1506
+
mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1508
1507
mmCOMPUTE_PGM_RSRC2, 20,
1509
1508
mmCOMPUTE_USER_DATA_0, 0xedcedc00,
1510
1509
mmCOMPUTE_USER_DATA_1, 0xedcedc01,
+1
drivers/gpu/drm/amd/amdkfd/Kconfig
+1
drivers/gpu/drm/amd/amdkfd/Kconfig
+9
-8
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+9
-8
drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
···
749
749
struct timespec64 time;
750
750
751
751
dev = kfd_device_by_id(args->gpu_id);
752
-
if (dev == NULL)
753
-
return -EINVAL;
754
-
755
-
/* Reading GPU clock counter from KGD */
756
-
args->gpu_clock_counter =
757
-
dev->kfd2kgd->get_gpu_clock_counter(dev->kgd);
752
+
if (dev)
753
+
/* Reading GPU clock counter from KGD */
754
+
args->gpu_clock_counter =
755
+
dev->kfd2kgd->get_gpu_clock_counter(dev->kgd);
756
+
else
757
+
/* Node without GPU resource */
758
+
args->gpu_clock_counter = 0;
758
759
759
760
/* No access to rdtsc. Using raw monotonic time */
760
761
getrawmonotonic64(&time);
···
1148
1147
return ret;
1149
1148
}
1150
1149
1151
-
bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1150
+
static bool kfd_dev_is_large_bar(struct kfd_dev *dev)
1152
1151
{
1153
1152
struct kfd_local_mem_info mem_info;
1154
1153
···
1422
1421
1423
1422
pdd = kfd_get_process_device_data(dev, p);
1424
1423
if (!pdd) {
1425
-
err = PTR_ERR(pdd);
1424
+
err = -EINVAL;
1426
1425
goto bind_process_to_device_failed;
1427
1426
}
1428
1427
+9
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+9
-1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
4557
4557
struct amdgpu_dm_connector *aconnector = NULL;
4558
4558
struct drm_connector_state *new_con_state = NULL;
4559
4559
struct dm_connector_state *dm_conn_state = NULL;
4560
+
struct drm_plane_state *new_plane_state = NULL;
4560
4561
4561
4562
new_stream = NULL;
4562
4563
4563
4564
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
4564
4565
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
4565
4566
acrtc = to_amdgpu_crtc(crtc);
4567
+
4568
+
new_plane_state = drm_atomic_get_new_plane_state(state, new_crtc_state->crtc->primary);
4569
+
4570
+
if (new_crtc_state->enable && new_plane_state && !new_plane_state->fb) {
4571
+
ret = -EINVAL;
4572
+
goto fail;
4573
+
}
4566
4574
4567
4575
aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);
4568
4576
···
4768
4760
if (!dm_old_crtc_state->stream)
4769
4761
continue;
4770
4762
4771
-
DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n",
4763
+
DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",
4772
4764
plane->base.id, old_plane_crtc->base.id);
4773
4765
4774
4766
if (!dc_remove_plane_from_context(
+3
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
+3
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
···
329
329
{
330
330
int src;
331
331
struct irq_list_head *lh;
332
+
unsigned long irq_table_flags;
332
333
DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
333
-
334
334
for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
335
-
335
+
DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
336
336
/* The handler was removed from the table,
337
337
* it means it is safe to flush all the 'work'
338
338
* (because no code can schedule a new one). */
339
339
lh = &adev->dm.irq_handler_list_low_tab[src];
340
+
DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
340
341
flush_work(&lh->work);
341
342
}
342
343
}
+22
-32
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+22
-32
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
···
161
161
struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
162
162
struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder;
163
163
164
+
if (amdgpu_dm_connector->edid) {
165
+
kfree(amdgpu_dm_connector->edid);
166
+
amdgpu_dm_connector->edid = NULL;
167
+
}
168
+
164
169
drm_encoder_cleanup(&amdgpu_encoder->base);
165
170
kfree(amdgpu_encoder);
166
171
drm_connector_cleanup(connector);
···
186
181
void dm_dp_mst_dc_sink_create(struct drm_connector *connector)
187
182
{
188
183
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
189
-
struct edid *edid;
190
184
struct dc_sink *dc_sink;
191
185
struct dc_sink_init_data init_params = {
192
186
.link = aconnector->dc_link,
193
187
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
188
+
189
+
/* FIXME none of this is safe. we shouldn't touch aconnector here in
190
+
* atomic_check
191
+
*/
194
192
195
193
/*
196
194
* TODO: Need to further figure out why ddc.algo is NULL while MST port exists
···
201
193
if (!aconnector->port || !aconnector->port->aux.ddc.algo)
202
194
return;
203
195
204
-
edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
205
-
206
-
if (!edid) {
207
-
drm_mode_connector_update_edid_property(
208
-
&aconnector->base,
209
-
NULL);
210
-
return;
211
-
}
212
-
213
-
aconnector->edid = edid;
196
+
ASSERT(aconnector->edid);
214
197
215
198
dc_sink = dc_link_add_remote_sink(
216
199
aconnector->dc_link,
···
214
215
215
216
amdgpu_dm_add_sink_to_freesync_module(
216
217
connector, aconnector->edid);
217
-
218
-
drm_mode_connector_update_edid_property(
219
-
&aconnector->base, aconnector->edid);
220
218
}
221
219
222
220
static int dm_dp_mst_get_modes(struct drm_connector *connector)
···
226
230
227
231
if (!aconnector->edid) {
228
232
struct edid *edid;
229
-
struct dc_sink *dc_sink;
230
-
struct dc_sink_init_data init_params = {
231
-
.link = aconnector->dc_link,
232
-
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
233
233
edid = drm_dp_mst_get_edid(connector, &aconnector->mst_port->mst_mgr, aconnector->port);
234
234
235
235
if (!edid) {
···
236
244
}
237
245
238
246
aconnector->edid = edid;
247
+
}
239
248
249
+
if (!aconnector->dc_sink) {
250
+
struct dc_sink *dc_sink;
251
+
struct dc_sink_init_data init_params = {
252
+
.link = aconnector->dc_link,
253
+
.sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST };
240
254
dc_sink = dc_link_add_remote_sink(
241
255
aconnector->dc_link,
242
-
(uint8_t *)edid,
243
-
(edid->extensions + 1) * EDID_LENGTH,
256
+
(uint8_t *)aconnector->edid,
257
+
(aconnector->edid->extensions + 1) * EDID_LENGTH,
244
258
&init_params);
245
259
246
260
dc_sink->priv = aconnector;
···
254
256
255
257
if (aconnector->dc_sink)
256
258
amdgpu_dm_add_sink_to_freesync_module(
257
-
connector, edid);
258
-
259
-
drm_mode_connector_update_edid_property(
260
-
&aconnector->base, edid);
259
+
connector, aconnector->edid);
261
260
}
261
+
262
+
drm_mode_connector_update_edid_property(
263
+
&aconnector->base, aconnector->edid);
262
264
263
265
ret = drm_add_edid_modes(connector, aconnector->edid);
264
266
···
422
424
dc_sink_release(aconnector->dc_sink);
423
425
aconnector->dc_sink = NULL;
424
426
}
425
-
if (aconnector->edid) {
426
-
kfree(aconnector->edid);
427
-
aconnector->edid = NULL;
428
-
}
429
-
430
-
drm_mode_connector_update_edid_property(
431
-
&aconnector->base,
432
-
NULL);
433
427
434
428
aconnector->mst_connected = false;
435
429
}
+3
-8
drivers/gpu/drm/drm_edid.c
+3
-8
drivers/gpu/drm/drm_edid.c
···
4451
4451
info->max_tmds_clock = 0;
4452
4452
info->dvi_dual = false;
4453
4453
info->has_hdmi_infoframe = false;
4454
+
memset(&info->hdmi, 0, sizeof(info->hdmi));
4454
4455
4455
4456
info->non_desktop = 0;
4456
4457
}
···
4463
4462
4464
4463
u32 quirks = edid_get_quirks(edid);
4465
4464
4465
+
drm_reset_display_info(connector);
4466
+
4466
4467
info->width_mm = edid->width_cm * 10;
4467
4468
info->height_mm = edid->height_cm * 10;
4468
-
4469
-
/* driver figures it out in this case */
4470
-
info->bpc = 0;
4471
-
info->color_formats = 0;
4472
-
info->cea_rev = 0;
4473
-
info->max_tmds_clock = 0;
4474
-
info->dvi_dual = false;
4475
-
info->has_hdmi_infoframe = false;
4476
4469
4477
4470
info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4478
4471
+14
-2
drivers/gpu/drm/i915/intel_cdclk.c
+14
-2
drivers/gpu/drm/i915/intel_cdclk.c
···
2140
2140
}
2141
2141
}
2142
2142
2143
-
/* According to BSpec, "The CD clock frequency must be at least twice
2143
+
/*
2144
+
* According to BSpec, "The CD clock frequency must be at least twice
2144
2145
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2146
+
*
2147
+
* FIXME: Check the actual, not default, BCLK being used.
2148
+
*
2149
+
* FIXME: This does not depend on ->has_audio because the higher CDCLK
2150
+
* is required for audio probe, also when there are no audio capable
2151
+
* displays connected at probe time. This leads to unnecessarily high
2152
+
* CDCLK when audio is not required.
2153
+
*
2154
+
* FIXME: This limit is only applied when there are displays connected
2155
+
* at probe time. If we probe without displays, we'll still end up using
2156
+
* the platform minimum CDCLK, failing audio probe.
2145
2157
*/
2146
-
if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
2158
+
if (INTEL_GEN(dev_priv) >= 9)
2147
2159
min_cdclk = max(2 * 96000, min_cdclk);
2148
2160
2149
2161
/*
+2
-2
drivers/gpu/drm/i915/intel_drv.h
+2
-2
drivers/gpu/drm/i915/intel_drv.h
···
49
49
* check the condition before the timeout.
50
50
*/
51
51
#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
52
-
unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
52
+
const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
53
53
long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
54
54
int ret__; \
55
55
might_sleep(); \
56
56
for (;;) { \
57
-
bool expired__ = time_after(jiffies, timeout__); \
57
+
const bool expired__ = ktime_after(ktime_get_raw(), end__); \
58
58
OP; \
59
59
if (COND) { \
60
60
ret__ = 0; \
+1
-1
drivers/gpu/drm/i915/intel_fbdev.c
+1
-1
drivers/gpu/drm/i915/intel_fbdev.c
+5
-6
drivers/gpu/drm/i915/intel_runtime_pm.c
+5
-6
drivers/gpu/drm/i915/intel_runtime_pm.c
···
641
641
642
642
DRM_DEBUG_KMS("Enabling DC6\n");
643
643
644
-
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
644
+
/* Wa Display #1183: skl,kbl,cfl */
645
+
if (IS_GEN9_BC(dev_priv))
646
+
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
647
+
SKL_SELECT_ALTERNATE_DC_EXIT);
645
648
649
+
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
646
650
}
647
651
648
652
void skl_disable_dc6(struct drm_i915_private *dev_priv)
649
653
{
650
654
DRM_DEBUG_KMS("Disabling DC6\n");
651
-
652
-
/* Wa Display #1183: skl,kbl,cfl */
653
-
if (IS_GEN9_BC(dev_priv))
654
-
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
655
-
SKL_SELECT_ALTERNATE_DC_EXIT);
656
655
657
656
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
658
657
}
+1
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+1
drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+1
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+1
drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+2
-1
drivers/gpu/drm/msm/disp/mdp_format.c
+2
-1
drivers/gpu/drm/msm/disp/mdp_format.c
···
171
171
return i;
172
172
}
173
173
174
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format)
174
+
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
175
+
uint64_t modifier)
175
176
{
176
177
int i;
177
178
for (i = 0; i < ARRAY_SIZE(formats); i++) {
+1
-1
drivers/gpu/drm/msm/disp/mdp_kms.h
+1
-1
drivers/gpu/drm/msm/disp/mdp_kms.h
···
98
98
#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
99
99
100
100
uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
101
-
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format);
101
+
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
102
102
103
103
/* MDP capabilities */
104
104
#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
+12
-4
drivers/gpu/drm/msm/dsi/dsi_host.c
+12
-4
drivers/gpu/drm/msm/dsi/dsi_host.c
···
173
173
174
174
bool registered;
175
175
bool power_on;
176
+
bool enabled;
176
177
int irq;
177
178
};
178
179
···
776
775
switch (mipi_fmt) {
777
776
case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
778
777
case MIPI_DSI_FMT_RGB666_PACKED:
779
-
case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666;
778
+
case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
780
779
case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
781
780
default: return CMD_DST_FORMAT_RGB888;
782
781
}
···
987
986
988
987
static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
989
988
{
989
+
u32 ret = 0;
990
+
struct device *dev = &msm_host->pdev->dev;
991
+
990
992
dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
991
993
992
994
reinit_completion(&msm_host->video_comp);
993
995
994
-
wait_for_completion_timeout(&msm_host->video_comp,
996
+
ret = wait_for_completion_timeout(&msm_host->video_comp,
995
997
msecs_to_jiffies(70));
998
+
999
+
if (ret <= 0)
1000
+
dev_err(dev, "wait for video done timed out\n");
996
1001
997
1002
dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
998
1003
}
···
1008
1001
if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1009
1002
return;
1010
1003
1011
-
if (msm_host->power_on) {
1004
+
if (msm_host->power_on && msm_host->enabled) {
1012
1005
dsi_wait4video_done(msm_host);
1013
1006
/* delay 4 ms to skip BLLP */
1014
1007
usleep_range(2000, 4000);
···
2210
2203
* pm_runtime_put_autosuspend(&msm_host->pdev->dev);
2211
2204
* }
2212
2205
*/
2213
-
2206
+
msm_host->enabled = true;
2214
2207
return 0;
2215
2208
}
2216
2209
···
2218
2211
{
2219
2212
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2220
2213
2214
+
msm_host->enabled = false;
2221
2215
dsi_op_mode_config(msm_host,
2222
2216
!!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2223
2217
+109
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+109
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
···
265
265
return 0;
266
266
}
267
267
268
+
int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
269
+
struct msm_dsi_phy_clk_request *clk_req)
270
+
{
271
+
const unsigned long bit_rate = clk_req->bitclk_rate;
272
+
const unsigned long esc_rate = clk_req->escclk_rate;
273
+
s32 ui, ui_x8, lpx;
274
+
s32 tmax, tmin;
275
+
s32 pcnt0 = 50;
276
+
s32 pcnt1 = 50;
277
+
s32 pcnt2 = 10;
278
+
s32 pcnt3 = 30;
279
+
s32 pcnt4 = 10;
280
+
s32 pcnt5 = 2;
281
+
s32 coeff = 1000; /* Precision, should avoid overflow */
282
+
s32 hb_en, hb_en_ckln;
283
+
s32 temp;
284
+
285
+
if (!bit_rate || !esc_rate)
286
+
return -EINVAL;
287
+
288
+
timing->hs_halfbyte_en = 0;
289
+
hb_en = 0;
290
+
timing->hs_halfbyte_en_ckln = 0;
291
+
hb_en_ckln = 0;
292
+
293
+
ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
294
+
ui_x8 = ui << 3;
295
+
lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
296
+
297
+
temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
298
+
tmin = max_t(s32, temp, 0);
299
+
temp = (95 * coeff) / ui_x8;
300
+
tmax = max_t(s32, temp, 0);
301
+
timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
302
+
303
+
temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
304
+
tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
305
+
tmax = (tmin > 255) ? 511 : 255;
306
+
timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
307
+
308
+
tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
309
+
temp = 105 * coeff + 12 * ui - 20 * coeff;
310
+
tmax = (temp + 3 * ui) / ui_x8;
311
+
timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
312
+
313
+
temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
314
+
tmin = max_t(s32, temp, 0);
315
+
temp = (85 * coeff + 6 * ui) / ui_x8;
316
+
tmax = max_t(s32, temp, 0);
317
+
timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
318
+
319
+
temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
320
+
tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
321
+
tmax = 255;
322
+
timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
323
+
324
+
tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
325
+
temp = 105 * coeff + 12 * ui - 20 * coeff;
326
+
tmax = (temp / ui_x8) - 1;
327
+
timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
328
+
329
+
temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
330
+
timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
331
+
332
+
tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
333
+
tmax = 255;
334
+
timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
335
+
336
+
temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
337
+
timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
338
+
339
+
temp = 60 * coeff + 52 * ui - 43 * ui;
340
+
tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
341
+
tmax = 63;
342
+
timing->shared_timings.clk_post =
343
+
linear_inter(tmax, tmin, pcnt2, 0, false);
344
+
345
+
temp = 8 * ui + (timing->clk_prepare << 3) * ui;
346
+
temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
347
+
temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
348
+
(((timing->hs_rqst_ckln << 3) + 8) * ui);
349
+
tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
350
+
tmax = 63;
351
+
if (tmin > tmax) {
352
+
temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
353
+
timing->shared_timings.clk_pre = temp >> 1;
354
+
timing->shared_timings.clk_pre_inc_by_2 = 1;
355
+
} else {
356
+
timing->shared_timings.clk_pre =
357
+
linear_inter(tmax, tmin, pcnt2, 0, false);
358
+
timing->shared_timings.clk_pre_inc_by_2 = 0;
359
+
}
360
+
361
+
timing->ta_go = 3;
362
+
timing->ta_sure = 0;
363
+
timing->ta_get = 4;
364
+
365
+
DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
366
+
timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
367
+
timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
368
+
timing->clk_trail, timing->clk_prepare, timing->hs_exit,
369
+
timing->hs_zero, timing->hs_prepare, timing->hs_trail,
370
+
timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
371
+
timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
372
+
timing->hs_prep_dly_ckln);
373
+
374
+
return 0;
375
+
}
376
+
268
377
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
269
378
u32 bit_mask)
270
379
{
+2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+2
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
···
101
101
struct msm_dsi_phy_clk_request *clk_req);
102
102
int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
103
103
struct msm_dsi_phy_clk_request *clk_req);
104
+
int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
105
+
struct msm_dsi_phy_clk_request *clk_req);
104
106
void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
105
107
u32 bit_mask);
106
108
int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);
-28
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
-28
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
···
79
79
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);
80
80
}
81
81
82
-
static int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
83
-
struct msm_dsi_phy_clk_request *clk_req)
84
-
{
85
-
/*
86
-
* TODO: These params need to be computed, they're currently hardcoded
87
-
* for a 1440x2560@60Hz panel with a byteclk of 100.618 Mhz, and a
88
-
* default escape clock of 19.2 Mhz.
89
-
*/
90
-
91
-
timing->hs_halfbyte_en = 0;
92
-
timing->clk_zero = 0x1c;
93
-
timing->clk_prepare = 0x07;
94
-
timing->clk_trail = 0x07;
95
-
timing->hs_exit = 0x23;
96
-
timing->hs_zero = 0x21;
97
-
timing->hs_prepare = 0x07;
98
-
timing->hs_trail = 0x07;
99
-
timing->hs_rqst = 0x05;
100
-
timing->ta_sure = 0x00;
101
-
timing->ta_go = 0x03;
102
-
timing->ta_get = 0x04;
103
-
104
-
timing->shared_timings.clk_pre = 0x2d;
105
-
timing->shared_timings.clk_post = 0x0d;
106
-
107
-
return 0;
108
-
}
109
-
110
82
static int dsi_10nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
111
83
struct msm_dsi_phy_clk_request *clk_req)
112
84
{
+2
-1
drivers/gpu/drm/msm/msm_fb.c
+2
-1
drivers/gpu/drm/msm/msm_fb.c
···
183
183
hsub = drm_format_horz_chroma_subsampling(mode_cmd->pixel_format);
184
184
vsub = drm_format_vert_chroma_subsampling(mode_cmd->pixel_format);
185
185
186
-
format = kms->funcs->get_format(kms, mode_cmd->pixel_format);
186
+
format = kms->funcs->get_format(kms, mode_cmd->pixel_format,
187
+
mode_cmd->modifier[0]);
187
188
if (!format) {
188
189
dev_err(dev->dev, "unsupported pixel format: %4.4s\n",
189
190
(char *)&mode_cmd->pixel_format);
+2
-9
drivers/gpu/drm/msm/msm_fbdev.c
+2
-9
drivers/gpu/drm/msm/msm_fbdev.c
···
92
92
93
93
if (IS_ERR(fb)) {
94
94
dev_err(dev->dev, "failed to allocate fb\n");
95
-
ret = PTR_ERR(fb);
96
-
goto fail;
95
+
return PTR_ERR(fb);
97
96
}
98
97
99
98
bo = msm_framebuffer_bo(fb, 0);
···
150
151
151
152
fail_unlock:
152
153
mutex_unlock(&dev->struct_mutex);
153
-
fail:
154
-
155
-
if (ret) {
156
-
if (fb)
157
-
drm_framebuffer_remove(fb);
158
-
}
159
-
154
+
drm_framebuffer_remove(fb);
160
155
return ret;
161
156
}
162
157
+11
-9
drivers/gpu/drm/msm/msm_gem.c
+11
-9
drivers/gpu/drm/msm/msm_gem.c
···
132
132
struct msm_gem_object *msm_obj = to_msm_bo(obj);
133
133
134
134
if (msm_obj->pages) {
135
-
/* For non-cached buffers, ensure the new pages are clean
136
-
* because display controller, GPU, etc. are not coherent:
137
-
*/
138
-
if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
139
-
dma_unmap_sg(obj->dev->dev, msm_obj->sgt->sgl,
140
-
msm_obj->sgt->nents, DMA_BIDIRECTIONAL);
135
+
if (msm_obj->sgt) {
136
+
/* For non-cached buffers, ensure the new
137
+
* pages are clean because display controller,
138
+
* GPU, etc. are not coherent:
139
+
*/
140
+
if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED))
141
+
dma_unmap_sg(obj->dev->dev, msm_obj->sgt->sgl,
142
+
msm_obj->sgt->nents,
143
+
DMA_BIDIRECTIONAL);
141
144
142
-
if (msm_obj->sgt)
143
145
sg_free_table(msm_obj->sgt);
144
-
145
-
kfree(msm_obj->sgt);
146
+
kfree(msm_obj->sgt);
147
+
}
146
148
147
149
if (use_pages(obj))
148
150
drm_gem_put_pages(obj, msm_obj->pages, true, false);
+4
-1
drivers/gpu/drm/msm/msm_kms.h
+4
-1
drivers/gpu/drm/msm/msm_kms.h
···
48
48
/* functions to wait for atomic commit completed on each CRTC */
49
49
void (*wait_for_crtc_commit_done)(struct msm_kms *kms,
50
50
struct drm_crtc *crtc);
51
+
/* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
52
+
const struct msm_format *(*get_format)(struct msm_kms *kms,
53
+
const uint32_t format,
54
+
const uint64_t modifiers);
51
55
/* misc: */
52
-
const struct msm_format *(*get_format)(struct msm_kms *kms, uint32_t format);
53
56
long (*round_pixclk)(struct msm_kms *kms, unsigned long rate,
54
57
struct drm_encoder *encoder);
55
58
int (*set_split_display)(struct msm_kms *kms,
+2
-4
drivers/gpu/drm/qxl/qxl_cmd.c
+2
-4
drivers/gpu/drm/qxl/qxl_cmd.c
···
179
179
uint32_t type, bool interruptible)
180
180
{
181
181
struct qxl_command cmd;
182
-
struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head);
183
182
184
183
cmd.type = type;
185
-
cmd.data = qxl_bo_physical_address(qdev, to_qxl_bo(entry->tv.bo), release->release_offset);
184
+
cmd.data = qxl_bo_physical_address(qdev, release->release_bo, release->release_offset);
186
185
187
186
return qxl_ring_push(qdev->command_ring, &cmd, interruptible);
188
187
}
···
191
192
uint32_t type, bool interruptible)
192
193
{
193
194
struct qxl_command cmd;
194
-
struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head);
195
195
196
196
cmd.type = type;
197
-
cmd.data = qxl_bo_physical_address(qdev, to_qxl_bo(entry->tv.bo), release->release_offset);
197
+
cmd.data = qxl_bo_physical_address(qdev, release->release_bo, release->release_offset);
198
198
199
199
return qxl_ring_push(qdev->cursor_ring, &cmd, interruptible);
200
200
}
+1
drivers/gpu/drm/qxl/qxl_drv.h
+1
drivers/gpu/drm/qxl/qxl_drv.h
+2
-2
drivers/gpu/drm/qxl/qxl_ioctl.c
+2
-2
drivers/gpu/drm/qxl/qxl_ioctl.c
···
182
182
goto out_free_reloc;
183
183
184
184
/* TODO copy slow path code from i915 */
185
-
fb_cmd = qxl_bo_kmap_atomic_page(qdev, cmd_bo, (release->release_offset & PAGE_SIZE));
185
+
fb_cmd = qxl_bo_kmap_atomic_page(qdev, cmd_bo, (release->release_offset & PAGE_MASK));
186
186
unwritten = __copy_from_user_inatomic_nocache
187
-
(fb_cmd + sizeof(union qxl_release_info) + (release->release_offset & ~PAGE_SIZE),
187
+
(fb_cmd + sizeof(union qxl_release_info) + (release->release_offset & ~PAGE_MASK),
188
188
u64_to_user_ptr(cmd->command), cmd->command_size);
189
189
190
190
{
+9
-9
drivers/gpu/drm/qxl/qxl_release.c
+9
-9
drivers/gpu/drm/qxl/qxl_release.c
···
173
173
list_del(&entry->tv.head);
174
174
kfree(entry);
175
175
}
176
+
release->release_bo = NULL;
176
177
}
177
178
178
179
void
···
297
296
{
298
297
if (surface_cmd_type == QXL_SURFACE_CMD_DESTROY && create_rel) {
299
298
int idr_ret;
300
-
struct qxl_bo_list *entry = list_first_entry(&create_rel->bos, struct qxl_bo_list, tv.head);
301
299
struct qxl_bo *bo;
302
300
union qxl_release_info *info;
303
301
···
304
304
idr_ret = qxl_release_alloc(qdev, QXL_RELEASE_SURFACE_CMD, release);
305
305
if (idr_ret < 0)
306
306
return idr_ret;
307
-
bo = to_qxl_bo(entry->tv.bo);
307
+
bo = create_rel->release_bo;
308
308
309
+
(*release)->release_bo = bo;
309
310
(*release)->release_offset = create_rel->release_offset + 64;
310
311
311
312
qxl_release_list_add(*release, bo);
···
366
365
367
366
bo = qxl_bo_ref(qdev->current_release_bo[cur_idx]);
368
367
368
+
(*release)->release_bo = bo;
369
369
(*release)->release_offset = qdev->current_release_bo_offset[cur_idx] * release_size_per_bo[cur_idx];
370
370
qdev->current_release_bo_offset[cur_idx]++;
371
371
···
410
408
{
411
409
void *ptr;
412
410
union qxl_release_info *info;
413
-
struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head);
414
-
struct qxl_bo *bo = to_qxl_bo(entry->tv.bo);
411
+
struct qxl_bo *bo = release->release_bo;
415
412
416
-
ptr = qxl_bo_kmap_atomic_page(qdev, bo, release->release_offset & PAGE_SIZE);
413
+
ptr = qxl_bo_kmap_atomic_page(qdev, bo, release->release_offset & PAGE_MASK);
417
414
if (!ptr)
418
415
return NULL;
419
-
info = ptr + (release->release_offset & ~PAGE_SIZE);
416
+
info = ptr + (release->release_offset & ~PAGE_MASK);
420
417
return info;
421
418
}
422
419
···
423
422
struct qxl_release *release,
424
423
union qxl_release_info *info)
425
424
{
426
-
struct qxl_bo_list *entry = list_first_entry(&release->bos, struct qxl_bo_list, tv.head);
427
-
struct qxl_bo *bo = to_qxl_bo(entry->tv.bo);
425
+
struct qxl_bo *bo = release->release_bo;
428
426
void *ptr;
429
427
430
-
ptr = ((void *)info) - (release->release_offset & ~PAGE_SIZE);
428
+
ptr = ((void *)info) - (release->release_offset & ~PAGE_MASK);
431
429
qxl_bo_kunmap_atomic_page(qdev, bo, ptr);
432
430
}
433
431
-55
drivers/gpu/drm/sun4i/sun4i_lvds.c
-55
drivers/gpu/drm/sun4i/sun4i_lvds.c
···
94
94
}
95
95
}
96
96
97
-
static enum drm_mode_status sun4i_lvds_encoder_mode_valid(struct drm_encoder *crtc,
98
-
const struct drm_display_mode *mode)
99
-
{
100
-
struct sun4i_lvds *lvds = drm_encoder_to_sun4i_lvds(crtc);
101
-
struct sun4i_tcon *tcon = lvds->tcon;
102
-
u32 hsync = mode->hsync_end - mode->hsync_start;
103
-
u32 vsync = mode->vsync_end - mode->vsync_start;
104
-
unsigned long rate = mode->clock * 1000;
105
-
long rounded_rate;
106
-
107
-
DRM_DEBUG_DRIVER("Validating modes...\n");
108
-
109
-
if (hsync < 1)
110
-
return MODE_HSYNC_NARROW;
111
-
112
-
if (hsync > 0x3ff)
113
-
return MODE_HSYNC_WIDE;
114
-
115
-
if ((mode->hdisplay < 1) || (mode->htotal < 1))
116
-
return MODE_H_ILLEGAL;
117
-
118
-
if ((mode->hdisplay > 0x7ff) || (mode->htotal > 0xfff))
119
-
return MODE_BAD_HVALUE;
120
-
121
-
DRM_DEBUG_DRIVER("Horizontal parameters OK\n");
122
-
123
-
if (vsync < 1)
124
-
return MODE_VSYNC_NARROW;
125
-
126
-
if (vsync > 0x3ff)
127
-
return MODE_VSYNC_WIDE;
128
-
129
-
if ((mode->vdisplay < 1) || (mode->vtotal < 1))
130
-
return MODE_V_ILLEGAL;
131
-
132
-
if ((mode->vdisplay > 0x7ff) || (mode->vtotal > 0xfff))
133
-
return MODE_BAD_VVALUE;
134
-
135
-
DRM_DEBUG_DRIVER("Vertical parameters OK\n");
136
-
137
-
tcon->dclk_min_div = 7;
138
-
tcon->dclk_max_div = 7;
139
-
rounded_rate = clk_round_rate(tcon->dclk, rate);
140
-
if (rounded_rate < rate)
141
-
return MODE_CLOCK_LOW;
142
-
143
-
if (rounded_rate > rate)
144
-
return MODE_CLOCK_HIGH;
145
-
146
-
DRM_DEBUG_DRIVER("Clock rate OK\n");
147
-
148
-
return MODE_OK;
149
-
}
150
-
151
97
static const struct drm_encoder_helper_funcs sun4i_lvds_enc_helper_funcs = {
152
98
.disable = sun4i_lvds_encoder_disable,
153
99
.enable = sun4i_lvds_encoder_enable,
154
-
.mode_valid = sun4i_lvds_encoder_mode_valid,
155
100
};
156
101
157
102
static const struct drm_encoder_funcs sun4i_lvds_enc_funcs = {
+2
-2
drivers/gpu/drm/virtio/virtgpu_vq.c
+2
-2
drivers/gpu/drm/virtio/virtgpu_vq.c
···
293
293
ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC);
294
294
if (ret == -ENOSPC) {
295
295
spin_unlock(&vgdev->ctrlq.qlock);
296
-
wait_event(vgdev->ctrlq.ack_queue, vq->num_free);
296
+
wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= outcnt + incnt);
297
297
spin_lock(&vgdev->ctrlq.qlock);
298
298
goto retry;
299
299
} else {
···
368
368
ret = virtqueue_add_sgs(vq, sgs, outcnt, 0, vbuf, GFP_ATOMIC);
369
369
if (ret == -ENOSPC) {
370
370
spin_unlock(&vgdev->cursorq.qlock);
371
-
wait_event(vgdev->cursorq.ack_queue, vq->num_free);
371
+
wait_event(vgdev->cursorq.ack_queue, vq->num_free >= outcnt);
372
372
spin_lock(&vgdev->cursorq.qlock);
373
373
goto retry;
374
374
} else {