Merge tag 'drm-fixes-2018-09-14' of git://anongit.freedesktop.org/drm/drm

+17 -10

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

··· 39 39 { 40 40 struct drm_gem_object *gobj; 41 41 unsigned long size; 42 + int r; 42 43 43 44 gobj = drm_gem_object_lookup(p->filp, data->handle); 44 45 if (gobj == NULL) ··· 51 50 p->uf_entry.tv.shared = true; 52 51 p->uf_entry.user_pages = NULL; 53 52 53 + drm_gem_object_put_unlocked(gobj); 54 + 54 55 size = amdgpu_bo_size(p->uf_entry.robj); 55 - if (size != PAGE_SIZE || (data->offset + 8) > size) 56 - return -EINVAL; 56 + if (size != PAGE_SIZE || (data->offset + 8) > size) { 57 + r = -EINVAL; 58 + goto error_unref; 59 + } 60 + 61 + if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { 62 + r = -EINVAL; 63 + goto error_unref; 64 + } 57 65 58 66 *offset = data->offset; 59 67 60 - drm_gem_object_put_unlocked(gobj); 61 - 62 - if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) { 63 - amdgpu_bo_unref(&p->uf_entry.robj); 64 - return -EINVAL; 65 - } 66 - 67 68 return 0; 69 + 70 + error_unref: 71 + amdgpu_bo_unref(&p->uf_entry.robj); 72 + return r; 68 73 } 69 74 70 75 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p, ··· 1269 1262 error_abort: 1270 1263 dma_fence_put(&job->base.s_fence->finished); 1271 1264 job->base.s_fence = NULL; 1265 + amdgpu_mn_unlock(p->mn); 1272 1266 1273 1267 error_unlock: 1274 1268 amdgpu_job_free(job); 1275 - amdgpu_mn_unlock(p->mn); 1276 1269 return r; 1277 1270 } 1278 1271

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

··· 2063 2063 static enum amd_ip_block_type ip_order[] = { 2064 2064 AMD_IP_BLOCK_TYPE_GMC, 2065 2065 AMD_IP_BLOCK_TYPE_COMMON, 2066 + AMD_IP_BLOCK_TYPE_PSP, 2066 2067 AMD_IP_BLOCK_TYPE_IH, 2067 2068 }; 2068 2069 ··· 2094 2093 2095 2094 static enum amd_ip_block_type ip_order[] = { 2096 2095 AMD_IP_BLOCK_TYPE_SMC, 2097 - AMD_IP_BLOCK_TYPE_PSP, 2098 2096 AMD_IP_BLOCK_TYPE_DCE, 2099 2097 AMD_IP_BLOCK_TYPE_GFX, 2100 2098 AMD_IP_BLOCK_TYPE_SDMA,

+5 -2

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

··· 70 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 71 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 72 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 73 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 73 74 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07), 74 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 75 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), ··· 82 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 83 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 84 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 85 - SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 84 + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 85 + SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 86 86 }; 87 87 88 88 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { ··· 111 109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 112 110 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 113 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 114 - SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0) 112 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 113 + SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 115 114 }; 116 115 117 116 static const struct soc15_reg_golden golden_settings_sdma_4_2[] =

+8 -2

drivers/gpu/drm/i915/gvt/kvmgt.c

··· 32 32 #include <linux/device.h> 33 33 #include <linux/mm.h> 34 34 #include <linux/mmu_context.h> 35 + #include <linux/sched/mm.h> 35 36 #include <linux/types.h> 36 37 #include <linux/list.h> 37 38 #include <linux/rbtree.h> ··· 1793 1792 info = (struct kvmgt_guest_info *)handle; 1794 1793 kvm = info->kvm; 1795 1794 1796 - if (kthread) 1795 + if (kthread) { 1796 + if (!mmget_not_zero(kvm->mm)) 1797 + return -EFAULT; 1797 1798 use_mm(kvm->mm); 1799 + } 1798 1800 1799 1801 idx = srcu_read_lock(&kvm->srcu); 1800 1802 ret = write ? kvm_write_guest(kvm, gpa, buf, len) : 1801 1803 kvm_read_guest(kvm, gpa, buf, len); 1802 1804 srcu_read_unlock(&kvm->srcu, idx); 1803 1805 1804 - if (kthread) 1806 + if (kthread) { 1805 1807 unuse_mm(kvm->mm); 1808 + mmput(kvm->mm); 1809 + } 1806 1810 1807 1811 return ret; 1808 1812 }

+9 -11

drivers/gpu/drm/i915/gvt/opregion.c

··· 42 42 #define DEVICE_TYPE_EFP3 0x20 43 43 #define DEVICE_TYPE_EFP4 0x10 44 44 45 - #define DEV_SIZE 38 46 - 47 45 struct opregion_header { 48 46 u8 signature[16]; 49 47 u32 size; ··· 61 63 u16 size; /* data size */ 62 64 } __packed; 63 65 66 + /* For supporting windows guest with opregion, here hardcode the emulated 67 + * bdb header version as '186', and the corresponding child_device_config 68 + * length should be '33' but not '38'. 69 + */ 64 70 struct efp_child_device_config { 65 71 u16 handle; 66 72 u16 device_type; ··· 111 109 u8 mipi_bridge_type; /* 171 */ 112 110 u16 device_class_ext; 113 111 u8 dvo_function; 114 - u8 dp_usb_type_c:1; /* 195 */ 115 - u8 skip6:7; 116 - u8 dp_usb_type_c_2x_gpio_index; /* 195 */ 117 - u16 dp_usb_type_c_2x_gpio_pin; /* 195 */ 118 - u8 iboost_dp:4; /* 196 */ 119 - u8 iboost_hdmi:4; /* 196 */ 120 112 } __packed; 121 113 122 114 struct vbt { ··· 151 155 v->header.bdb_offset = offsetof(struct vbt, bdb_header); 152 156 153 157 strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK"); 154 - v->bdb_header.version = 186; /* child_dev_size = 38 */ 158 + v->bdb_header.version = 186; /* child_dev_size = 33 */ 155 159 v->bdb_header.header_size = sizeof(v->bdb_header); 156 160 157 161 v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header) ··· 165 169 166 170 /* child device */ 167 171 num_child = 4; /* each port has one child */ 172 + v->general_definitions.child_dev_size = 173 + sizeof(struct efp_child_device_config); 168 174 v->general_definitions_header.id = BDB_GENERAL_DEFINITIONS; 169 175 /* size will include child devices */ 170 176 v->general_definitions_header.size = 171 - sizeof(struct bdb_general_definitions) + num_child * DEV_SIZE; 172 - v->general_definitions.child_dev_size = DEV_SIZE; 177 + sizeof(struct bdb_general_definitions) + 178 + num_child * v->general_definitions.child_dev_size; 173 179 174 180 /* portA */ 175 181 v->child0.handle = DEVICE_TYPE_EFP1;

+6 -2

drivers/gpu/drm/i915/intel_display.c

··· 5079 5079 mutex_lock(&dev_priv->pcu_lock); 5080 5080 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); 5081 5081 mutex_unlock(&dev_priv->pcu_lock); 5082 - /* wait for pcode to finish disabling IPS, which may take up to 42ms */ 5082 + /* 5083 + * Wait for PCODE to finish disabling IPS. The BSpec specified 5084 + * 42ms timeout value leads to occasional timeouts so use 100ms 5085 + * instead. 5086 + */ 5083 5087 if (intel_wait_for_register(dev_priv, 5084 5088 IPS_CTL, IPS_ENABLE, 0, 5085 - 42)) 5089 + 100)) 5086 5090 DRM_ERROR("Timed out waiting for IPS disable\n"); 5087 5091 } else { 5088 5092 I915_WRITE(IPS_CTL, 0);

+75 -153

drivers/gpu/drm/i915/intel_overlay.c

··· 181 181 u32 brightness, contrast, saturation; 182 182 u32 old_xscale, old_yscale; 183 183 /* register access */ 184 - u32 flip_addr; 185 184 struct drm_i915_gem_object *reg_bo; 185 + struct overlay_registers __iomem *regs; 186 + u32 flip_addr; 186 187 /* flip handling */ 187 188 struct i915_gem_active last_flip; 188 189 }; ··· 209 208 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 210 209 pci_bus_write_config_byte(pdev->bus, 211 210 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 212 - } 213 - 214 - static struct overlay_registers __iomem * 215 - intel_overlay_map_regs(struct intel_overlay *overlay) 216 - { 217 - struct drm_i915_private *dev_priv = overlay->i915; 218 - struct overlay_registers __iomem *regs; 219 - 220 - if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 221 - regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; 222 - else 223 - regs = io_mapping_map_wc(&dev_priv->ggtt.iomap, 224 - overlay->flip_addr, 225 - PAGE_SIZE); 226 - 227 - return regs; 228 - } 229 - 230 - static void intel_overlay_unmap_regs(struct intel_overlay *overlay, 231 - struct overlay_registers __iomem *regs) 232 - { 233 - if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 234 - io_mapping_unmap(regs); 235 211 } 236 212 237 213 static void intel_overlay_submit_request(struct intel_overlay *overlay, ··· 762 784 struct drm_i915_gem_object *new_bo, 763 785 struct put_image_params *params) 764 786 { 765 - int ret, tmp_width; 766 - struct overlay_registers __iomem *regs; 767 - bool scale_changed = false; 787 + struct overlay_registers __iomem *regs = overlay->regs; 768 788 struct drm_i915_private *dev_priv = overlay->i915; 769 789 u32 swidth, swidthsw, sheight, ostride; 770 790 enum pipe pipe = overlay->crtc->pipe; 791 + bool scale_changed = false; 771 792 struct i915_vma *vma; 793 + int ret, tmp_width; 772 794 773 795 lockdep_assert_held(&dev_priv->drm.struct_mutex); 774 796 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); ··· 793 815 794 816 if (!overlay->active) { 795 817 u32 oconfig; 796 - regs = intel_overlay_map_regs(overlay); 797 - if (!regs) { 798 - ret = -ENOMEM; 799 - goto out_unpin; 800 - } 818 + 801 819 oconfig = OCONF_CC_OUT_8BIT; 802 820 if (IS_GEN4(dev_priv)) 803 821 oconfig |= OCONF_CSC_MODE_BT709; 804 822 oconfig |= pipe == 0 ? 805 823 OCONF_PIPE_A : OCONF_PIPE_B; 806 824 iowrite32(oconfig, &regs->OCONFIG); 807 - intel_overlay_unmap_regs(overlay, regs); 808 825 809 826 ret = intel_overlay_on(overlay); 810 827 if (ret != 0) 811 828 goto out_unpin; 812 - } 813 - 814 - regs = intel_overlay_map_regs(overlay); 815 - if (!regs) { 816 - ret = -ENOMEM; 817 - goto out_unpin; 818 829 } 819 830 820 831 iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS); ··· 849 882 850 883 iowrite32(overlay_cmd_reg(params), &regs->OCMD); 851 884 852 - intel_overlay_unmap_regs(overlay, regs); 853 - 854 885 ret = intel_overlay_continue(overlay, vma, scale_changed); 855 886 if (ret) 856 887 goto out_unpin; ··· 866 901 int intel_overlay_switch_off(struct intel_overlay *overlay) 867 902 { 868 903 struct drm_i915_private *dev_priv = overlay->i915; 869 - struct overlay_registers __iomem *regs; 870 904 int ret; 871 905 872 906 lockdep_assert_held(&dev_priv->drm.struct_mutex); ··· 882 918 if (ret != 0) 883 919 return ret; 884 920 885 - regs = intel_overlay_map_regs(overlay); 886 - iowrite32(0, &regs->OCMD); 887 - intel_overlay_unmap_regs(overlay, regs); 921 + iowrite32(0, &overlay->regs->OCMD); 888 922 889 923 return intel_overlay_off(overlay); 890 924 } ··· 1267 1305 struct drm_intel_overlay_attrs *attrs = data; 1268 1306 struct drm_i915_private *dev_priv = to_i915(dev); 1269 1307 struct intel_overlay *overlay; 1270 - struct overlay_registers __iomem *regs; 1271 1308 int ret; 1272 1309 1273 1310 overlay = dev_priv->overlay; ··· 1306 1345 overlay->contrast = attrs->contrast; 1307 1346 overlay->saturation = attrs->saturation; 1308 1347 1309 - regs = intel_overlay_map_regs(overlay); 1310 - if (!regs) { 1311 - ret = -ENOMEM; 1312 - goto out_unlock; 1313 - } 1314 - 1315 - update_reg_attrs(overlay, regs); 1316 - 1317 - intel_overlay_unmap_regs(overlay, regs); 1348 + update_reg_attrs(overlay, overlay->regs); 1318 1349 1319 1350 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1320 1351 if (IS_GEN2(dev_priv)) ··· 1339 1386 return ret; 1340 1387 } 1341 1388 1389 + static int get_registers(struct intel_overlay *overlay, bool use_phys) 1390 + { 1391 + struct drm_i915_gem_object *obj; 1392 + struct i915_vma *vma; 1393 + int err; 1394 + 1395 + obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE); 1396 + if (obj == NULL) 1397 + obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE); 1398 + if (IS_ERR(obj)) 1399 + return PTR_ERR(obj); 1400 + 1401 + vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1402 + if (IS_ERR(vma)) { 1403 + err = PTR_ERR(vma); 1404 + goto err_put_bo; 1405 + } 1406 + 1407 + if (use_phys) 1408 + overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1409 + else 1410 + overlay->flip_addr = i915_ggtt_offset(vma); 1411 + overlay->regs = i915_vma_pin_iomap(vma); 1412 + i915_vma_unpin(vma); 1413 + 1414 + if (IS_ERR(overlay->regs)) { 1415 + err = PTR_ERR(overlay->regs); 1416 + goto err_put_bo; 1417 + } 1418 + 1419 + overlay->reg_bo = obj; 1420 + return 0; 1421 + 1422 + err_put_bo: 1423 + i915_gem_object_put(obj); 1424 + return err; 1425 + } 1426 + 1342 1427 void intel_setup_overlay(struct drm_i915_private *dev_priv) 1343 1428 { 1344 1429 struct intel_overlay *overlay; 1345 - struct drm_i915_gem_object *reg_bo; 1346 - struct overlay_registers __iomem *regs; 1347 - struct i915_vma *vma = NULL; 1348 1430 int ret; 1349 1431 1350 1432 if (!HAS_OVERLAY(dev_priv)) ··· 1389 1401 if (!overlay) 1390 1402 return; 1391 1403 1392 - mutex_lock(&dev_priv->drm.struct_mutex); 1393 - if (WARN_ON(dev_priv->overlay)) 1394 - goto out_free; 1395 - 1396 1404 overlay->i915 = dev_priv; 1397 1405 1398 - reg_bo = NULL; 1399 - if (!OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1400 - reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE); 1401 - if (reg_bo == NULL) 1402 - reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE); 1403 - if (IS_ERR(reg_bo)) 1404 - goto out_free; 1405 - overlay->reg_bo = reg_bo; 1406 - 1407 - if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) { 1408 - ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); 1409 - if (ret) { 1410 - DRM_ERROR("failed to attach phys overlay regs\n"); 1411 - goto out_free_bo; 1412 - } 1413 - overlay->flip_addr = reg_bo->phys_handle->busaddr; 1414 - } else { 1415 - vma = i915_gem_object_ggtt_pin(reg_bo, NULL, 1416 - 0, PAGE_SIZE, PIN_MAPPABLE); 1417 - if (IS_ERR(vma)) { 1418 - DRM_ERROR("failed to pin overlay register bo\n"); 1419 - ret = PTR_ERR(vma); 1420 - goto out_free_bo; 1421 - } 1422 - overlay->flip_addr = i915_ggtt_offset(vma); 1423 - 1424 - ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); 1425 - if (ret) { 1426 - DRM_ERROR("failed to move overlay register bo into the GTT\n"); 1427 - goto out_unpin_bo; 1428 - } 1429 - } 1430 - 1431 - /* init all values */ 1432 1406 overlay->color_key = 0x0101fe; 1433 1407 overlay->color_key_enabled = true; 1434 1408 overlay->brightness = -19; ··· 1399 1449 1400 1450 init_request_active(&overlay->last_flip, NULL); 1401 1451 1402 - regs = intel_overlay_map_regs(overlay); 1403 - if (!regs) 1404 - goto out_unpin_bo; 1452 + mutex_lock(&dev_priv->drm.struct_mutex); 1405 1453 1406 - memset_io(regs, 0, sizeof(struct overlay_registers)); 1407 - update_polyphase_filter(regs); 1408 - update_reg_attrs(overlay, regs); 1454 + ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1455 + if (ret) 1456 + goto out_free; 1409 1457 1410 - intel_overlay_unmap_regs(overlay, regs); 1458 + ret = i915_gem_object_set_to_gtt_domain(overlay->reg_bo, true); 1459 + if (ret) 1460 + goto out_reg_bo; 1461 + 1462 + mutex_unlock(&dev_priv->drm.struct_mutex); 1463 + 1464 + memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1465 + update_polyphase_filter(overlay->regs); 1466 + update_reg_attrs(overlay, overlay->regs); 1411 1467 1412 1468 dev_priv->overlay = overlay; 1413 - mutex_unlock(&dev_priv->drm.struct_mutex); 1414 - DRM_INFO("initialized overlay support\n"); 1469 + DRM_INFO("Initialized overlay support.\n"); 1415 1470 return; 1416 1471 1417 - out_unpin_bo: 1418 - if (vma) 1419 - i915_vma_unpin(vma); 1420 - out_free_bo: 1421 - i915_gem_object_put(reg_bo); 1472 + out_reg_bo: 1473 + i915_gem_object_put(overlay->reg_bo); 1422 1474 out_free: 1423 1475 mutex_unlock(&dev_priv->drm.struct_mutex); 1424 1476 kfree(overlay); 1425 - return; 1426 1477 } 1427 1478 1428 1479 void intel_cleanup_overlay(struct drm_i915_private *dev_priv) 1429 1480 { 1430 - if (!dev_priv->overlay) 1481 + struct intel_overlay *overlay; 1482 + 1483 + overlay = fetch_and_zero(&dev_priv->overlay); 1484 + if (!overlay) 1431 1485 return; 1432 1486 1433 - /* The bo's should be free'd by the generic code already. 1487 + /* 1488 + * The bo's should be free'd by the generic code already. 1434 1489 * Furthermore modesetting teardown happens beforehand so the 1435 - * hardware should be off already */ 1436 - WARN_ON(dev_priv->overlay->active); 1490 + * hardware should be off already. 1491 + */ 1492 + WARN_ON(overlay->active); 1437 1493 1438 - i915_gem_object_put(dev_priv->overlay->reg_bo); 1439 - kfree(dev_priv->overlay); 1494 + i915_gem_object_put(overlay->reg_bo); 1495 + 1496 + kfree(overlay); 1440 1497 } 1441 1498 1442 1499 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ··· 1455 1498 u32 isr; 1456 1499 }; 1457 1500 1458 - static struct overlay_registers __iomem * 1459 - intel_overlay_map_regs_atomic(struct intel_overlay *overlay) 1460 - { 1461 - struct drm_i915_private *dev_priv = overlay->i915; 1462 - struct overlay_registers __iomem *regs; 1463 - 1464 - if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1465 - /* Cast to make sparse happy, but it's wc memory anyway, so 1466 - * equivalent to the wc io mapping on X86. */ 1467 - regs = (struct overlay_registers __iomem *) 1468 - overlay->reg_bo->phys_handle->vaddr; 1469 - else 1470 - regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.iomap, 1471 - overlay->flip_addr); 1472 - 1473 - return regs; 1474 - } 1475 - 1476 - static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, 1477 - struct overlay_registers __iomem *regs) 1478 - { 1479 - if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 1480 - io_mapping_unmap_atomic(regs); 1481 - } 1482 - 1483 1501 struct intel_overlay_error_state * 1484 1502 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1485 1503 { 1486 1504 struct intel_overlay *overlay = dev_priv->overlay; 1487 1505 struct intel_overlay_error_state *error; 1488 - struct overlay_registers __iomem *regs; 1489 1506 1490 1507 if (!overlay || !overlay->active) 1491 1508 return NULL; ··· 1472 1541 error->isr = I915_READ(ISR); 1473 1542 error->base = overlay->flip_addr; 1474 1543 1475 - regs = intel_overlay_map_regs_atomic(overlay); 1476 - if (!regs) 1477 - goto err; 1478 - 1479 - memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); 1480 - intel_overlay_unmap_regs_atomic(overlay, regs); 1544 + memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1481 1545 1482 1546 return error; 1483 - 1484 - err: 1485 - kfree(error); 1486 - return NULL; 1487 1547 } 1488 1548 1489 1549 void

+11 -10

drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.c

··· 86 86 struct nvkm_bios *bios = subdev->device->bios; 87 87 struct nvbios_pmuR pmu; 88 88 89 - if (!nvbios_pmuRm(bios, type, &pmu)) { 90 - nvkm_error(subdev, "VBIOS PMU fuc %02x not found\n", type); 89 + if (!nvbios_pmuRm(bios, type, &pmu)) 91 90 return -EINVAL; 92 - } 93 91 94 92 if (!post) 95 93 return 0; ··· 122 124 return -EINVAL; 123 125 } 124 126 127 + /* Upload DEVINIT application from VBIOS onto PMU. */ 125 128 ret = pmu_load(init, 0x04, post, &exec, &args); 126 - if (ret) 129 + if (ret) { 130 + nvkm_error(subdev, "VBIOS PMU/DEVINIT not found\n"); 127 131 return ret; 132 + } 128 133 129 - /* upload first chunk of init data */ 134 + /* Upload tables required by opcodes in boot scripts. */ 130 135 if (post) { 131 - // devinit tables 132 136 u32 pmu = pmu_args(init, args + 0x08, 0x08); 133 137 u32 img = nvbios_rd16(bios, bit_I.offset + 0x14); 134 138 u32 len = nvbios_rd16(bios, bit_I.offset + 0x16); 135 139 pmu_data(init, pmu, img, len); 136 140 } 137 141 138 - /* upload second chunk of init data */ 142 + /* Upload boot scripts. */ 139 143 if (post) { 140 - // devinit boot scripts 141 144 u32 pmu = pmu_args(init, args + 0x08, 0x10); 142 145 u32 img = nvbios_rd16(bios, bit_I.offset + 0x18); 143 146 u32 len = nvbios_rd16(bios, bit_I.offset + 0x1a); 144 147 pmu_data(init, pmu, img, len); 145 148 } 146 149 147 - /* execute init tables */ 150 + /* Execute DEVINIT. */ 148 151 if (post) { 149 152 nvkm_wr32(device, 0x10a040, 0x00005000); 150 153 pmu_exec(init, exec); ··· 156 157 return -ETIMEDOUT; 157 158 } 158 159 159 - /* load and execute some other ucode image (bios therm?) */ 160 + /* Optional: Execute PRE_OS application on PMU, which should at 161 + * least take care of fans until a full PMU has been loaded. 162 + */ 160 163 pmu_load(init, 0x01, post, NULL, NULL); 161 164 return 0; 162 165 }

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