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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
Add pinctrl definitions for Rockchip RV1126.
From RK3568 on-wards pinctrl configurations are maintained
in common conf file rockchip-pinconf.dtsi and it is available
in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi).
So, include the same conf file to RV1126 pinctrl from arm64 path.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20221129075424.189655-4-jagan@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
authored by
Jagan Teki
and committed by
Heiko Stuebner
0fa22d06
d7ffb4c3
+212
-1
+1
-1
MAINTAINERS
+1
-1
MAINTAINERS
···
2807
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F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
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F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
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F: arch/arm/boot/dts/rk3*
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-
F: arch/arm/boot/dts/rv1108*
2810
+
F: arch/arm/boot/dts/rv11*
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2811
F: arch/arm/mach-rockchip/
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F: drivers/*/*/*rockchip*
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2813
F: drivers/*/*rockchip*
+211
arch/arm/boot/dts/rv1126-pinctrl.dtsi
+211
arch/arm/boot/dts/rv1126-pinctrl.dtsi
···
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <arm64/rockchip/rockchip-pinconf.dtsi>
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/*
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* This file is auto generated by pin2dts tool, please keep these code
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* by adding changes at end of this file.
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*/
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&pinctrl {
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emmc {
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/omit-if-no-ref/
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emmc_rstnout: emmc-rstnout {
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rockchip,pins =
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/* emmc_rstn */
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<1 RK_PA3 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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emmc_bus8: emmc-bus8 {
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rockchip,pins =
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/* emmc_d0 */
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<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d1 */
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<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d2 */
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<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d3 */
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<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d4 */
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<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d5 */
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<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d6 */
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<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
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/* emmc_d7 */
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<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_clk: emmc-clk {
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rockchip,pins =
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/* emmc_clko */
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<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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emmc_cmd: emmc-cmd {
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rockchip,pins =
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/* emmc_cmd */
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<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
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};
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};
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i2c0 {
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/omit-if-no-ref/
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i2c0_xfer: i2c0-xfer {
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rockchip,pins =
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/* i2c0_scl */
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<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
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/* i2c0_sda */
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<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
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};
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};
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sdmmc0 {
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/omit-if-no-ref/
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sdmmc0_bus4: sdmmc0-bus4 {
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rockchip,pins =
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/* sdmmc0_d0 */
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<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc0_d1 */
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<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc0_d2 */
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<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc0_d3 */
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<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc0_clk: sdmmc0-clk {
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rockchip,pins =
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/* sdmmc0_clk */
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<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc0_cmd: sdmmc0-cmd {
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rockchip,pins =
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/* sdmmc0_cmd */
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<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc0_det: sdmmc0-det {
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rockchip,pins =
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<0 RK_PA3 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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sdmmc0_pwr: sdmmc0-pwr {
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rockchip,pins =
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<0 RK_PC0 1 &pcfg_pull_none>;
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};
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};
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sdmmc1 {
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/omit-if-no-ref/
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sdmmc1_bus4: sdmmc1-bus4 {
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rockchip,pins =
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/* sdmmc1_d0 */
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<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc1_d1 */
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<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc1_d2 */
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<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
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/* sdmmc1_d3 */
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<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc1_clk: sdmmc1-clk {
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rockchip,pins =
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/* sdmmc1_clk */
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<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc1_cmd: sdmmc1-cmd {
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rockchip,pins =
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/* sdmmc1_cmd */
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<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
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};
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/omit-if-no-ref/
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sdmmc1_det: sdmmc1-det {
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rockchip,pins =
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<1 RK_PD0 2 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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sdmmc1_pwr: sdmmc1-pwr {
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rockchip,pins =
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<1 RK_PD1 2 &pcfg_pull_none>;
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};
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};
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uart0 {
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/omit-if-no-ref/
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uart0_xfer: uart0-xfer {
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rockchip,pins =
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/* uart0_rx */
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<1 RK_PC2 1 &pcfg_pull_up>,
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/* uart0_tx */
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<1 RK_PC3 1 &pcfg_pull_up>;
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};
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/omit-if-no-ref/
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uart0_ctsn: uart0-ctsn {
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rockchip,pins =
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<1 RK_PC1 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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uart0_rtsn: uart0-rtsn {
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rockchip,pins =
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<1 RK_PC0 1 &pcfg_pull_none>;
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};
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/omit-if-no-ref/
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uart0_rtsn_gpio: uart0-rts-pin {
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rockchip,pins =
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<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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uart1 {
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/omit-if-no-ref/
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uart1m0_xfer: uart1m0-xfer {
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rockchip,pins =
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/* uart1_rx_m0 */
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<0 RK_PB7 2 &pcfg_pull_up>,
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/* uart1_tx_m0 */
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<0 RK_PB6 2 &pcfg_pull_up>;
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};
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};
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uart2 {
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/omit-if-no-ref/
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uart2m1_xfer: uart2m1-xfer {
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rockchip,pins =
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/* uart2_rx_m1 */
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<3 RK_PA3 1 &pcfg_pull_up>,
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/* uart2_tx_m1 */
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<3 RK_PA2 1 &pcfg_pull_up>;
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};
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};
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uart3 {
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/omit-if-no-ref/
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uart3m0_xfer: uart3m0-xfer {
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rockchip,pins =
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/* uart3_rx_m0 */
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<3 RK_PC7 4 &pcfg_pull_up>,
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/* uart3_tx_m0 */
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<3 RK_PC6 4 &pcfg_pull_up>;
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};
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};
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uart4 {
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/omit-if-no-ref/
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uart4m0_xfer: uart4m0-xfer {
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rockchip,pins =
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/* uart4_rx_m0 */
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<3 RK_PA5 4 &pcfg_pull_up>,
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/* uart4_tx_m0 */
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<3 RK_PA4 4 &pcfg_pull_up>;
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};
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};
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uart5 {
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/omit-if-no-ref/
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uart5m0_xfer: uart5m0-xfer {
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rockchip,pins =
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/* uart5_rx_m0 */
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<3 RK_PA7 4 &pcfg_pull_up>,
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/* uart5_tx_m0 */
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<3 RK_PA6 4 &pcfg_pull_up>;
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};
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};
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};