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Merge branch 'net-stmmac-qcom-ethqos-more-cleanups'

Russell King says:

====================
net: stmmac: qcom-ethqos: more cleanups

Further cleanups to qcom-ethqos, mainly concentrating on the RGMII
code, making it clearer what the differences are for each speed, thus
making the code more readable.

I'm still not really happy with this. The speed specific configuration
remains split between ethqos_fix_mac_speed_rgmii() and
ethqos_rgmii_macro_init(), where the latter is only ever called from
the former. So, I think further work is needed here - maybe it needs
restructuring into the various componenet parts of the RGMII block?
====================

Link: https://patch.msgid.link/acZDEg9wdjhBTHlL@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

Jakub Kicinski 0fb03e70 911e2c05

+109 -155
+109 -155
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
··· 100 100 struct qcom_ethqos { 101 101 struct platform_device *pdev; 102 102 void __iomem *rgmii_base; 103 - void (*configure_func)(struct qcom_ethqos *ethqos, 104 - phy_interface_t interface, int speed); 105 - 106 103 struct clk *link_clk; 107 104 struct phy *serdes_phy; 108 105 phy_interface_t phy_mode; ··· 374 377 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed) 375 378 { 376 379 struct device *dev = &ethqos->pdev->dev; 377 - int phase_shift; 378 - int loopback; 380 + unsigned int prg_rclk_dly, loopback; 381 + unsigned int phase_shift; 382 + 383 + /* Disable loopback mode */ 384 + rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 385 + RGMII_IO_MACRO_CONFIG2); 386 + 387 + /* Select RGMII, write 0 to interface select */ 388 + rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG); 389 + 390 + if (speed != SPEED_1000 && speed != SPEED_100 && speed != SPEED_10) { 391 + dev_err(dev, "Invalid speed %d\n", speed); 392 + return -EINVAL; 393 + } 394 + 395 + rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG); 396 + 397 + if (speed == SPEED_1000) { 398 + rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 399 + RGMII_IO_MACRO_CONFIG); 400 + rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 401 + RGMII_IO_MACRO_CONFIG); 402 + rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP, 403 + RGMII_IO_MACRO_CONFIG); 404 + } else { 405 + rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 406 + RGMII_IO_MACRO_CONFIG); 407 + rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 408 + RGMII_IO_MACRO_CONFIG); 409 + rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP, 410 + RGMII_IO_MACRO_CONFIG); 411 + } 412 + 413 + rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 414 + RGMII_IO_MACRO_CONFIG2); 379 415 380 416 /* Determine if the PHY adds a 2 ns TX delay or the MAC handles it */ 381 417 if (ethqos->phy_mode == PHY_INTERFACE_MODE_RGMII_ID || ··· 417 387 else 418 388 phase_shift = RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN; 419 389 420 - /* Disable loopback mode */ 421 - rgmii_clrmask(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN, 390 + rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, phase_shift, 422 391 RGMII_IO_MACRO_CONFIG2); 423 392 424 - /* Determine if this platform wants loopback enabled after programming */ 393 + if (speed == SPEED_100) 394 + rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 395 + FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_2, 1), 396 + RGMII_IO_MACRO_CONFIG); 397 + else if (speed == SPEED_10) 398 + rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 399 + FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_9, 19), 400 + RGMII_IO_MACRO_CONFIG); 401 + 402 + rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 403 + RGMII_IO_MACRO_CONFIG2); 404 + 405 + if (speed == SPEED_1000 || ethqos->has_emac_ge_3) 406 + rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 407 + RGMII_IO_MACRO_CONFIG2); 408 + else 409 + rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 410 + RGMII_IO_MACRO_CONFIG2); 411 + 412 + if (speed != SPEED_1000) { 413 + /* Write 0x5 to PRG_RCLK_DLY_CODE */ 414 + rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 415 + FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 416 + 5), SDCC_HC_REG_DDR_CONFIG); 417 + 418 + rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 419 + SDCC_HC_REG_DDR_CONFIG); 420 + 421 + rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 422 + SDCC_HC_REG_DDR_CONFIG); 423 + } else { 424 + /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 425 + * (2 * RX delay ns), 426 + * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 427 + * (2 * RX delay ns) 428 + */ 429 + if (ethqos->has_emac_ge_3) { 430 + /* 0.9 ns */ 431 + prg_rclk_dly = 115; 432 + } else { 433 + /* 1.8 ns */ 434 + prg_rclk_dly = 57; 435 + } 436 + 437 + rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 438 + FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY, 439 + prg_rclk_dly), SDCC_HC_REG_DDR_CONFIG); 440 + 441 + rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 442 + SDCC_HC_REG_DDR_CONFIG); 443 + } 444 + 425 445 if (ethqos->rgmii_config_loopback_en) 426 446 loopback = RGMII_CONFIG_LOOPBACK_EN; 427 447 else 428 448 loopback = 0; 429 449 430 - /* Select RGMII, write 0 to interface select */ 431 - rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG); 432 - 433 - switch (speed) { 434 - case SPEED_1000: 435 - rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 436 - RGMII_IO_MACRO_CONFIG); 437 - rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 438 - RGMII_IO_MACRO_CONFIG); 439 - rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 440 - RGMII_IO_MACRO_CONFIG); 441 - rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP, 442 - RGMII_IO_MACRO_CONFIG); 443 - rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 444 - RGMII_IO_MACRO_CONFIG2); 445 - 446 - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 447 - phase_shift, RGMII_IO_MACRO_CONFIG2); 448 - rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 449 - RGMII_IO_MACRO_CONFIG2); 450 - rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 451 - RGMII_IO_MACRO_CONFIG2); 452 - 453 - /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns, 454 - * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns 455 - */ 456 - if (ethqos->has_emac_ge_3) { 457 - /* 0.9 ns */ 458 - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 459 - FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY, 460 - 115), SDCC_HC_REG_DDR_CONFIG); 461 - } else { 462 - /* 1.8 ns */ 463 - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY, 464 - FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY, 465 - 57), SDCC_HC_REG_DDR_CONFIG); 466 - } 467 - rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN, 468 - SDCC_HC_REG_DDR_CONFIG); 469 - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 470 - loopback, RGMII_IO_MACRO_CONFIG); 471 - break; 472 - 473 - case SPEED_100: 474 - rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 475 - RGMII_IO_MACRO_CONFIG); 476 - rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 477 - RGMII_IO_MACRO_CONFIG); 478 - rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 479 - RGMII_IO_MACRO_CONFIG); 480 - rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP, 481 - RGMII_IO_MACRO_CONFIG); 482 - rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 483 - RGMII_IO_MACRO_CONFIG2); 484 - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 485 - phase_shift, RGMII_IO_MACRO_CONFIG2); 486 - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2, 487 - FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_2, 1), 488 - RGMII_IO_MACRO_CONFIG); 489 - rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 490 - RGMII_IO_MACRO_CONFIG2); 491 - 492 - if (ethqos->has_emac_ge_3) 493 - rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 494 - RGMII_IO_MACRO_CONFIG2); 495 - else 496 - rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 497 - RGMII_IO_MACRO_CONFIG2); 498 - 499 - /* Write 0x5 to PRG_RCLK_DLY_CODE */ 500 - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 501 - FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 502 - 5), SDCC_HC_REG_DDR_CONFIG); 503 - rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 504 - SDCC_HC_REG_DDR_CONFIG); 505 - rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 506 - SDCC_HC_REG_DDR_CONFIG); 507 - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 508 - loopback, RGMII_IO_MACRO_CONFIG); 509 - break; 510 - 511 - case SPEED_10: 512 - rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, 513 - RGMII_IO_MACRO_CONFIG); 514 - rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN, 515 - RGMII_IO_MACRO_CONFIG); 516 - rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL, 517 - RGMII_IO_MACRO_CONFIG); 518 - rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP, 519 - RGMII_IO_MACRO_CONFIG); 520 - rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL, 521 - RGMII_IO_MACRO_CONFIG2); 522 - rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, 523 - phase_shift, RGMII_IO_MACRO_CONFIG2); 524 - rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9, 525 - FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_9, 19), 526 - RGMII_IO_MACRO_CONFIG); 527 - rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15, 528 - RGMII_IO_MACRO_CONFIG2); 529 - if (ethqos->has_emac_ge_3) 530 - rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 531 - RGMII_IO_MACRO_CONFIG2); 532 - else 533 - rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP, 534 - RGMII_IO_MACRO_CONFIG2); 535 - /* Write 0x5 to PRG_RCLK_DLY_CODE */ 536 - rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 537 - FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, 538 - 5), SDCC_HC_REG_DDR_CONFIG); 539 - rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY, 540 - SDCC_HC_REG_DDR_CONFIG); 541 - rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN, 542 - SDCC_HC_REG_DDR_CONFIG); 543 - rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, 544 - loopback, RGMII_IO_MACRO_CONFIG); 545 - break; 546 - default: 547 - dev_err(dev, "Invalid speed %d\n", speed); 548 - return -EINVAL; 549 - } 450 + rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, loopback, 451 + RGMII_IO_MACRO_CONFIG); 550 452 551 453 return 0; 552 454 } 553 455 554 - static void ethqos_configure_rgmii(struct qcom_ethqos *ethqos, 555 - phy_interface_t interface, int speed) 456 + static void ethqos_fix_mac_speed_rgmii(void *bsp_priv, 457 + phy_interface_t interface, int speed, 458 + unsigned int mode) 556 459 { 557 - struct device *dev = &ethqos->pdev->dev; 460 + struct qcom_ethqos *ethqos = bsp_priv; 461 + struct device *dev; 558 462 unsigned int i; 559 463 u32 val; 464 + 465 + dev = &ethqos->pdev->dev; 560 466 561 467 /* Reset to POR values and enable clk */ 562 468 for (i = 0; i < ethqos->num_rgmii_por; i++) ··· 556 590 ethqos_rgmii_macro_init(ethqos, speed); 557 591 } 558 592 559 - static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable) 593 + static void ethqos_pcs_set_inband(struct qcom_ethqos *ethqos, bool enable) 560 594 { 595 + struct net_device *dev = platform_get_drvdata(ethqos->pdev); 596 + struct stmmac_priv *priv = netdev_priv(dev); 597 + 561 598 stmmac_pcs_ctrl_ane(priv, enable, 0); 562 599 } 563 600 564 601 /* On interface toggle MAC registers gets reset. 565 602 * Configure MAC block for SGMII on ethernet phy link up 566 603 */ 567 - static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos, 568 - phy_interface_t interface, int speed) 604 + static void ethqos_fix_mac_speed_sgmii(void *bsp_priv, 605 + phy_interface_t interface, int speed, 606 + unsigned int mode) 569 607 { 570 - struct net_device *dev = platform_get_drvdata(ethqos->pdev); 571 - struct stmmac_priv *priv = netdev_priv(dev); 608 + struct qcom_ethqos *ethqos = bsp_priv; 572 609 573 610 switch (speed) { 574 611 case SPEED_2500: ··· 589 620 break; 590 621 } 591 622 592 - ethqos_pcs_set_inband(priv, interface == PHY_INTERFACE_MODE_SGMII); 593 - } 594 - 595 - static void ethqos_configure(struct qcom_ethqos *ethqos, 596 - phy_interface_t interface, int speed) 597 - { 598 - return ethqos->configure_func(ethqos, interface, speed); 599 - } 600 - 601 - static void ethqos_fix_mac_speed(void *priv, phy_interface_t interface, 602 - int speed, unsigned int mode) 603 - { 604 - struct qcom_ethqos *ethqos = priv; 605 - 606 - ethqos_configure(ethqos, interface, speed); 623 + ethqos_pcs_set_inband(ethqos, interface == PHY_INTERFACE_MODE_SGMII); 607 624 } 608 625 609 626 static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv) ··· 648 693 /* Enable functional clock to prevent DMA reset to timeout due 649 694 * to lacking PHY clock after the hardware block has been power 650 695 * cycled. The actual configuration will be adjusted once 651 - * ethqos_fix_mac_speed() is invoked. 696 + * ethqos' fix_mac_speed() method is invoked. 652 697 */ 653 698 qcom_ethqos_set_sgmii_loopback(ethqos, true); 654 699 ethqos_set_func_clk_en(ethqos); ··· 714 759 case PHY_INTERFACE_MODE_RGMII_ID: 715 760 case PHY_INTERFACE_MODE_RGMII_RXID: 716 761 case PHY_INTERFACE_MODE_RGMII_TXID: 717 - ethqos->configure_func = ethqos_configure_rgmii; 762 + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii; 718 763 break; 719 764 case PHY_INTERFACE_MODE_2500BASEX: 720 765 case PHY_INTERFACE_MODE_SGMII: 721 - ethqos->configure_func = ethqos_configure_sgmii; 766 + plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii; 722 767 plat_dat->mac_finish = ethqos_mac_finish_serdes; 723 768 break; 724 769 default: ··· 766 811 767 812 plat_dat->bsp_priv = ethqos; 768 813 plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate; 769 - plat_dat->fix_mac_speed = ethqos_fix_mac_speed; 770 814 plat_dat->dump_debug_regs = rgmii_dump; 771 815 plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config; 772 816 plat_dat->core_type = DWMAC_CORE_GMAC4;