Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Clock driver for the Rockchip RV1103B SoC
For whatever reason that SoC only got a B addition to the name,
but major changes internally - likely it is pin compatible with
the non-b-variant. Other change is actually exporting PCIe
pipe-clocks that were already in the binding.
* tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3568: Add PCIe pipe clock gates
clk: rockchip: Add clock controller for the RV1103B
dt-bindings: clock: rockchip: Add RV1103B CRU support
+942
+1
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+1
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+7
drivers/clk/rockchip/Kconfig
+7
drivers/clk/rockchip/Kconfig
···
16
16
help
17
17
Build the driver for PX30 Clock Driver.
18
18
19
+
config CLK_RV1103B
20
+
bool "Rockchip RV1103B clock controller support"
21
+
depends on ARM || COMPILE_TEST
22
+
default y
23
+
help
24
+
Build the driver for RV1103B Clock Driver.
25
+
19
26
config CLK_RV110X
20
27
bool "Rockchip RV110x clock controller support"
21
28
depends on ARM || COMPILE_TEST
+1
drivers/clk/rockchip/Makefile
+1
drivers/clk/rockchip/Makefile
···
18
18
clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
19
19
20
20
obj-$(CONFIG_CLK_PX30) += clk-px30.o
21
+
obj-$(CONFIG_CLK_RV1103B) += clk-rv1103b.o
21
22
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
22
23
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
23
24
obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
+6
drivers/clk/rockchip/clk-rk3568.c
+6
drivers/clk/rockchip/clk-rk3568.c
···
827
827
RK3568_CLKGATE_CON(12), 3, GFLAGS),
828
828
GATE(CLK_PCIE20_AUX_NDFT, "clk_pcie20_aux_ndft", "xin24m", 0,
829
829
RK3568_CLKGATE_CON(12), 4, GFLAGS),
830
+
GATE(CLK_PCIE20_PIPE_DFT, "clk_pcie20_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
831
+
RK3568_CLKGATE_CON(12), 5, GFLAGS),
830
832
GATE(ACLK_PCIE30X1_MST, "aclk_pcie30x1_mst", "aclk_pipe", 0,
831
833
RK3568_CLKGATE_CON(12), 8, GFLAGS),
832
834
GATE(ACLK_PCIE30X1_SLV, "aclk_pcie30x1_slv", "aclk_pipe", 0,
···
839
837
RK3568_CLKGATE_CON(12), 11, GFLAGS),
840
838
GATE(CLK_PCIE30X1_AUX_NDFT, "clk_pcie30x1_aux_ndft", "xin24m", 0,
841
839
RK3568_CLKGATE_CON(12), 12, GFLAGS),
840
+
GATE(CLK_PCIE30X1_PIPE_DFT, "clk_pcie30x1_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
841
+
RK3568_CLKGATE_CON(12), 13, GFLAGS),
842
842
GATE(ACLK_PCIE30X2_MST, "aclk_pcie30x2_mst", "aclk_pipe", 0,
843
843
RK3568_CLKGATE_CON(13), 0, GFLAGS),
844
844
GATE(ACLK_PCIE30X2_SLV, "aclk_pcie30x2_slv", "aclk_pipe", 0,
···
851
847
RK3568_CLKGATE_CON(13), 3, GFLAGS),
852
848
GATE(CLK_PCIE30X2_AUX_NDFT, "clk_pcie30x2_aux_ndft", "xin24m", 0,
853
849
RK3568_CLKGATE_CON(13), 4, GFLAGS),
850
+
GATE(CLK_PCIE30X2_PIPE_DFT, "clk_pcie30x2_pipe_dft", "aclk_pipe", CLK_IGNORE_UNUSED,
851
+
RK3568_CLKGATE_CON(13), 5, GFLAGS),
854
852
GATE(ACLK_SATA0, "aclk_sata0", "aclk_pipe", 0,
855
853
RK3568_CLKGATE_CON(11), 0, GFLAGS),
856
854
GATE(CLK_SATA0_PMALIVE, "clk_sata0_pmalive", "gpll_20m", 0,
+658
drivers/clk/rockchip/clk-rv1103b.c
+658
drivers/clk/rockchip/clk-rv1103b.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/of.h>
9
+
#include <linux/of_address.h>
10
+
#include <dt-bindings/clock/rockchip,rv1103b-cru.h>
11
+
#include "clk.h"
12
+
13
+
#define RV1103B_GRF_SOC_STATUS0 0x10
14
+
#define RV1103B_FRAC_MAX_PRATE 1200000000
15
+
#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
16
+
17
+
enum rv1103b_plls {
18
+
dpll,
19
+
gpll,
20
+
};
21
+
22
+
static struct rockchip_pll_rate_table rv1103b_pll_rates[] = {
23
+
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
24
+
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
25
+
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
26
+
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
27
+
{ /* sentinel */ },
28
+
};
29
+
30
+
#define RV1103B_DIV_ACLK_CORE_MASK 0x1f
31
+
#define RV1103B_DIV_ACLK_CORE_SHIFT 0
32
+
#define RV1103B_DIV_PCLK_DBG_MASK 0x1f
33
+
#define RV1103B_DIV_PCLK_DBG_SHIFT 8
34
+
35
+
#define RV1103B_CLKSEL0(_aclk_core) \
36
+
{ \
37
+
.reg = RV1103B_CORECLKSEL_CON(2), \
38
+
.val = HIWORD_UPDATE(_aclk_core - 1, RV1103B_DIV_ACLK_CORE_MASK, \
39
+
RV1103B_DIV_ACLK_CORE_SHIFT), \
40
+
}
41
+
42
+
#define RV1103B_CLKSEL1(_pclk_dbg) \
43
+
{ \
44
+
.reg = RV1103B_CORECLKSEL_CON(2), \
45
+
.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1103B_DIV_PCLK_DBG_MASK, \
46
+
RV1103B_DIV_PCLK_DBG_SHIFT), \
47
+
}
48
+
49
+
#define RV1103B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
50
+
{ \
51
+
.prate = _prate, \
52
+
.divs = { \
53
+
RV1103B_CLKSEL0(_aclk_core), \
54
+
RV1103B_CLKSEL1(_pclk_dbg), \
55
+
}, \
56
+
}
57
+
58
+
static struct rockchip_cpuclk_rate_table rv1103b_cpuclk_rates[] __initdata = {
59
+
RV1103B_CPUCLK_RATE(1608000000, 4, 10),
60
+
RV1103B_CPUCLK_RATE(1512000000, 4, 10),
61
+
RV1103B_CPUCLK_RATE(1416000000, 4, 10),
62
+
RV1103B_CPUCLK_RATE(1296000000, 3, 10),
63
+
RV1103B_CPUCLK_RATE(1200000000, 3, 10),
64
+
RV1103B_CPUCLK_RATE(1188000000, 3, 8),
65
+
RV1103B_CPUCLK_RATE(1104000000, 2, 8),
66
+
RV1103B_CPUCLK_RATE(1008000000, 2, 8),
67
+
RV1103B_CPUCLK_RATE(816000000, 2, 6),
68
+
RV1103B_CPUCLK_RATE(600000000, 2, 4),
69
+
RV1103B_CPUCLK_RATE(594000000, 2, 4),
70
+
RV1103B_CPUCLK_RATE(408000000, 1, 3),
71
+
RV1103B_CPUCLK_RATE(396000000, 1, 3),
72
+
};
73
+
74
+
PNAME(mux_pll_p) = { "xin24m" };
75
+
PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_gpll_div12" };
76
+
PNAME(mux_gpll_24m_p) = { "gpll", "xin24m" };
77
+
PNAME(mux_480m_400m_300m_200m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
78
+
PNAME(mux_480m_400m_300m_p) = { "clk_gpll_div2p5", "clk_gpll_div3", "clk_gpll_div4" };
79
+
PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
80
+
PNAME(mux_600m_480m_400m_p) = { "clk_gpll_div2", "clk_gpll_div2p5", "clk_gpll_div3" };
81
+
PNAME(mux_400m_300m_p) = { "clk_gpll_div3", "clk_gpll_div4" };
82
+
PNAME(mux_100m_24m_p) = { "clk_gpll_div12", "xin24m" };
83
+
PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
84
+
PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_gpll_div12", "clk_gpll_div24", "xin24m" };
85
+
PNAME(mux_300m_200m_100m_p) = { "clk_gpll_div4", "clk_gpll_div6", "clk_gpll_div12" };
86
+
PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
87
+
PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
88
+
PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
89
+
PNAME(mclk_sai_src_p) = { "clk_sai_src", "clk_sai_frac", "mclk_sai_from_io", "xin_osc0_half" };
90
+
PNAME(clk_freq_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
91
+
PNAME(clk_counter_pwm0_src_p) = { "sclk_sai_from_io", "mclk_sai_from_io", "clk_testout_out" };
92
+
PNAME(clk_mipi0_out2io_p) = { "clk_ref_mipi0", "xin24m" };
93
+
PNAME(clk_mipi1_out2io_p) = { "clk_ref_mipi1", "xin24m" };
94
+
PNAME(mclk_sai_out2io_p) = { "mclk_sai_src", "xin_osc0_half" };
95
+
PNAME(aclk_npu_root_p) = { "clk_npu_src", "clk_npu_pvtpll" };
96
+
PNAME(clk_core_vepu_p) = { "clk_vepu_src", "clk_vepu_pvtpll" };
97
+
PNAME(lsclk_vi_root_p) = { "clk_gpll_div6", "lsclk_vi_100m" };
98
+
PNAME(clk_core_isp_p) = { "clk_isp_src", "clk_isp_pvtpll_src" };
99
+
PNAME(lsclk_pmu_root_p) = { "xin24m", "clk_rc_osc_io" };
100
+
PNAME(xin_rc_div_p) = { "xin24m", "clk_rc_osc_io" };
101
+
PNAME(clk_32k_p) = { "xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
102
+
PNAME(dbclk_pmu_gpio0_p) = { "xin24m", "clk_32k" };
103
+
PNAME(sclk_sfc_2x_pmu1_p) = { "clk_gpll_div12", "clk_rc_osc_io" };
104
+
PNAME(mux_armclk_p) = { "armclk_gpll", "clk_core_pvtpll" };
105
+
106
+
static struct rockchip_pll_clock rv1103b_pll_clks[] __initdata = {
107
+
[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
108
+
CLK_IS_CRITICAL, RV1103B_PLL_CON(16),
109
+
RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
110
+
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
111
+
CLK_IS_CRITICAL, RV1103B_PLL_CON(24),
112
+
RV1103B_MODE_CON, 0, 10, 0, rv1103b_pll_rates),
113
+
};
114
+
115
+
#define MFLAGS CLK_MUX_HIWORD_MASK
116
+
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
117
+
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
118
+
119
+
static struct rockchip_clk_branch rv1103b_clk_uart0_fracmux __initdata =
120
+
MUX(SCLK_UART0_SRC, "sclk_uart0_src", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
121
+
RV1103B_CLKSEL_CON(32), 8, 2, MFLAGS);
122
+
123
+
static struct rockchip_clk_branch rv1103b_clk_uart1_fracmux __initdata =
124
+
MUX(SCLK_UART1_SRC, "sclk_uart1_src", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
125
+
RV1103B_CLKSEL_CON(32), 10, 2, MFLAGS);
126
+
127
+
static struct rockchip_clk_branch rv1103b_clk_uart2_fracmux __initdata =
128
+
MUX(SCLK_UART2_SRC, "sclk_uart2_src", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
129
+
RV1103B_CLKSEL_CON(32), 12, 2, MFLAGS);
130
+
131
+
static struct rockchip_clk_branch rv1103b_rcdiv_pmu_fracmux __initdata =
132
+
MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
133
+
RK3568_PMU_CLKSEL_CON(0), 0, 2, MFLAGS);
134
+
135
+
static struct rockchip_clk_branch rv1103b_clk_branches[] __initdata = {
136
+
137
+
/* Clock Definition */
138
+
FACTOR(XIN_OSC0_HALF, "xin_osc0_half", "xin24m", 0, 1, 2),
139
+
140
+
COMPOSITE_NOGATE(0, "armclk_gpll", mux_gpll_24m_p, CLK_IS_CRITICAL,
141
+
RV1103B_CLKSEL_CON(37), 12, 1, MFLAGS, 13, 3, DFLAGS),
142
+
143
+
/* pd_top */
144
+
COMPOSITE_NOMUX(CLK_GPLL_DIV24, "clk_gpll_div24", "gpll", 0,
145
+
RV1103B_CLKSEL_CON(0), 0, 5, DFLAGS,
146
+
RV1103B_CLKGATE_CON(0), 0, GFLAGS),
147
+
COMPOSITE_NOMUX(CLK_GPLL_DIV12, "clk_gpll_div12", "gpll", 0,
148
+
RV1103B_CLKSEL_CON(0), 5, 5, DFLAGS,
149
+
RV1103B_CLKGATE_CON(0), 1, GFLAGS),
150
+
COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
151
+
RV1103B_CLKSEL_CON(1), 0, 5, DFLAGS,
152
+
RV1103B_CLKGATE_CON(0), 3, GFLAGS),
153
+
COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
154
+
RV1103B_CLKSEL_CON(1), 10, 5, DFLAGS,
155
+
RV1103B_CLKGATE_CON(0), 5, GFLAGS),
156
+
COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
157
+
RV1103B_CLKSEL_CON(2), 0, 5, DFLAGS,
158
+
RV1103B_CLKGATE_CON(0), 7, GFLAGS),
159
+
COMPOSITE_NOMUX_HALFDIV(CLK_GPLL_DIV2P5, "clk_gpll_div2p5", "gpll", 0,
160
+
RV1103B_CLKSEL_CON(2), 5, 5, DFLAGS,
161
+
RV1103B_CLKGATE_CON(0), 8, GFLAGS),
162
+
COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
163
+
RV1103B_CLKSEL_CON(2), 10, 5, DFLAGS,
164
+
RV1103B_CLKGATE_CON(0), 9, GFLAGS),
165
+
COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
166
+
RV1103B_CLKSEL_CON(5), 0, 5, DFLAGS,
167
+
RV1103B_CLKGATE_CON(1), 0, GFLAGS),
168
+
COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
169
+
RV1103B_CLKSEL_CON(5), 5, 5, DFLAGS,
170
+
RV1103B_CLKGATE_CON(1), 1, GFLAGS),
171
+
COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
172
+
RV1103B_CLKSEL_CON(5), 10, 5, DFLAGS,
173
+
RV1103B_CLKGATE_CON(1), 2, GFLAGS),
174
+
COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", 0,
175
+
RV1103B_CLKSEL_CON(10), 0,
176
+
RV1103B_CLKGATE_CON(1), 6, GFLAGS,
177
+
&rv1103b_clk_uart0_fracmux),
178
+
COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", 0,
179
+
RV1103B_CLKSEL_CON(11), 0,
180
+
RV1103B_CLKGATE_CON(1), 7, GFLAGS,
181
+
&rv1103b_clk_uart1_fracmux),
182
+
COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", 0,
183
+
RV1103B_CLKSEL_CON(12), 0,
184
+
RV1103B_CLKGATE_CON(1), 8, GFLAGS,
185
+
&rv1103b_clk_uart2_fracmux),
186
+
GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_src", 0,
187
+
RV1103B_CLKGATE_CON(3), 3, GFLAGS),
188
+
GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_src", 0,
189
+
RV1103B_CLKGATE_CON(3), 4, GFLAGS),
190
+
GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_src", 0,
191
+
RV1103B_CLKGATE_CON(3), 8, GFLAGS),
192
+
193
+
COMPOSITE_NOMUX(CLK_SAI_SRC, "clk_sai_src", "gpll", 0,
194
+
RV1103B_CLKSEL_CON(20), 0, 5, DFLAGS,
195
+
RV1103B_CLKGATE_CON(1), 12, GFLAGS),
196
+
MUX(MCLK_SAI_SRC, "mclk_sai_src", mclk_sai_src_p, CLK_SET_RATE_PARENT,
197
+
RV1103B_CLKSEL_CON(35), 10, 2, MFLAGS),
198
+
GATE(MCLK_SAI, "mclk_sai", "mclk_sai_src", 0,
199
+
RV1103B_CLKGATE_CON(5), 5, GFLAGS),
200
+
201
+
COMPOSITE_NODIV(LSCLK_NPU_SRC, "lsclk_npu_src", mux_200m_100m_p, CLK_IS_CRITICAL,
202
+
RV1103B_CLKSEL_CON(30), 0, 1, MFLAGS,
203
+
RV1103B_CLKGATE_CON(2), 0, GFLAGS),
204
+
COMPOSITE(CLK_NPU_SRC, "clk_npu_src", mux_gpll_24m_p, 0,
205
+
RV1103B_CLKSEL_CON(37), 0, 1, MFLAGS, 1, 2, DFLAGS,
206
+
RV1103B_CLKGATE_CON(5), 12, GFLAGS),
207
+
COMPOSITE_NODIV(ACLK_VEPU_SRC, "aclk_vepu_src", mux_480m_400m_300m_200m_p, 0,
208
+
RV1103B_CLKSEL_CON(30), 8, 2, MFLAGS,
209
+
RV1103B_CLKGATE_CON(2), 4, GFLAGS),
210
+
COMPOSITE(CLK_VEPU_SRC, "clk_vepu_src", mux_gpll_24m_p, 0,
211
+
RV1103B_CLKSEL_CON(37), 4, 1, MFLAGS, 5, 2, DFLAGS,
212
+
RV1103B_CLKGATE_CON(5), 13, GFLAGS),
213
+
COMPOSITE_NODIV(ACLK_VI_SRC, "aclk_vi_src", mux_480m_400m_300m_p, CLK_IS_CRITICAL,
214
+
RV1103B_CLKSEL_CON(30), 12, 2, MFLAGS,
215
+
RV1103B_CLKGATE_CON(2), 8, GFLAGS),
216
+
COMPOSITE(CLK_ISP_SRC, "clk_isp_src", mux_gpll_24m_p, 0,
217
+
RV1103B_CLKSEL_CON(37), 8, 1, MFLAGS, 9, 2, DFLAGS,
218
+
RV1103B_CLKGATE_CON(5), 14, GFLAGS),
219
+
COMPOSITE_NODIV(DCLK_VICAP, "dclk_vicap", mux_300m_200m_p, 0,
220
+
RV1103B_CLKSEL_CON(30), 14, 1, MFLAGS,
221
+
RV1103B_CLKGATE_CON(2), 9, GFLAGS),
222
+
COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_24m_p, 0,
223
+
RV1103B_CLKSEL_CON(31), 15, 1, MFLAGS, 0, 8, DFLAGS,
224
+
RV1103B_CLKGATE_CON(2), 10, GFLAGS),
225
+
COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_24m_p, 0,
226
+
RV1103B_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 8, DFLAGS,
227
+
RV1103B_CLKGATE_CON(2), 11, GFLAGS),
228
+
COMPOSITE(SCLK_SFC_2X, "sclk_sfc_2x", mux_gpll_24m_p, 0,
229
+
RV1103B_CLKSEL_CON(33), 15, 1, MFLAGS, 0, 8, DFLAGS,
230
+
RV1103B_CLKGATE_CON(2), 12, GFLAGS),
231
+
COMPOSITE_NODIV(LSCLK_PERI_SRC, "lsclk_peri_src", mux_300m_200m_p, CLK_IS_CRITICAL,
232
+
RV1103B_CLKSEL_CON(31), 9, 1, MFLAGS,
233
+
RV1103B_CLKGATE_CON(3), 0, GFLAGS),
234
+
COMPOSITE_NODIV(ACLK_PERI_SRC, "aclk_peri_src", mux_600m_480m_400m_p, CLK_IS_CRITICAL,
235
+
RV1103B_CLKSEL_CON(31), 10, 2, MFLAGS,
236
+
RV1103B_CLKGATE_CON(3), 1, GFLAGS),
237
+
COMPOSITE_NODIV(HCLK_HPMCU, "hclk_hpmcu", mux_400m_300m_p, 0,
238
+
RV1103B_CLKSEL_CON(31), 12, 1, MFLAGS,
239
+
RV1103B_CLKGATE_CON(3), 2, GFLAGS),
240
+
COMPOSITE_NODIV(CLK_I2C_PMU, "clk_i2c_pmu", mux_100m_24m_p, 0,
241
+
RV1103B_CLKSEL_CON(34), 0, 1, MFLAGS,
242
+
RV1103B_CLKGATE_CON(4), 0, GFLAGS),
243
+
COMPOSITE_NODIV(CLK_I2C_PERI, "clk_i2c_peri", mux_200m_24m_p, 0,
244
+
RV1103B_CLKSEL_CON(34), 1, 1, MFLAGS,
245
+
RV1103B_CLKGATE_CON(4), 4, GFLAGS),
246
+
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
247
+
RV1103B_CLKSEL_CON(34), 2, 2, MFLAGS,
248
+
RV1103B_CLKGATE_CON(4), 5, GFLAGS),
249
+
COMPOSITE_NODIV(CLK_PWM0_SRC, "clk_pwm0_src", mux_100m_24m_p, 0,
250
+
RV1103B_CLKSEL_CON(34), 12, 1, MFLAGS,
251
+
RV1103B_CLKGATE_CON(4), 10, GFLAGS),
252
+
COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_24m_p, 0,
253
+
RV1103B_CLKSEL_CON(34), 13, 1, MFLAGS,
254
+
RV1103B_CLKGATE_CON(4), 11, GFLAGS),
255
+
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
256
+
RV1103B_CLKSEL_CON(34), 14, 1, MFLAGS,
257
+
RV1103B_CLKGATE_CON(4), 12, GFLAGS),
258
+
COMPOSITE_NODIV(DCLK_DECOM_SRC, "dclk_decom_src", mux_480m_400m_300m_p, 0,
259
+
RV1103B_CLKSEL_CON(35), 0, 2, MFLAGS,
260
+
RV1103B_CLKGATE_CON(5), 0, GFLAGS),
261
+
COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_24m_p, 0,
262
+
RV1103B_CLKSEL_CON(36), 15, 1, MFLAGS, 0, 8, DFLAGS,
263
+
RV1103B_CLKGATE_CON(5), 1, GFLAGS),
264
+
COMPOSITE_NODIV(CLK_CORE_CRYPTO, "clk_core_crypto", mux_300m_200m_100m_p, 0,
265
+
RV1103B_CLKSEL_CON(35), 2, 2, MFLAGS,
266
+
RV1103B_CLKGATE_CON(5), 2, GFLAGS),
267
+
COMPOSITE_NODIV(CLK_PKA_CRYPTO, "clk_pka_crypto", mux_300m_200m_100m_p, 0,
268
+
RV1103B_CLKSEL_CON(35), 4, 2, MFLAGS,
269
+
RV1103B_CLKGATE_CON(5), 3, GFLAGS),
270
+
COMPOSITE_NODIV(CLK_CORE_RGA, "clk_core_rga", mux_400m_300m_p, 0,
271
+
RV1103B_CLKSEL_CON(35), 8, 1, MFLAGS,
272
+
RV1103B_CLKGATE_CON(5), 4, GFLAGS),
273
+
274
+
GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_gpll_div12", CLK_IS_CRITICAL,
275
+
RV1103B_CLKGATE_CON(6), 0, GFLAGS),
276
+
COMPOSITE_NOMUX(CLK_REF_MIPI0, "clk_ref_mipi0", "clk_gpll_div2", 0,
277
+
RV1103B_CLKSEL_CON(40), 0, 5, DFLAGS,
278
+
RV1103B_CLKGATE_CON(6), 3, GFLAGS),
279
+
COMPOSITE_NODIV(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", clk_mipi0_out2io_p, CLK_SET_RATE_PARENT,
280
+
RV1103B_CLKSEL_CON(40), 6, 1, MFLAGS,
281
+
RV1103B_CLKGATE_CON(6), 4, GFLAGS),
282
+
COMPOSITE_NOMUX(CLK_REF_MIPI1, "clk_ref_mipi1", "clk_gpll_div2", 0,
283
+
RV1103B_CLKSEL_CON(40), 8, 5, DFLAGS,
284
+
RV1103B_CLKGATE_CON(6), 5, GFLAGS),
285
+
COMPOSITE_NODIV(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", clk_mipi1_out2io_p, CLK_SET_RATE_PARENT,
286
+
RV1103B_CLKSEL_CON(40), 14, 1, MFLAGS,
287
+
RV1103B_CLKGATE_CON(6), 6, GFLAGS),
288
+
COMPOSITE(MCLK_SAI_OUT2IO, "mclk_sai_out2io", mclk_sai_out2io_p, 0,
289
+
RV1103B_CLKSEL_CON(41), 7, 1, MFLAGS, 13, 3, DFLAGS,
290
+
RV1103B_CLKGATE_CON(6), 9, GFLAGS),
291
+
292
+
/* pd_vpu */
293
+
COMPOSITE_NODIV(ACLK_NPU_ROOT, "aclk_npu_root", aclk_npu_root_p, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
294
+
RV1103B_NPUCLKSEL_CON(0), 1, 1, MFLAGS,
295
+
RV1103B_NPUCLKGATE_CON(0), 1, GFLAGS),
296
+
GATE(HCLK_RKNN, "hclk_rknn", "lsclk_npu_src", 0,
297
+
RV1103B_NPUCLKGATE_CON(0), 4, GFLAGS),
298
+
GATE(ACLK_RKNN, "aclk_rknn", "aclk_npu_root", 0,
299
+
RV1103B_NPUCLKGATE_CON(0), 5, GFLAGS),
300
+
301
+
/* pd_vepu */
302
+
COMPOSITE_NOMUX(LSCLK_VEPU_ROOT, "lsclk_vepu_root", "aclk_vepu_src", CLK_IS_CRITICAL,
303
+
RV1103B_VEPUCLKSEL_CON(0), 2, 2, DFLAGS,
304
+
RV1103B_VEPUCLKGATE_CON(0), 0, GFLAGS),
305
+
GATE(HCLK_VEPU, "hclk_vepu", "lsclk_vepu_root", 0,
306
+
RV1103B_VEPUCLKGATE_CON(0), 4, GFLAGS),
307
+
GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_src", 0,
308
+
RV1103B_VEPUCLKGATE_CON(0), 5, GFLAGS),
309
+
COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, 0,
310
+
RV1103B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
311
+
RV1103B_VEPUCLKGATE_CON(0), 6, GFLAGS),
312
+
GATE(PCLK_ACODEC, "pclk_acodec", "lsclk_vepu_root", 0,
313
+
RV1103B_VEPUCLKGATE_CON(0), 13, GFLAGS),
314
+
GATE(PCLK_USBPHY, "pclk_usbphy", "lsclk_vepu_root", 0,
315
+
RV1103B_VEPUCLKGATE_CON(0), 14, GFLAGS),
316
+
317
+
/* pd_vi */
318
+
FACTOR(LSCLK_VI_100M, "lsclk_vi_100m", "clk_gpll_div6", 0, 1, 2),
319
+
COMPOSITE_NODIV(LSCLK_VI_ROOT, "lsclk_vi_root", lsclk_vi_root_p, CLK_IS_CRITICAL,
320
+
RV1103B_VICLKSEL_CON(0), 3, 1, MFLAGS,
321
+
RV1103B_VICLKGATE_CON(0), 0, GFLAGS),
322
+
GATE(HCLK_ISP, "hclk_isp", "lsclk_vi_root", 0,
323
+
RV1103B_VICLKGATE_CON(0), 4, GFLAGS),
324
+
GATE(ACLK_ISP, "aclk_isp", "aclk_vi_src", 0,
325
+
RV1103B_VICLKGATE_CON(0), 5, GFLAGS),
326
+
COMPOSITE_NODIV(CLK_CORE_ISP, "clk_core_isp", clk_core_isp_p, 0,
327
+
RV1103B_VICLKSEL_CON(0), 1, 1, MFLAGS,
328
+
RV1103B_VICLKGATE_CON(0), 6, GFLAGS),
329
+
GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_src", 0,
330
+
RV1103B_VICLKGATE_CON(1), 2, GFLAGS),
331
+
GATE(HCLK_VICAP, "hclk_vicap", "lsclk_vi_root", 0,
332
+
RV1103B_VICLKGATE_CON(1), 3, GFLAGS),
333
+
GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp", 0,
334
+
RV1103B_VICLKGATE_CON(1), 8, GFLAGS),
335
+
GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "lsclk_vi_root", 0,
336
+
RV1103B_VICLKGATE_CON(1), 9, GFLAGS),
337
+
GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "lsclk_vi_root", 0,
338
+
RV1103B_VICLKGATE_CON(1), 11, GFLAGS),
339
+
GATE(HCLK_EMMC, "hclk_emmc", "lsclk_vi_root", 0,
340
+
RV1103B_VICLKGATE_CON(1), 13, GFLAGS),
341
+
GATE(HCLK_SFC, "hclk_sfc", "lsclk_vi_root", 0,
342
+
RV1103B_VICLKGATE_CON(1), 14, GFLAGS),
343
+
GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "lsclk_vi_root", 0,
344
+
RV1103B_VICLKGATE_CON(1), 15, GFLAGS),
345
+
GATE(HCLK_SDMMC0, "hclk_sdmmc0", "lsclk_vi_root", 0,
346
+
RV1103B_VICLKGATE_CON(2), 0, GFLAGS),
347
+
GATE(PCLK_CSIPHY, "pclk_csiphy", "lsclk_vi_root", 0,
348
+
RV1103B_VICLKGATE_CON(2), 2, GFLAGS),
349
+
GATE(PCLK_GPIO1, "pclk_gpio1", "lsclk_vi_root", 0,
350
+
RV1103B_VICLKGATE_CON(2), 3, GFLAGS),
351
+
GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
352
+
RV1103B_VICLKGATE_CON(2), 4, GFLAGS),
353
+
354
+
/* pd_ddr */
355
+
GATE(LSCLK_DDR_ROOT, "lsclk_ddr_root", "clk_gpll_div12", CLK_IS_CRITICAL,
356
+
RV1103B_DDRCLKGATE_CON(0), 0, GFLAGS),
357
+
GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
358
+
RV1103B_DDRCLKGATE_CON(0), 4, GFLAGS),
359
+
FACTOR(0, "sclk_ddr", "dpll", 0, 1, 2),
360
+
361
+
/* pd_pmu */
362
+
COMPOSITE(LSCLK_PMU_ROOT, "lsclk_pmu_root", lsclk_pmu_root_p, CLK_IS_CRITICAL,
363
+
RV1103B_PMUCLKSEL_CON(2), 4, 1, MFLAGS, 0, 2, DFLAGS,
364
+
RV1103B_PMUCLKGATE_CON(0), 0, GFLAGS),
365
+
GATE(PCLK_PMU, "pclk_pmu", "lsclk_pmu_root", CLK_IS_CRITICAL,
366
+
RV1103B_PMUCLKGATE_CON(0), 2, GFLAGS),
367
+
MUX(XIN_RC_SRC, "xin_rc_src", xin_rc_div_p, 0,
368
+
RV1103B_PMUCLKSEL_CON(0), 2, 1, MFLAGS),
369
+
COMPOSITE_FRACMUX(XIN_RC_DIV, "xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
370
+
RV1103B_PMUCLKSEL_CON(1), 0,
371
+
RV1103B_PMUCLKGATE_CON(0), 3, GFLAGS,
372
+
&rv1103b_rcdiv_pmu_fracmux),
373
+
GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "lsclk_pmu_root", 0,
374
+
RV1103B_PMUCLKGATE_CON(0), 4, GFLAGS),
375
+
COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", dbclk_pmu_gpio0_p, 0,
376
+
RK3568_PMU_CLKSEL_CON(0), 3, 1, MFLAGS,
377
+
RV1103B_PMUCLKGATE_CON(0), 5, GFLAGS),
378
+
GATE(PCLK_PWM0, "pclk_pwm0", "lsclk_pmu_root", 0,
379
+
RV1103B_PMUCLKGATE_CON(2), 0, GFLAGS),
380
+
GATE(CLK_PWM0, "clk_pwm0", "clk_pwm0_src", 0,
381
+
RV1103B_PMUCLKGATE_CON(2), 1, GFLAGS),
382
+
GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
383
+
RV1103B_PMUCLKGATE_CON(2), 2, GFLAGS),
384
+
GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_32k", 0,
385
+
RV1103B_PMUCLKGATE_CON(2), 3, GFLAGS),
386
+
GATE(PCLK_I2C0, "pclk_i2c0", "lsclk_pmu_root", 0,
387
+
RV1103B_PMUCLKGATE_CON(0), 12, GFLAGS),
388
+
GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_pmu", 0,
389
+
RV1103B_PMUCLKGATE_CON(0), 13, GFLAGS),
390
+
GATE(PCLK_UART0, "pclk_uart0", "lsclk_pmu_root", 0,
391
+
RV1103B_PMUCLKGATE_CON(0), 14, GFLAGS),
392
+
GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
393
+
RV1103B_PMUCLKGATE_CON(1), 4, GFLAGS),
394
+
GATE(CLK_PREROLL, "clk_preroll", "lsclk_pmu_root", 0,
395
+
RV1103B_PMUCLKGATE_CON(1), 6, GFLAGS),
396
+
GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
397
+
RV1103B_PMUCLKGATE_CON(1), 7, GFLAGS),
398
+
GATE(CLK_LPMCU_PMU, "clk_lpmcu_pmu", "lsclk_pmu_root", 0,
399
+
RV1103B_PMUCLKGATE_CON(2), 12, GFLAGS),
400
+
401
+
/* pd_pmu1 */
402
+
GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "lsclk_pmu_root", 0,
403
+
RV1103B_PMU1CLKGATE_CON(0), 0, GFLAGS),
404
+
GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "lsclk_pmu_root", 0,
405
+
RV1103B_PMU1CLKGATE_CON(0), 1, GFLAGS),
406
+
GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "lsclk_pmu_root", 0,
407
+
RV1103B_PMU1CLKGATE_CON(0), 9, GFLAGS),
408
+
GATE(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", "xin24m", 0,
409
+
RV1103B_PMU1CLKGATE_CON(0), 10, GFLAGS),
410
+
GATE(HCLK_SFC_PMU1, "hclk_sfc_pmu1", "lsclk_pmu_root", 0,
411
+
RV1103B_PMU1CLKGATE_CON(0), 12, GFLAGS),
412
+
GATE(HCLK_SFC_XIP_PMU1, "hclk_sfc_xip_pmu1", "lsclk_pmu_root", 0,
413
+
RV1103B_PMU1CLKGATE_CON(0), 13, GFLAGS),
414
+
COMPOSITE_NODIV(SCLK_SFC_2X_PMU1, "sclk_sfc_2x_pmu1", sclk_sfc_2x_pmu1_p, 0,
415
+
RV1103B_PMU1CLKSEL_CON(0), 8, 1, MFLAGS,
416
+
RV1103B_PMU1CLKGATE_CON(0), 14, GFLAGS),
417
+
GATE(CLK_LPMCU, "clk_lpmcu", "lsclk_pmu_root", 0,
418
+
RV1103B_PMU1CLKGATE_CON(1), 0, GFLAGS),
419
+
GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
420
+
RV1103B_PMU1CLKGATE_CON(1), 4, GFLAGS),
421
+
GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "lsclk_pmu_root", 0,
422
+
RV1103B_PMU1CLKGATE_CON(1), 8, GFLAGS),
423
+
424
+
/* pd_peri */
425
+
COMPOSITE_NOMUX(PCLK_PERI_ROOT, "pclk_peri_root", "lsclk_peri_src", CLK_IS_CRITICAL,
426
+
RV1103B_PERICLKSEL_CON(0), 0, 2, DFLAGS,
427
+
RV1103B_PERICLKGATE_CON(0), 0, GFLAGS),
428
+
COMPOSITE_NOMUX(PCLK_RTC_ROOT, "pclk_rtc_root", "lsclk_peri_src", CLK_IS_CRITICAL,
429
+
RV1103B_PERICLKSEL_CON(2), 12, 4, DFLAGS,
430
+
RV1103B_PERICLKGATE_CON(0), 8, GFLAGS),
431
+
GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
432
+
RV1103B_PERICLKGATE_CON(0), 1, GFLAGS),
433
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_peri_root", 0,
434
+
RV1103B_PERICLKGATE_CON(1), 0, GFLAGS),
435
+
GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
436
+
RV1103B_PERICLKGATE_CON(1), 1, GFLAGS),
437
+
GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
438
+
RV1103B_PERICLKGATE_CON(1), 2, GFLAGS),
439
+
GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
440
+
RV1103B_PERICLKGATE_CON(1), 3, GFLAGS),
441
+
GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
442
+
RV1103B_PERICLKGATE_CON(1), 4, GFLAGS),
443
+
GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
444
+
RV1103B_PERICLKGATE_CON(1), 5, GFLAGS),
445
+
GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
446
+
RV1103B_PERICLKGATE_CON(1), 6, GFLAGS),
447
+
GATE(PCLK_STIMER, "pclk_stimer", "pclk_peri_root", 0,
448
+
RV1103B_PERICLKGATE_CON(1), 7, GFLAGS),
449
+
GATE(CLK_STIMER0, "clk_stimer0", "clk_timer_root", 0,
450
+
RV1103B_PERICLKGATE_CON(1), 8, GFLAGS),
451
+
GATE(CLK_STIMER1, "clk_stimer1", "clk_timer_root", 0,
452
+
RV1103B_PERICLKGATE_CON(1), 9, GFLAGS),
453
+
GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_peri_root", 0,
454
+
RV1103B_PERICLKGATE_CON(2), 0, GFLAGS),
455
+
GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
456
+
RV1103B_PERICLKGATE_CON(2), 1, GFLAGS),
457
+
GATE(PCLK_WDT_S, "pclk_wdt_s", "pclk_peri_root", 0,
458
+
RV1103B_PERICLKGATE_CON(2), 2, GFLAGS),
459
+
GATE(TCLK_WDT_S, "tclk_wdt_s", "xin24m", 0,
460
+
RV1103B_PERICLKGATE_CON(2), 3, GFLAGS),
461
+
GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_peri_root", 0,
462
+
RV1103B_PERICLKGATE_CON(2), 4, GFLAGS),
463
+
GATE(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", "xin24m", 0,
464
+
RV1103B_PERICLKGATE_CON(2), 5, GFLAGS),
465
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri_root", 0,
466
+
RV1103B_PERICLKGATE_CON(2), 6, GFLAGS),
467
+
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_peri", 0,
468
+
RV1103B_PERICLKGATE_CON(2), 7, GFLAGS),
469
+
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri_root", 0,
470
+
RV1103B_PERICLKGATE_CON(2), 8, GFLAGS),
471
+
GATE(CLK_I2C2, "clk_i2c2", "clk_i2c_peri", 0,
472
+
RV1103B_PERICLKGATE_CON(2), 9, GFLAGS),
473
+
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri_root", 0,
474
+
RV1103B_PERICLKGATE_CON(2), 10, GFLAGS),
475
+
GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_peri", 0,
476
+
RV1103B_PERICLKGATE_CON(2), 11, GFLAGS),
477
+
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri_root", 0,
478
+
RV1103B_PERICLKGATE_CON(2), 12, GFLAGS),
479
+
GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_peri", 0,
480
+
RV1103B_PERICLKGATE_CON(2), 13, GFLAGS),
481
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri_root", 0,
482
+
RV1103B_PERICLKGATE_CON(3), 10, GFLAGS),
483
+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_peri_root", 0,
484
+
RV1103B_PERICLKGATE_CON(4), 6, GFLAGS),
485
+
GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
486
+
RV1103B_PERICLKGATE_CON(4), 8, GFLAGS),
487
+
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_peri_root", 0,
488
+
RV1103B_PERICLKGATE_CON(4), 12, GFLAGS),
489
+
GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
490
+
RV1103B_PERICLKGATE_CON(4), 13, GFLAGS),
491
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_peri_root", 0,
492
+
RV1103B_PERICLKGATE_CON(3), 0, GFLAGS),
493
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_peri_root", 0,
494
+
RV1103B_PERICLKGATE_CON(3), 2, GFLAGS),
495
+
GATE(ACLK_RKDMA, "aclk_rkdma", "lsclk_peri_src", 0,
496
+
RV1103B_PERICLKGATE_CON(5), 8, GFLAGS),
497
+
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri_root", 0,
498
+
RV1103B_PERICLKGATE_CON(5), 9, GFLAGS),
499
+
COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
500
+
RV1103B_PERICLKSEL_CON(0), 4, 5, DFLAGS,
501
+
RV1103B_PERICLKGATE_CON(5), 10, GFLAGS),
502
+
COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
503
+
RV1103B_PERICLKSEL_CON(0), 10, 5, DFLAGS,
504
+
RV1103B_PERICLKGATE_CON(5), 11, GFLAGS),
505
+
GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri_root", 0,
506
+
RV1103B_PERICLKGATE_CON(5), 12, GFLAGS),
507
+
COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
508
+
RV1103B_PERICLKSEL_CON(1), 0, 3, DFLAGS,
509
+
RV1103B_PERICLKGATE_CON(5), 13, GFLAGS),
510
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri_root", 0,
511
+
RV1103B_PERICLKGATE_CON(6), 3, GFLAGS),
512
+
GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
513
+
RV1103B_PERICLKGATE_CON(6), 4, GFLAGS),
514
+
GATE(ACLK_USBOTG, "aclk_usbotg", "lsclk_peri_src", 0,
515
+
RV1103B_PERICLKGATE_CON(6), 9, GFLAGS),
516
+
GATE(CLK_REF_USBOTG, "clk_ref_usbotg", "xin24m", 0,
517
+
RV1103B_PERICLKGATE_CON(6), 10, GFLAGS),
518
+
GATE(HCLK_SDMMC1, "hclk_sdmmc1", "lsclk_peri_src", 0,
519
+
RV1103B_PERICLKGATE_CON(7), 0, GFLAGS),
520
+
GATE(HCLK_SAI, "hclk_sai", "lsclk_peri_src", 0,
521
+
RV1103B_PERICLKGATE_CON(7), 1, GFLAGS),
522
+
GATE(ACLK_CRYPTO, "aclk_crypto", "lsclk_peri_src", 0,
523
+
RV1103B_PERICLKGATE_CON(8), 2, GFLAGS),
524
+
GATE(HCLK_CRYPTO, "hclk_crypto", "lsclk_peri_src", 0,
525
+
RV1103B_PERICLKGATE_CON(8), 3, GFLAGS),
526
+
GATE(HCLK_RK_RNG_S, "hclk_rk_rng_s", "lsclk_peri_src", 0,
527
+
RV1103B_PERICLKGATE_CON(8), 5, GFLAGS),
528
+
GATE(HCLK_RK_RNG_NS, "hclk_rk_rng_ns", "hclk_rk_rng_s", 0,
529
+
RV1103B_PERICLKGATE_CON(8), 4, GFLAGS),
530
+
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri_root", 0,
531
+
RV1103B_PERICLKGATE_CON(8), 6, GFLAGS),
532
+
GATE(CLK_OTPC_ROOT_NS, "clk_otpc_root_ns", "xin24m", 0,
533
+
RV1103B_PERICLKGATE_CON(8), 7, GFLAGS),
534
+
GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "clk_otpc_root_ns", 0,
535
+
RV1103B_PERICLKGATE_CON(8), 8, GFLAGS),
536
+
COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_otpc_root_ns", 0,
537
+
RV1103B_PERICLKSEL_CON(1), 4, 3, DFLAGS,
538
+
RV1103B_PERICLKGATE_CON(8), 9, GFLAGS),
539
+
GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri_root", 0,
540
+
RV1103B_PERICLKGATE_CON(8), 10, GFLAGS),
541
+
GATE(CLK_OTPC_ROOT_S, "clk_otpc_root_s", "xin24m", 0,
542
+
RV1103B_PERICLKGATE_CON(8), 11, GFLAGS),
543
+
GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "clk_otpc_root_s", 0,
544
+
RV1103B_PERICLKGATE_CON(8), 12, GFLAGS),
545
+
COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "clk_otpc_root_s", 0,
546
+
RV1103B_PERICLKSEL_CON(1), 8, 3, DFLAGS,
547
+
RV1103B_PERICLKGATE_CON(8), 13, GFLAGS),
548
+
GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_peri_root", 0,
549
+
RV1103B_PERICLKGATE_CON(8), 15, GFLAGS),
550
+
GATE(HCLK_RGA, "hclk_rga", "lsclk_peri_src", 0,
551
+
RV1103B_PERICLKGATE_CON(9), 0, GFLAGS),
552
+
GATE(ACLK_RGA, "aclk_rga", "aclk_peri_src", 0,
553
+
RV1103B_PERICLKGATE_CON(9), 1, GFLAGS),
554
+
GATE(ACLK_MAC, "aclk_mac", "lsclk_peri_src", 0,
555
+
RV1103B_PERICLKGATE_CON(9), 3, GFLAGS),
556
+
GATE(PCLK_MAC, "pclk_mac", "pclk_peri_root", 0,
557
+
RV1103B_PERICLKGATE_CON(9), 4, GFLAGS),
558
+
GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
559
+
RV1103B_PERICLKGATE_CON(9), 11, GFLAGS),
560
+
GATE(ACLK_SPINLOCK, "aclk_spinlock", "lsclk_peri_src", 0,
561
+
RV1103B_PERICLKGATE_CON(10), 0, GFLAGS),
562
+
GATE(HCLK_CACHE, "hclk_cache", "hclk_hpmcu", 0,
563
+
RV1103B_PERICLKGATE_CON(10), 1, GFLAGS),
564
+
GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_peri_root", 0,
565
+
RV1103B_PERICLKGATE_CON(10), 2, GFLAGS),
566
+
GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_peri_root", 0,
567
+
RV1103B_PERICLKGATE_CON(10), 3, GFLAGS),
568
+
GATE(CLK_HPMCU, "clk_hpmcu", "hclk_hpmcu", 0,
569
+
RV1103B_PERICLKGATE_CON(10), 4, GFLAGS),
570
+
GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
571
+
RV1103B_PERICLKGATE_CON(10), 8, GFLAGS),
572
+
GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
573
+
RV1103B_PERICLKGATE_CON(11), 0, GFLAGS),
574
+
GATE(ACLK_DECOM, "aclk_decom", "aclk_peri_src", 0,
575
+
RV1103B_PERICLKGATE_CON(11), 1, GFLAGS),
576
+
GATE(PCLK_DECOM, "pclk_decom", "pclk_peri_root", 0,
577
+
RV1103B_PERICLKGATE_CON(11), 2, GFLAGS),
578
+
GATE(ACLK_SYS_SRAM, "aclk_sys_sram", "lsclk_peri_src", CLK_IS_CRITICAL,
579
+
RV1103B_PERICLKGATE_CON(11), 3, GFLAGS),
580
+
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_peri_root", 0,
581
+
RV1103B_PERICLKGATE_CON(11), 4, GFLAGS),
582
+
GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_peri_src", 0,
583
+
RV1103B_PERICLKGATE_CON(11), 5, GFLAGS),
584
+
GATE(PCLK_DCF, "pclk_dcf", "pclk_peri_root", 0,
585
+
RV1103B_PERICLKGATE_CON(11), 6, GFLAGS),
586
+
GATE(ACLK_DCF, "aclk_dcf", "lsclk_peri_src", 0,
587
+
RV1103B_PERICLKGATE_CON(11), 7, GFLAGS),
588
+
COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_sai_src", 0,
589
+
RV1103B_PERICLKSEL_CON(2), 0, 3, DFLAGS,
590
+
RV1103B_PERICLKGATE_CON(11), 9, GFLAGS),
591
+
GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
592
+
RV1103B_PERICLKGATE_CON(11), 12, GFLAGS),
593
+
594
+
/* io */
595
+
COMPOSITE_NODIV(CLK_FREQ_PWM0_SRC, "clk_freq_pwm0_src", clk_freq_pwm0_src_p, 0,
596
+
RV1103B_CLKSEL_CON(35), 12, 2, MFLAGS,
597
+
RV1103B_CLKGATE_CON(5), 6, GFLAGS),
598
+
GATE(CLK_FREQ_PWM0, "clk_freq_pwm0", "clk_freq_pwm0_src", 0,
599
+
RV1103B_PMUCLKGATE_CON(2), 4, GFLAGS),
600
+
COMPOSITE_NODIV(CLK_COUNTER_PWM0_SRC, "clk_counter_pwm0_src", clk_counter_pwm0_src_p, 0,
601
+
RV1103B_CLKSEL_CON(35), 14, 2, MFLAGS,
602
+
RV1103B_CLKGATE_CON(5), 7, GFLAGS),
603
+
GATE(CLK_COUNTER_PWM0, "clk_counter_pwm0", "clk_counter_pwm0_src", 0,
604
+
RV1103B_PMUCLKGATE_CON(2), 5, GFLAGS),
605
+
GATE(SCLK_SPI2AHB, "sclk_spi2ahb", "sclk_spi2ahb_io", 0,
606
+
RV1103B_PMU1CLKGATE_CON(0), 2, GFLAGS),
607
+
GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
608
+
RV1103B_PERICRU_IP_CON, 14, GFLAGS),
609
+
};
610
+
611
+
static struct rockchip_clk_branch rv1103b_armclk __initdata =
612
+
MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
613
+
RV1103B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
614
+
615
+
static void __init rv1103b_clk_init(struct device_node *np)
616
+
{
617
+
struct rockchip_clk_provider *ctx;
618
+
unsigned long clk_nr;
619
+
void __iomem *reg_base;
620
+
621
+
clk_nr = rockchip_clk_find_max_clk_id(rv1103b_clk_branches,
622
+
ARRAY_SIZE(rv1103b_clk_branches)) + 1;
623
+
reg_base = of_iomap(np, 0);
624
+
if (!reg_base) {
625
+
pr_err("%s: could not map cru region\n", __func__);
626
+
return;
627
+
}
628
+
629
+
ctx = rockchip_clk_init(np, reg_base, clk_nr);
630
+
if (IS_ERR(ctx)) {
631
+
pr_err("%s: rockchip clk init failed\n", __func__);
632
+
iounmap(reg_base);
633
+
return;
634
+
}
635
+
636
+
rockchip_clk_register_plls(ctx, rv1103b_pll_clks,
637
+
ARRAY_SIZE(rv1103b_pll_clks),
638
+
RV1103B_GRF_SOC_STATUS0);
639
+
640
+
rockchip_clk_register_branches(ctx, rv1103b_clk_branches,
641
+
ARRAY_SIZE(rv1103b_clk_branches));
642
+
643
+
rockchip_clk_register_armclk_multi_pll(ctx, &rv1103b_armclk,
644
+
rv1103b_cpuclk_rates,
645
+
ARRAY_SIZE(rv1103b_cpuclk_rates));
646
+
647
+
rockchip_register_restart_notifier(ctx, RV1103B_GLB_SRST_FST, NULL);
648
+
649
+
rockchip_clk_of_add_provider(np, ctx);
650
+
651
+
/* pvtpll src init */
652
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_CORECLKSEL_CON(0));
653
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_NPUCLKSEL_CON(0));
654
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VICLKSEL_CON(0));
655
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1103B_VEPUCLKSEL_CON(0));
656
+
}
657
+
658
+
CLK_OF_DECLARE(rv1103b_cru, "rockchip,rv1103b-cru", rv1103b_clk_init);
+49
drivers/clk/rockchip/clk.h
+49
drivers/clk/rockchip/clk.h
···
66
66
#define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
67
67
#define PX30_PMU_MODE 0x0020
68
68
69
+
#define RV1103B_TOPCRU_BASE 0x60000
70
+
#define RV1103B_PERICRU_BASE 0x0
71
+
#define RV1103B_VICRU_BASE 0x30000
72
+
#define RV1103B_NPUCRU_BASE 0x20000
73
+
#define RV1103B_CORECRU_BASE 0x40000
74
+
#define RV1103B_VEPUCRU_BASE 0x10000
75
+
#define RV1103B_DDRCRU_BASE 0x50000
76
+
#define RV1103B_SUBDDRCRU_BASE 0x58000
77
+
#define RV1103B_PMUCRU_BASE 0x70000
78
+
#define RV1103B_PMU1CRU_BASE 0x80000
79
+
80
+
#define RV1103B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMUCRU_BASE)
81
+
#define RV1103B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMUCRU_BASE)
82
+
#define RV1103B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMUCRU_BASE)
83
+
#define RV1103B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PMU1CRU_BASE)
84
+
#define RV1103B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PMU1CRU_BASE)
85
+
#define RV1103B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PMU1CRU_BASE)
86
+
#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
87
+
#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
88
+
#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
89
+
#define RV1103B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_TOPCRU_BASE)
90
+
#define RV1103B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_TOPCRU_BASE)
91
+
#define RV1103B_GLB_SRST_FST (0xc08 + RV1103B_TOPCRU_BASE)
92
+
#define RV1103B_GLB_SRST_SND (0xc0c + RV1103B_TOPCRU_BASE)
93
+
#define RV1103B_CLK_SAI_FRAC_DIV_HIGH (0xcc0 + RV1103B_TOPCRU_BASE)
94
+
#define RV1103B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_PERICRU_BASE)
95
+
#define RV1103B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_PERICRU_BASE)
96
+
#define RV1103B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_PERICRU_BASE)
97
+
#define RV1103B_PERICRU_IP_CON (0xc08 + RV1103B_PERICRU_BASE)
98
+
#define RV1103B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VICRU_BASE)
99
+
#define RV1103B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VICRU_BASE)
100
+
#define RV1103B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VICRU_BASE)
101
+
#define RV1103B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_NPUCRU_BASE)
102
+
#define RV1103B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_NPUCRU_BASE)
103
+
#define RV1103B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_NPUCRU_BASE)
104
+
#define RV1103B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_CORECRU_BASE)
105
+
#define RV1103B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_CORECRU_BASE)
106
+
#define RV1103B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_CORECRU_BASE)
107
+
#define RV1103B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_VEPUCRU_BASE)
108
+
#define RV1103B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_VEPUCRU_BASE)
109
+
#define RV1103B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_VEPUCRU_BASE)
110
+
#define RV1103B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_DDRCRU_BASE)
111
+
#define RV1103B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_DDRCRU_BASE)
112
+
#define RV1103B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_DDRCRU_BASE)
113
+
#define RV1103B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_SUBDDRCRU_BASE)
114
+
#define RV1103B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1103B_SUBDDRCRU_BASE)
115
+
#define RV1103B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1103B_SUBDDRCRU_BASE)
116
+
#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
117
+
69
118
#define RV1108_PLL_CON(x) ((x) * 0x4)
70
119
#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
71
120
#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
+220
include/dt-bindings/clock/rockchip,rv1103b-cru.h
+220
include/dt-bindings/clock/rockchip,rv1103b-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
8
+
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
9
+
10
+
#define PLL_GPLL 0
11
+
#define ARMCLK 1
12
+
#define PLL_DPLL 2
13
+
#define XIN_OSC0_HALF 3
14
+
#define CLK_GPLL_DIV24 4
15
+
#define CLK_GPLL_DIV12 5
16
+
#define CLK_GPLL_DIV6 6
17
+
#define CLK_GPLL_DIV4 7
18
+
#define CLK_GPLL_DIV3 8
19
+
#define CLK_GPLL_DIV2P5 9
20
+
#define CLK_GPLL_DIV2 10
21
+
#define CLK_UART0_SRC 11
22
+
#define CLK_UART1_SRC 12
23
+
#define CLK_UART2_SRC 13
24
+
#define CLK_UART0_FRAC 14
25
+
#define CLK_UART1_FRAC 15
26
+
#define CLK_UART2_FRAC 16
27
+
#define CLK_SAI_SRC 17
28
+
#define CLK_SAI_FRAC 18
29
+
#define LSCLK_NPU_SRC 19
30
+
#define CLK_NPU_SRC 20
31
+
#define ACLK_VEPU_SRC 21
32
+
#define CLK_VEPU_SRC 22
33
+
#define ACLK_VI_SRC 23
34
+
#define CLK_ISP_SRC 24
35
+
#define DCLK_VICAP 25
36
+
#define CCLK_EMMC 26
37
+
#define CCLK_SDMMC0 27
38
+
#define SCLK_SFC_2X 28
39
+
#define LSCLK_PERI_SRC 29
40
+
#define ACLK_PERI_SRC 30
41
+
#define HCLK_HPMCU 31
42
+
#define SCLK_UART0 32
43
+
#define SCLK_UART1 33
44
+
#define SCLK_UART2 34
45
+
#define CLK_I2C_PMU 35
46
+
#define CLK_I2C_PERI 36
47
+
#define CLK_SPI0 37
48
+
#define CLK_PWM0_SRC 38
49
+
#define CLK_PWM1 39
50
+
#define CLK_PWM2 40
51
+
#define DCLK_DECOM_SRC 41
52
+
#define CCLK_SDMMC1 42
53
+
#define CLK_CORE_CRYPTO 43
54
+
#define CLK_PKA_CRYPTO 44
55
+
#define CLK_CORE_RGA 45
56
+
#define MCLK_SAI_SRC 46
57
+
#define CLK_FREQ_PWM0_SRC 47
58
+
#define CLK_COUNTER_PWM0_SRC 48
59
+
#define PCLK_TOP_ROOT 49
60
+
#define CLK_REF_MIPI0 50
61
+
#define CLK_MIPI0_OUT2IO 51
62
+
#define CLK_REF_MIPI1 52
63
+
#define CLK_MIPI1_OUT2IO 53
64
+
#define MCLK_SAI_OUT2IO 54
65
+
#define ACLK_NPU_ROOT 55
66
+
#define HCLK_RKNN 56
67
+
#define ACLK_RKNN 57
68
+
#define LSCLK_VEPU_ROOT 58
69
+
#define HCLK_VEPU 59
70
+
#define ACLK_VEPU 60
71
+
#define CLK_CORE_VEPU 61
72
+
#define PCLK_IOC_VCCIO3 62
73
+
#define PCLK_ACODEC 63
74
+
#define PCLK_USBPHY 64
75
+
#define LSCLK_VI_100M 65
76
+
#define LSCLK_VI_ROOT 66
77
+
#define HCLK_ISP 67
78
+
#define ACLK_ISP 68
79
+
#define CLK_CORE_ISP 69
80
+
#define ACLK_VICAP 70
81
+
#define HCLK_VICAP 71
82
+
#define ISP0CLK_VICAP 72
83
+
#define PCLK_CSI2HOST0 73
84
+
#define PCLK_CSI2HOST1 74
85
+
#define HCLK_EMMC 75
86
+
#define HCLK_SFC 76
87
+
#define HCLK_SFC_XIP 77
88
+
#define HCLK_SDMMC0 78
89
+
#define PCLK_CSIPHY 79
90
+
#define PCLK_GPIO1 80
91
+
#define DBCLK_GPIO1 81
92
+
#define PCLK_IOC_VCCIO47 82
93
+
#define LSCLK_DDR_ROOT 83
94
+
#define CLK_TIMER_DDRMON 84
95
+
#define LSCLK_PMU_ROOT 85
96
+
#define PCLK_PMU 86
97
+
#define XIN_RC_DIV 87
98
+
#define CLK_32K 88
99
+
#define PCLK_PMU_GPIO0 89
100
+
#define DBCLK_PMU_GPIO0 90
101
+
#define CLK_DDR_FAIL_SAFE 91
102
+
#define PCLK_PMU_HP_TIMER 92
103
+
#define CLK_PMU_32K_HP_TIMER 93
104
+
#define PCLK_PWM0 94
105
+
#define CLK_PWM0 95
106
+
#define CLK_OSC_PWM0 96
107
+
#define CLK_RC_PWM0 97
108
+
#define CLK_FREQ_PWM0 98
109
+
#define CLK_COUNTER_PWM0 99
110
+
#define PCLK_I2C0 100
111
+
#define CLK_I2C0 101
112
+
#define PCLK_UART0 102
113
+
#define PCLK_IOC_PMUIO0 103
114
+
#define CLK_REFOUT 104
115
+
#define CLK_PREROLL 105
116
+
#define CLK_PREROLL_32K 106
117
+
#define CLK_LPMCU_PMU 107
118
+
#define PCLK_SPI2AHB 108
119
+
#define HCLK_SPI2AHB 109
120
+
#define SCLK_SPI2AHB 110
121
+
#define PCLK_WDT_LPMCU 111
122
+
#define TCLK_WDT_LPMCU 112
123
+
#define HCLK_SFC_PMU1 113
124
+
#define HCLK_SFC_XIP_PMU1 114
125
+
#define SCLK_SFC_2X_PMU1 115
126
+
#define CLK_LPMCU 116
127
+
#define CLK_LPMCU_RTC 117
128
+
#define PCLK_LPMCU_MAILBOX 118
129
+
#define PCLK_IOC_PMUIO1 119
130
+
#define PCLK_CRU_PMU1 120
131
+
#define PCLK_PERI_ROOT 121
132
+
#define PCLK_RTC_ROOT 122
133
+
#define CLK_TIMER_ROOT 123
134
+
#define PCLK_TIMER 124
135
+
#define CLK_TIMER0 125
136
+
#define CLK_TIMER1 126
137
+
#define CLK_TIMER2 127
138
+
#define CLK_TIMER3 128
139
+
#define CLK_TIMER4 129
140
+
#define CLK_TIMER5 130
141
+
#define PCLK_STIMER 131
142
+
#define CLK_STIMER0 132
143
+
#define CLK_STIMER1 133
144
+
#define PCLK_WDT_NS 134
145
+
#define TCLK_WDT_NS 135
146
+
#define PCLK_WDT_S 136
147
+
#define TCLK_WDT_S 137
148
+
#define PCLK_WDT_HPMCU 138
149
+
#define TCLK_WDT_HPMCU 139
150
+
#define PCLK_I2C1 140
151
+
#define CLK_I2C1 141
152
+
#define PCLK_I2C2 142
153
+
#define CLK_I2C2 143
154
+
#define PCLK_I2C3 144
155
+
#define CLK_I2C3 145
156
+
#define PCLK_I2C4 146
157
+
#define CLK_I2C4 147
158
+
#define PCLK_SPI0 148
159
+
#define PCLK_PWM1 149
160
+
#define CLK_OSC_PWM1 150
161
+
#define PCLK_PWM2 151
162
+
#define CLK_OSC_PWM2 152
163
+
#define PCLK_UART2 153
164
+
#define PCLK_UART1 154
165
+
#define ACLK_RKDMA 155
166
+
#define PCLK_TSADC 156
167
+
#define CLK_TSADC 157
168
+
#define CLK_TSADC_TSEN 158
169
+
#define PCLK_SARADC 159
170
+
#define CLK_SARADC 160
171
+
#define PCLK_GPIO2 161
172
+
#define DBCLK_GPIO2 162
173
+
#define PCLK_IOC_VCCIO6 163
174
+
#define ACLK_USBOTG 164
175
+
#define CLK_REF_USBOTG 165
176
+
#define HCLK_SDMMC1 166
177
+
#define HCLK_SAI 167
178
+
#define MCLK_SAI 168
179
+
#define ACLK_CRYPTO 169
180
+
#define HCLK_CRYPTO 170
181
+
#define HCLK_RK_RNG_NS 171
182
+
#define HCLK_RK_RNG_S 172
183
+
#define PCLK_OTPC_NS 173
184
+
#define CLK_OTPC_ROOT_NS 174
185
+
#define CLK_SBPI_OTPC_NS 175
186
+
#define CLK_USER_OTPC_NS 176
187
+
#define PCLK_OTPC_S 177
188
+
#define CLK_OTPC_ROOT_S 178
189
+
#define CLK_SBPI_OTPC_S 179
190
+
#define CLK_USER_OTPC_S 180
191
+
#define CLK_OTPC_ARB 181
192
+
#define PCLK_OTP_MASK 182
193
+
#define HCLK_RGA 183
194
+
#define ACLK_RGA 184
195
+
#define ACLK_MAC 185
196
+
#define PCLK_MAC 186
197
+
#define CLK_MACPHY 187
198
+
#define ACLK_SPINLOCK 188
199
+
#define HCLK_CACHE 189
200
+
#define PCLK_HPMCU_MAILBOX 190
201
+
#define PCLK_HPMCU_INTMUX 191
202
+
#define CLK_HPMCU 192
203
+
#define CLK_HPMCU_RTC 193
204
+
#define DCLK_DECOM 194
205
+
#define ACLK_DECOM 195
206
+
#define PCLK_DECOM 196
207
+
#define ACLK_SYS_SRAM 197
208
+
#define PCLK_DMA2DDR 198
209
+
#define ACLK_DMA2DDR 199
210
+
#define PCLK_DCF 200
211
+
#define ACLK_DCF 201
212
+
#define MCLK_ACODEC_TX 202
213
+
#define SCLK_UART0_SRC 203
214
+
#define SCLK_UART1_SRC 204
215
+
#define SCLK_UART2_SRC 205
216
+
#define XIN_RC_SRC 206
217
+
#define CLK_UTMI_USBOTG 207
218
+
#define CLK_REF_USBPHY 208
219
+
220
+
#endif // _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H