tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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dt-bindings: clock: Add Qualcomm SA8775P GCC

Add DT bindings for the GCC clock on SA8775P platforms. Add relevant
DT include definitions as well.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230117180429.305266-2-brgl@bgdev.pl

authored by

Bartosz Golaszewski and committed by
Bjorn Andersson 0fff9fa0 d03de417

+399
+79
Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on sa8775p 8 + 9 + maintainers: 10 + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> 11 + 12 + description: | 13 + Qualcomm global clock control module provides the clocks, resets and 14 + power domains on sa8775p. 15 + 16 + See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h 17 + 18 + properties: 19 + compatible: 20 + const: qcom,sa8775p-gcc 21 + 22 + clocks: 23 + items: 24 + - description: XO reference clock 25 + - description: Sleep clock 26 + - description: UFS memory first RX symbol clock 27 + - description: UFS memory second RX symbol clock 28 + - description: UFS memory first TX symbol clock 29 + - description: UFS card first RX symbol clock 30 + - description: UFS card second RX symbol clock 31 + - description: UFS card first TX symbol clock 32 + - description: Primary USB3 PHY wrapper pipe clock 33 + - description: Secondary USB3 PHY wrapper pipe clock 34 + - description: PCIe 0 pipe clock 35 + - description: PCIe 1 pipe clock 36 + - description: PCIe PHY clock 37 + - description: First EMAC controller reference clock 38 + - description: Second EMAC controller reference clock 39 + 40 + protected-clocks: 41 + maxItems: 240 42 + 43 + required: 44 + - compatible 45 + - clocks 46 + 47 + allOf: 48 + - $ref: qcom,gcc.yaml# 49 + 50 + unevaluatedProperties: false 51 + 52 + examples: 53 + - | 54 + #include <dt-bindings/clock/qcom,rpmh.h> 55 + 56 + gcc: clock-controller@100000 { 57 + compatible = "qcom,sa8775p-gcc"; 58 + reg = <0x100000 0xc7018>; 59 + clocks = <&rpmhcc RPMH_CXO_CLK>, 60 + <&sleep_clk>, 61 + <&ufs_phy_rx_symbol_0_clk>, 62 + <&ufs_phy_rx_symbol_1_clk>, 63 + <&ufs_phy_tx_symbol_0_clk>, 64 + <&ufs_card_rx_symbol_0_clk>, 65 + <&ufs_card_rx_symbol_1_clk>, 66 + <&ufs_card_tx_symbol_0_clk>, 67 + <&usb_0_ssphy>, 68 + <&usb_1_ssphy>, 69 + <&pcie_0_pipe_clk>, 70 + <&pcie_1_pipe_clk>, 71 + <&pcie_phy_pipe_clk>, 72 + <&rxc0_ref_clk>, 73 + <&rxc1_ref_clk>; 74 + 75 + #clock-cells = <1>; 76 + #reset-cells = <1>; 77 + #power-domain-cells = <1>; 78 + }; 79 + ...
+320
include/dt-bindings/clock/qcom,sa8775p-gcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 + * Copyright (c) 2023, Linaro Limited 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H 8 + #define _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H 9 + 10 + /* GCC clocks */ 11 + #define GCC_GPLL0 0 12 + #define GCC_GPLL0_OUT_EVEN 1 13 + #define GCC_GPLL1 2 14 + #define GCC_GPLL4 3 15 + #define GCC_GPLL5 4 16 + #define GCC_GPLL7 5 17 + #define GCC_GPLL9 6 18 + #define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7 19 + #define GCC_AGGRE_UFS_CARD_AXI_CLK 8 20 + #define GCC_AGGRE_UFS_PHY_AXI_CLK 9 21 + #define GCC_AGGRE_USB2_PRIM_AXI_CLK 10 22 + #define GCC_AGGRE_USB3_PRIM_AXI_CLK 11 23 + #define GCC_AGGRE_USB3_SEC_AXI_CLK 12 24 + #define GCC_AHB2PHY0_CLK 13 25 + #define GCC_AHB2PHY2_CLK 14 26 + #define GCC_AHB2PHY3_CLK 15 27 + #define GCC_BOOT_ROM_AHB_CLK 16 28 + #define GCC_CAMERA_AHB_CLK 17 29 + #define GCC_CAMERA_HF_AXI_CLK 18 30 + #define GCC_CAMERA_SF_AXI_CLK 19 31 + #define GCC_CAMERA_THROTTLE_XO_CLK 20 32 + #define GCC_CAMERA_XO_CLK 21 33 + #define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22 34 + #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 35 + #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 36 + #define GCC_DDRSS_GPU_AXI_CLK 25 37 + #define GCC_DISP1_AHB_CLK 26 38 + #define GCC_DISP1_HF_AXI_CLK 27 39 + #define GCC_DISP1_XO_CLK 28 40 + #define GCC_DISP_AHB_CLK 29 41 + #define GCC_DISP_HF_AXI_CLK 30 42 + #define GCC_DISP_XO_CLK 31 43 + #define GCC_EDP_REF_CLKREF_EN 32 44 + #define GCC_EMAC0_AXI_CLK 33 45 + #define GCC_EMAC0_PHY_AUX_CLK 34 46 + #define GCC_EMAC0_PHY_AUX_CLK_SRC 35 47 + #define GCC_EMAC0_PTP_CLK 36 48 + #define GCC_EMAC0_PTP_CLK_SRC 37 49 + #define GCC_EMAC0_RGMII_CLK 38 50 + #define GCC_EMAC0_RGMII_CLK_SRC 39 51 + #define GCC_EMAC0_SLV_AHB_CLK 40 52 + #define GCC_EMAC1_AXI_CLK 41 53 + #define GCC_EMAC1_PHY_AUX_CLK 42 54 + #define GCC_EMAC1_PHY_AUX_CLK_SRC 43 55 + #define GCC_EMAC1_PTP_CLK 44 56 + #define GCC_EMAC1_PTP_CLK_SRC 45 57 + #define GCC_EMAC1_RGMII_CLK 46 58 + #define GCC_EMAC1_RGMII_CLK_SRC 47 59 + #define GCC_EMAC1_SLV_AHB_CLK 48 60 + #define GCC_GP1_CLK 49 61 + #define GCC_GP1_CLK_SRC 50 62 + #define GCC_GP2_CLK 51 63 + #define GCC_GP2_CLK_SRC 52 64 + #define GCC_GP3_CLK 53 65 + #define GCC_GP3_CLK_SRC 54 66 + #define GCC_GP4_CLK 55 67 + #define GCC_GP4_CLK_SRC 56 68 + #define GCC_GP5_CLK 57 69 + #define GCC_GP5_CLK_SRC 58 70 + #define GCC_GPU_CFG_AHB_CLK 59 71 + #define GCC_GPU_GPLL0_CLK_SRC 60 72 + #define GCC_GPU_GPLL0_DIV_CLK_SRC 61 73 + #define GCC_GPU_MEMNOC_GFX_CLK 62 74 + #define GCC_GPU_SNOC_DVM_GFX_CLK 63 75 + #define GCC_GPU_TCU_THROTTLE_AHB_CLK 64 76 + #define GCC_GPU_TCU_THROTTLE_CLK 65 77 + #define GCC_PCIE_0_AUX_CLK 66 78 + #define GCC_PCIE_0_AUX_CLK_SRC 67 79 + #define GCC_PCIE_0_CFG_AHB_CLK 68 80 + #define GCC_PCIE_0_MSTR_AXI_CLK 69 81 + #define GCC_PCIE_0_PHY_AUX_CLK 70 82 + #define GCC_PCIE_0_PHY_AUX_CLK_SRC 71 83 + #define GCC_PCIE_0_PHY_RCHNG_CLK 72 84 + #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73 85 + #define GCC_PCIE_0_PIPE_CLK 74 86 + #define GCC_PCIE_0_PIPE_CLK_SRC 75 87 + #define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76 88 + #define GCC_PCIE_0_PIPEDIV2_CLK 77 89 + #define GCC_PCIE_0_SLV_AXI_CLK 78 90 + #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79 91 + #define GCC_PCIE_1_AUX_CLK 80 92 + #define GCC_PCIE_1_AUX_CLK_SRC 81 93 + #define GCC_PCIE_1_CFG_AHB_CLK 82 94 + #define GCC_PCIE_1_MSTR_AXI_CLK 83 95 + #define GCC_PCIE_1_PHY_AUX_CLK 84 96 + #define GCC_PCIE_1_PHY_AUX_CLK_SRC 85 97 + #define GCC_PCIE_1_PHY_RCHNG_CLK 86 98 + #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87 99 + #define GCC_PCIE_1_PIPE_CLK 88 100 + #define GCC_PCIE_1_PIPE_CLK_SRC 89 101 + #define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90 102 + #define GCC_PCIE_1_PIPEDIV2_CLK 91 103 + #define GCC_PCIE_1_SLV_AXI_CLK 92 104 + #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93 105 + #define GCC_PCIE_CLKREF_EN 94 106 + #define GCC_PCIE_THROTTLE_CFG_CLK 95 107 + #define GCC_PDM2_CLK 96 108 + #define GCC_PDM2_CLK_SRC 97 109 + #define GCC_PDM_AHB_CLK 98 110 + #define GCC_PDM_XO4_CLK 99 111 + #define GCC_QMIP_CAMERA_NRT_AHB_CLK 100 112 + #define GCC_QMIP_CAMERA_RT_AHB_CLK 101 113 + #define GCC_QMIP_DISP1_AHB_CLK 102 114 + #define GCC_QMIP_DISP1_ROT_AHB_CLK 103 115 + #define GCC_QMIP_DISP_AHB_CLK 104 116 + #define GCC_QMIP_DISP_ROT_AHB_CLK 105 117 + #define GCC_QMIP_VIDEO_CVP_AHB_CLK 106 118 + #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107 119 + #define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108 120 + #define GCC_QUPV3_WRAP0_CORE_2X_CLK 109 121 + #define GCC_QUPV3_WRAP0_CORE_CLK 110 122 + #define GCC_QUPV3_WRAP0_S0_CLK 111 123 + #define GCC_QUPV3_WRAP0_S0_CLK_SRC 112 124 + #define GCC_QUPV3_WRAP0_S1_CLK 113 125 + #define GCC_QUPV3_WRAP0_S1_CLK_SRC 114 126 + #define GCC_QUPV3_WRAP0_S2_CLK 115 127 + #define GCC_QUPV3_WRAP0_S2_CLK_SRC 116 128 + #define GCC_QUPV3_WRAP0_S3_CLK 117 129 + #define GCC_QUPV3_WRAP0_S3_CLK_SRC 118 130 + #define GCC_QUPV3_WRAP0_S4_CLK 119 131 + #define GCC_QUPV3_WRAP0_S4_CLK_SRC 120 132 + #define GCC_QUPV3_WRAP0_S5_CLK 121 133 + #define GCC_QUPV3_WRAP0_S5_CLK_SRC 122 134 + #define GCC_QUPV3_WRAP0_S6_CLK 123 135 + #define GCC_QUPV3_WRAP0_S6_CLK_SRC 124 136 + #define GCC_QUPV3_WRAP1_CORE_2X_CLK 125 137 + #define GCC_QUPV3_WRAP1_CORE_CLK 126 138 + #define GCC_QUPV3_WRAP1_S0_CLK 127 139 + #define GCC_QUPV3_WRAP1_S0_CLK_SRC 128 140 + #define GCC_QUPV3_WRAP1_S1_CLK 129 141 + #define GCC_QUPV3_WRAP1_S1_CLK_SRC 130 142 + #define GCC_QUPV3_WRAP1_S2_CLK 131 143 + #define GCC_QUPV3_WRAP1_S2_CLK_SRC 132 144 + #define GCC_QUPV3_WRAP1_S3_CLK 133 145 + #define GCC_QUPV3_WRAP1_S3_CLK_SRC 134 146 + #define GCC_QUPV3_WRAP1_S4_CLK 135 147 + #define GCC_QUPV3_WRAP1_S4_CLK_SRC 136 148 + #define GCC_QUPV3_WRAP1_S5_CLK 137 149 + #define GCC_QUPV3_WRAP1_S5_CLK_SRC 138 150 + #define GCC_QUPV3_WRAP1_S6_CLK 139 151 + #define GCC_QUPV3_WRAP1_S6_CLK_SRC 140 152 + #define GCC_QUPV3_WRAP2_CORE_2X_CLK 141 153 + #define GCC_QUPV3_WRAP2_CORE_CLK 142 154 + #define GCC_QUPV3_WRAP2_S0_CLK 143 155 + #define GCC_QUPV3_WRAP2_S0_CLK_SRC 144 156 + #define GCC_QUPV3_WRAP2_S1_CLK 145 157 + #define GCC_QUPV3_WRAP2_S1_CLK_SRC 146 158 + #define GCC_QUPV3_WRAP2_S2_CLK 147 159 + #define GCC_QUPV3_WRAP2_S2_CLK_SRC 148 160 + #define GCC_QUPV3_WRAP2_S3_CLK 149 161 + #define GCC_QUPV3_WRAP2_S3_CLK_SRC 150 162 + #define GCC_QUPV3_WRAP2_S4_CLK 151 163 + #define GCC_QUPV3_WRAP2_S4_CLK_SRC 152 164 + #define GCC_QUPV3_WRAP2_S5_CLK 153 165 + #define GCC_QUPV3_WRAP2_S5_CLK_SRC 154 166 + #define GCC_QUPV3_WRAP2_S6_CLK 155 167 + #define GCC_QUPV3_WRAP2_S6_CLK_SRC 156 168 + #define GCC_QUPV3_WRAP3_CORE_2X_CLK 157 169 + #define GCC_QUPV3_WRAP3_CORE_CLK 158 170 + #define GCC_QUPV3_WRAP3_QSPI_CLK 159 171 + #define GCC_QUPV3_WRAP3_S0_CLK 160 172 + #define GCC_QUPV3_WRAP3_S0_CLK_SRC 161 173 + #define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162 174 + #define GCC_QUPV3_WRAP_0_M_AHB_CLK 163 175 + #define GCC_QUPV3_WRAP_0_S_AHB_CLK 164 176 + #define GCC_QUPV3_WRAP_1_M_AHB_CLK 165 177 + #define GCC_QUPV3_WRAP_1_S_AHB_CLK 166 178 + #define GCC_QUPV3_WRAP_2_M_AHB_CLK 167 179 + #define GCC_QUPV3_WRAP_2_S_AHB_CLK 168 180 + #define GCC_QUPV3_WRAP_3_M_AHB_CLK 169 181 + #define GCC_QUPV3_WRAP_3_S_AHB_CLK 170 182 + #define GCC_SDCC1_AHB_CLK 171 183 + #define GCC_SDCC1_APPS_CLK 172 184 + #define GCC_SDCC1_APPS_CLK_SRC 173 185 + #define GCC_SDCC1_ICE_CORE_CLK 174 186 + #define GCC_SDCC1_ICE_CORE_CLK_SRC 175 187 + #define GCC_SGMI_CLKREF_EN 176 188 + #define GCC_TSCSS_AHB_CLK 177 189 + #define GCC_TSCSS_CNTR_CLK_SRC 178 190 + #define GCC_TSCSS_ETU_CLK 179 191 + #define GCC_TSCSS_GLOBAL_CNTR_CLK 180 192 + #define GCC_UFS_CARD_AHB_CLK 181 193 + #define GCC_UFS_CARD_AXI_CLK 182 194 + #define GCC_UFS_CARD_AXI_CLK_SRC 183 195 + #define GCC_UFS_CARD_ICE_CORE_CLK 184 196 + #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185 197 + #define GCC_UFS_CARD_PHY_AUX_CLK 186 198 + #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187 199 + #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188 200 + #define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189 201 + #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190 202 + #define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191 203 + #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192 204 + #define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193 205 + #define GCC_UFS_CARD_UNIPRO_CORE_CLK 194 206 + #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195 207 + #define GCC_UFS_PHY_AHB_CLK 196 208 + #define GCC_UFS_PHY_AXI_CLK 197 209 + #define GCC_UFS_PHY_AXI_CLK_SRC 198 210 + #define GCC_UFS_PHY_ICE_CORE_CLK 199 211 + #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200 212 + #define GCC_UFS_PHY_PHY_AUX_CLK 201 213 + #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202 214 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203 215 + #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204 216 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205 217 + #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206 218 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207 219 + #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208 220 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK 209 221 + #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210 222 + #define GCC_USB20_MASTER_CLK 211 223 + #define GCC_USB20_MASTER_CLK_SRC 212 224 + #define GCC_USB20_MOCK_UTMI_CLK 213 225 + #define GCC_USB20_MOCK_UTMI_CLK_SRC 214 226 + #define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215 227 + #define GCC_USB20_SLEEP_CLK 216 228 + #define GCC_USB30_PRIM_MASTER_CLK 217 229 + #define GCC_USB30_PRIM_MASTER_CLK_SRC 218 230 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK 219 231 + #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220 232 + #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221 233 + #define GCC_USB30_PRIM_SLEEP_CLK 222 234 + #define GCC_USB30_SEC_MASTER_CLK 223 235 + #define GCC_USB30_SEC_MASTER_CLK_SRC 224 236 + #define GCC_USB30_SEC_MOCK_UTMI_CLK 225 237 + #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226 238 + #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227 239 + #define GCC_USB30_SEC_SLEEP_CLK 228 240 + #define GCC_USB3_PRIM_PHY_AUX_CLK 229 241 + #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230 242 + #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231 243 + #define GCC_USB3_PRIM_PHY_PIPE_CLK 232 244 + #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233 245 + #define GCC_USB3_SEC_PHY_AUX_CLK 234 246 + #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235 247 + #define GCC_USB3_SEC_PHY_COM_AUX_CLK 236 248 + #define GCC_USB3_SEC_PHY_PIPE_CLK 237 249 + #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238 250 + #define GCC_USB_CLKREF_EN 239 251 + #define GCC_VIDEO_AHB_CLK 240 252 + #define GCC_VIDEO_AXI0_CLK 241 253 + #define GCC_VIDEO_AXI1_CLK 242 254 + #define GCC_VIDEO_XO_CLK 243 255 + #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244 256 + #define GCC_UFS_PHY_AXI_HW_CTL_CLK 245 257 + #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246 258 + #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247 259 + #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248 260 + 261 + /* GCC resets */ 262 + #define GCC_CAMERA_BCR 0 263 + #define GCC_DISPLAY1_BCR 1 264 + #define GCC_DISPLAY_BCR 2 265 + #define GCC_EMAC0_BCR 3 266 + #define GCC_EMAC1_BCR 4 267 + #define GCC_GPU_BCR 5 268 + #define GCC_MMSS_BCR 6 269 + #define GCC_PCIE_0_BCR 7 270 + #define GCC_PCIE_0_LINK_DOWN_BCR 8 271 + #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 9 272 + #define GCC_PCIE_0_PHY_BCR 10 273 + #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 11 274 + #define GCC_PCIE_1_BCR 12 275 + #define GCC_PCIE_1_LINK_DOWN_BCR 13 276 + #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 14 277 + #define GCC_PCIE_1_PHY_BCR 15 278 + #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 16 279 + #define GCC_PDM_BCR 17 280 + #define GCC_QUPV3_WRAPPER_0_BCR 18 281 + #define GCC_QUPV3_WRAPPER_1_BCR 19 282 + #define GCC_QUPV3_WRAPPER_2_BCR 20 283 + #define GCC_QUPV3_WRAPPER_3_BCR 21 284 + #define GCC_SDCC1_BCR 22 285 + #define GCC_TSCSS_BCR 23 286 + #define GCC_UFS_CARD_BCR 24 287 + #define GCC_UFS_PHY_BCR 25 288 + #define GCC_USB20_PRIM_BCR 26 289 + #define GCC_USB2_PHY_PRIM_BCR 27 290 + #define GCC_USB2_PHY_SEC_BCR 28 291 + #define GCC_USB30_PRIM_BCR 29 292 + #define GCC_USB30_SEC_BCR 30 293 + #define GCC_USB3_DP_PHY_PRIM_BCR 31 294 + #define GCC_USB3_DP_PHY_SEC_BCR 32 295 + #define GCC_USB3_PHY_PRIM_BCR 33 296 + #define GCC_USB3_PHY_SEC_BCR 34 297 + #define GCC_USB3_PHY_TERT_BCR 35 298 + #define GCC_USB3_UNIPHY_MP0_BCR 36 299 + #define GCC_USB3_UNIPHY_MP1_BCR 37 300 + #define GCC_USB3PHY_PHY_PRIM_BCR 38 301 + #define GCC_USB3PHY_PHY_SEC_BCR 39 302 + #define GCC_USB3UNIPHY_PHY_MP0_BCR 40 303 + #define GCC_USB3UNIPHY_PHY_MP1_BCR 41 304 + #define GCC_USB_PHY_CFG_AHB2PHY_BCR 42 305 + #define GCC_VIDEO_BCR 43 306 + #define GCC_VIDEO_AXI0_CLK_ARES 44 307 + #define GCC_VIDEO_AXI1_CLK_ARES 45 308 + 309 + /* GCC GDSCs */ 310 + #define PCIE_0_GDSC 0 311 + #define PCIE_1_GDSC 1 312 + #define UFS_CARD_GDSC 2 313 + #define UFS_PHY_GDSC 3 314 + #define USB20_PRIM_GDSC 4 315 + #define USB30_PRIM_GDSC 5 316 + #define USB30_SEC_GDSC 6 317 + #define EMAC0_GDSC 7 318 + #define EMAC1_GDSC 8 319 + 320 + #endif /* _DT_BINDINGS_CLK_QCOM_GCC_SA8775P_H */