tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branches 'pm-cpuidle' and 'pm-powercap'

Merge cpuidle and power capping changes for 6.18-rc1:

- Fail cpuidle device registration if there is one already to avoid
sysfs-related issues (Rafael Wysocki)

- Use sysfs_emit()/sysfs_emit_at() instead of sprintf()/scnprintf() in
cpuidle (Vivek Yadav)

- Fix device and OF node leaks at probe in the qcom-spm cpuidle driver
and drop unnecessary initialisations from it (Johan Hovold)

- Remove unnecessary address-of operators from the intel_idle cpuidle
driver (Kaushlendra Kumar)

- Rearrange main loop in menu_select() to make the code in that funtion
easier to follow (Rafael Wysocki)

- Convert values in microseconds to ktime using us_to_ktime() where
applicable in the intel_idle power capping driver (Xichao Zhao)

* pm-cpuidle:
cpuidle: Fail cpuidle device registration if there is one already
cpuidle: sysfs: Use sysfs_emit()/sysfs_emit_at() instead of sprintf()/scnprintf()
cpuidle: qcom-spm: drop unnecessary initialisations
cpuidle: qcom-spm: fix device and OF node leaks at probe
intel_idle: Remove unnecessary address-of operators
cpuidle: governors: menu: Rearrange main loop in menu_select()

* pm-powercap:
powercap: idle_inject: use us_to_ktime() where appropriate

Rafael J. Wysocki 101642e4 d6fd599c

+200 -190
+7 -4
drivers/cpuidle/cpuidle-qcom-spm.c
··· 86 86 87 87 static int spm_cpuidle_register(struct device *cpuidle_dev, int cpu) 88 88 { 89 - struct platform_device *pdev = NULL; 89 + struct platform_device *pdev; 90 90 struct device_node *cpu_node, *saw_node; 91 - struct cpuidle_qcom_spm_data *data = NULL; 91 + struct cpuidle_qcom_spm_data *data; 92 92 int ret; 93 93 94 94 cpu_node = of_cpu_device_node_get(cpu); ··· 96 96 return -ENODEV; 97 97 98 98 saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); 99 + of_node_put(cpu_node); 99 100 if (!saw_node) 100 101 return -ENODEV; 101 102 102 103 pdev = of_find_device_by_node(saw_node); 103 104 of_node_put(saw_node); 104 - of_node_put(cpu_node); 105 105 if (!pdev) 106 106 return -ENODEV; 107 107 108 108 data = devm_kzalloc(cpuidle_dev, sizeof(*data), GFP_KERNEL); 109 - if (!data) 109 + if (!data) { 110 + put_device(&pdev->dev); 110 111 return -ENOMEM; 112 + } 111 113 112 114 data->spm = dev_get_drvdata(&pdev->dev); 115 + put_device(&pdev->dev); 113 116 if (!data->spm) 114 117 return -EINVAL; 115 118
+7 -1
drivers/cpuidle/cpuidle.c
··· 635 635 static int __cpuidle_register_device(struct cpuidle_device *dev) 636 636 { 637 637 struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev); 638 + unsigned int cpu = dev->cpu; 638 639 int i, ret; 640 + 641 + if (per_cpu(cpuidle_devices, cpu)) { 642 + pr_info("CPU%d: cpuidle device already registered\n", cpu); 643 + return -EEXIST; 644 + } 639 645 640 646 if (!try_module_get(drv->owner)) 641 647 return -EINVAL; ··· 654 648 dev->states_usage[i].disable |= CPUIDLE_STATE_DISABLED_BY_USER; 655 649 } 656 650 657 - per_cpu(cpuidle_devices, dev->cpu) = dev; 651 + per_cpu(cpuidle_devices, cpu) = dev; 658 652 list_add(&dev->device_list, &cpuidle_detected_devices); 659 653 660 654 ret = cpuidle_coupled_register_device(dev);
+39 -37
drivers/cpuidle/governors/menu.c
··· 314 314 if (s->exit_latency_ns > latency_req) 315 315 break; 316 316 317 - if (s->target_residency_ns > predicted_ns) { 318 - /* 319 - * Use a physical idle state, not busy polling, unless 320 - * a timer is going to trigger soon enough. 321 - */ 322 - if ((drv->states[idx].flags & CPUIDLE_FLAG_POLLING) && 323 - s->target_residency_ns <= data->next_timer_ns) { 324 - predicted_ns = s->target_residency_ns; 325 - idx = i; 326 - break; 327 - } 328 - if (predicted_ns < TICK_NSEC) 329 - break; 330 - 331 - if (!tick_nohz_tick_stopped()) { 332 - /* 333 - * If the state selected so far is shallow, 334 - * waking up early won't hurt, so retain the 335 - * tick in that case and let the governor run 336 - * again in the next iteration of the loop. 337 - */ 338 - predicted_ns = drv->states[idx].target_residency_ns; 339 - break; 340 - } 341 - 342 - /* 343 - * If the state selected so far is shallow and this 344 - * state's target residency matches the time till the 345 - * closest timer event, select this one to avoid getting 346 - * stuck in the shallow one for too long. 347 - */ 348 - if (drv->states[idx].target_residency_ns < TICK_NSEC && 349 - s->target_residency_ns <= delta_tick) 350 - idx = i; 351 - 352 - return idx; 317 + if (s->target_residency_ns <= predicted_ns) { 318 + idx = i; 319 + continue; 353 320 } 354 321 355 - idx = i; 322 + /* 323 + * Use a physical idle state, not busy polling, unless a timer 324 + * is going to trigger soon enough. 325 + */ 326 + if ((drv->states[idx].flags & CPUIDLE_FLAG_POLLING) && 327 + s->target_residency_ns <= data->next_timer_ns) { 328 + predicted_ns = s->target_residency_ns; 329 + idx = i; 330 + break; 331 + } 332 + 333 + if (predicted_ns < TICK_NSEC) 334 + break; 335 + 336 + if (!tick_nohz_tick_stopped()) { 337 + /* 338 + * If the state selected so far is shallow, waking up 339 + * early won't hurt, so retain the tick in that case and 340 + * let the governor run again in the next iteration of 341 + * the idle loop. 342 + */ 343 + predicted_ns = drv->states[idx].target_residency_ns; 344 + break; 345 + } 346 + 347 + /* 348 + * If the state selected so far is shallow and this state's 349 + * target residency matches the time till the closest timer 350 + * event, select this one to avoid getting stuck in the shallow 351 + * one for too long. 352 + */ 353 + if (drv->states[idx].target_residency_ns < TICK_NSEC && 354 + s->target_residency_ns <= delta_tick) 355 + idx = i; 356 + 357 + return idx; 356 358 } 357 359 358 360 if (idx == -1)
+17 -17
drivers/cpuidle/sysfs.c
··· 27 27 28 28 mutex_lock(&cpuidle_lock); 29 29 list_for_each_entry(tmp, &cpuidle_governors, governor_list) { 30 - if (i >= (ssize_t) (PAGE_SIZE - (CPUIDLE_NAME_LEN + 2))) 30 + if (i >= (ssize_t)(PAGE_SIZE - (CPUIDLE_NAME_LEN + 2))) 31 31 goto out; 32 32 33 - i += scnprintf(&buf[i], CPUIDLE_NAME_LEN + 1, "%s ", tmp->name); 33 + i += sysfs_emit_at(buf, i, "%.*s ", CPUIDLE_NAME_LEN, tmp->name); 34 34 } 35 35 36 36 out: 37 - i+= sprintf(&buf[i], "\n"); 37 + i += sysfs_emit_at(buf, i, "\n"); 38 38 mutex_unlock(&cpuidle_lock); 39 39 return i; 40 40 } ··· 49 49 spin_lock(&cpuidle_driver_lock); 50 50 drv = cpuidle_get_driver(); 51 51 if (drv) 52 - ret = sprintf(buf, "%s\n", drv->name); 52 + ret = sysfs_emit(buf, "%s\n", drv->name); 53 53 else 54 - ret = sprintf(buf, "none\n"); 54 + ret = sysfs_emit(buf, "none\n"); 55 55 spin_unlock(&cpuidle_driver_lock); 56 56 57 57 return ret; ··· 65 65 66 66 mutex_lock(&cpuidle_lock); 67 67 if (cpuidle_curr_governor) 68 - ret = sprintf(buf, "%s\n", cpuidle_curr_governor->name); 68 + ret = sysfs_emit(buf, "%s\n", cpuidle_curr_governor->name); 69 69 else 70 - ret = sprintf(buf, "none\n"); 70 + ret = sysfs_emit(buf, "none\n"); 71 71 mutex_unlock(&cpuidle_lock); 72 72 73 73 return ret; ··· 230 230 static ssize_t show_state_##_name(struct cpuidle_state *state, \ 231 231 struct cpuidle_state_usage *state_usage, char *buf) \ 232 232 { \ 233 - return sprintf(buf, "%u\n", state->_name);\ 233 + return sysfs_emit(buf, "%u\n", state->_name);\ 234 234 } 235 235 236 236 #define define_show_state_ull_function(_name) \ ··· 238 238 struct cpuidle_state_usage *state_usage, \ 239 239 char *buf) \ 240 240 { \ 241 - return sprintf(buf, "%llu\n", state_usage->_name);\ 241 + return sysfs_emit(buf, "%llu\n", state_usage->_name);\ 242 242 } 243 243 244 244 #define define_show_state_str_function(_name) \ ··· 247 247 char *buf) \ 248 248 { \ 249 249 if (state->_name[0] == '\0')\ 250 - return sprintf(buf, "<null>\n");\ 251 - return sprintf(buf, "%s\n", state->_name);\ 250 + return sysfs_emit(buf, "<null>\n");\ 251 + return sysfs_emit(buf, "%s\n", state->_name);\ 252 252 } 253 253 254 254 #define define_show_state_time_function(_name) \ ··· 256 256 struct cpuidle_state_usage *state_usage, \ 257 257 char *buf) \ 258 258 { \ 259 - return sprintf(buf, "%llu\n", ktime_to_us(state->_name##_ns)); \ 259 + return sysfs_emit(buf, "%llu\n", ktime_to_us(state->_name##_ns)); \ 260 260 } 261 261 262 262 define_show_state_time_function(exit_latency) ··· 273 273 struct cpuidle_state_usage *state_usage, 274 274 char *buf) 275 275 { 276 - return sprintf(buf, "%llu\n", ktime_to_us(state_usage->time_ns)); 276 + return sysfs_emit(buf, "%llu\n", ktime_to_us(state_usage->time_ns)); 277 277 } 278 278 279 279 static ssize_t show_state_disable(struct cpuidle_state *state, 280 280 struct cpuidle_state_usage *state_usage, 281 281 char *buf) 282 282 { 283 - return sprintf(buf, "%llu\n", 283 + return sysfs_emit(buf, "%llu\n", 284 284 state_usage->disable & CPUIDLE_STATE_DISABLED_BY_USER); 285 285 } 286 286 ··· 310 310 struct cpuidle_state_usage *state_usage, 311 311 char *buf) 312 312 { 313 - return sprintf(buf, "%s\n", 313 + return sysfs_emit(buf, "%s\n", 314 314 state->flags & CPUIDLE_FLAG_OFF ? "disabled" : "enabled"); 315 315 } 316 316 ··· 358 358 struct cpuidle_state_usage *state_usage, \ 359 359 char *buf) \ 360 360 { \ 361 - return sprintf(buf, "%llu\n", state_usage->s2idle_##_name);\ 361 + return sysfs_emit(buf, "%llu\n", state_usage->s2idle_##_name);\ 362 362 } 363 363 364 364 define_show_state_s2idle_ull_function(usage); ··· 550 550 ssize_t ret; 551 551 552 552 spin_lock(&cpuidle_driver_lock); 553 - ret = sprintf(buf, "%s\n", drv ? drv->name : "none"); 553 + ret = sysfs_emit(buf, "%s\n", drv ? drv->name : "none"); 554 554 spin_unlock(&cpuidle_driver_lock); 555 555 556 556 return ret;
+128 -128
drivers/idle/intel_idle.c
··· 259 259 .flags = MWAIT2flg(0x00), 260 260 .exit_latency = 3, 261 261 .target_residency = 6, 262 - .enter = &intel_idle, 262 + .enter = intel_idle, 263 263 .enter_s2idle = intel_idle_s2idle, }, 264 264 { 265 265 .name = "C1E", ··· 267 267 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 268 268 .exit_latency = 10, 269 269 .target_residency = 20, 270 - .enter = &intel_idle, 270 + .enter = intel_idle, 271 271 .enter_s2idle = intel_idle_s2idle, }, 272 272 { 273 273 .name = "C3", ··· 275 275 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 276 276 .exit_latency = 20, 277 277 .target_residency = 80, 278 - .enter = &intel_idle, 278 + .enter = intel_idle, 279 279 .enter_s2idle = intel_idle_s2idle, }, 280 280 { 281 281 .name = "C6", ··· 283 283 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 284 284 .exit_latency = 200, 285 285 .target_residency = 800, 286 - .enter = &intel_idle, 286 + .enter = intel_idle, 287 287 .enter_s2idle = intel_idle_s2idle, }, 288 288 { 289 289 .enter = NULL } ··· 296 296 .flags = MWAIT2flg(0x00), 297 297 .exit_latency = 2, 298 298 .target_residency = 2, 299 - .enter = &intel_idle, 299 + .enter = intel_idle, 300 300 .enter_s2idle = intel_idle_s2idle, }, 301 301 { 302 302 .name = "C1E", ··· 304 304 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 305 305 .exit_latency = 10, 306 306 .target_residency = 20, 307 - .enter = &intel_idle, 307 + .enter = intel_idle, 308 308 .enter_s2idle = intel_idle_s2idle, }, 309 309 { 310 310 .name = "C3", ··· 312 312 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 313 313 .exit_latency = 80, 314 314 .target_residency = 211, 315 - .enter = &intel_idle, 315 + .enter = intel_idle, 316 316 .enter_s2idle = intel_idle_s2idle, }, 317 317 { 318 318 .name = "C6", ··· 320 320 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 321 321 .exit_latency = 104, 322 322 .target_residency = 345, 323 - .enter = &intel_idle, 323 + .enter = intel_idle, 324 324 .enter_s2idle = intel_idle_s2idle, }, 325 325 { 326 326 .name = "C7", ··· 328 328 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 329 329 .exit_latency = 109, 330 330 .target_residency = 345, 331 - .enter = &intel_idle, 331 + .enter = intel_idle, 332 332 .enter_s2idle = intel_idle_s2idle, }, 333 333 { 334 334 .enter = NULL } ··· 341 341 .flags = MWAIT2flg(0x00), 342 342 .exit_latency = 1, 343 343 .target_residency = 1, 344 - .enter = &intel_idle, 344 + .enter = intel_idle, 345 345 .enter_s2idle = intel_idle_s2idle, }, 346 346 { 347 347 .name = "C6N", ··· 349 349 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, 350 350 .exit_latency = 300, 351 351 .target_residency = 275, 352 - .enter = &intel_idle, 352 + .enter = intel_idle, 353 353 .enter_s2idle = intel_idle_s2idle, }, 354 354 { 355 355 .name = "C6S", ··· 357 357 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 358 358 .exit_latency = 500, 359 359 .target_residency = 560, 360 - .enter = &intel_idle, 360 + .enter = intel_idle, 361 361 .enter_s2idle = intel_idle_s2idle, }, 362 362 { 363 363 .name = "C7", ··· 365 365 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 366 366 .exit_latency = 1200, 367 367 .target_residency = 4000, 368 - .enter = &intel_idle, 368 + .enter = intel_idle, 369 369 .enter_s2idle = intel_idle_s2idle, }, 370 370 { 371 371 .name = "C7S", ··· 373 373 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 374 374 .exit_latency = 10000, 375 375 .target_residency = 20000, 376 - .enter = &intel_idle, 376 + .enter = intel_idle, 377 377 .enter_s2idle = intel_idle_s2idle, }, 378 378 { 379 379 .enter = NULL } ··· 386 386 .flags = MWAIT2flg(0x00), 387 387 .exit_latency = 1, 388 388 .target_residency = 1, 389 - .enter = &intel_idle, 389 + .enter = intel_idle, 390 390 .enter_s2idle = intel_idle_s2idle, }, 391 391 { 392 392 .name = "C6N", ··· 394 394 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, 395 395 .exit_latency = 80, 396 396 .target_residency = 275, 397 - .enter = &intel_idle, 397 + .enter = intel_idle, 398 398 .enter_s2idle = intel_idle_s2idle, }, 399 399 { 400 400 .name = "C6S", ··· 402 402 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 403 403 .exit_latency = 200, 404 404 .target_residency = 560, 405 - .enter = &intel_idle, 405 + .enter = intel_idle, 406 406 .enter_s2idle = intel_idle_s2idle, }, 407 407 { 408 408 .name = "C7", ··· 410 410 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 411 411 .exit_latency = 1200, 412 412 .target_residency = 4000, 413 - .enter = &intel_idle, 413 + .enter = intel_idle, 414 414 .enter_s2idle = intel_idle_s2idle, }, 415 415 { 416 416 .name = "C7S", ··· 418 418 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 419 419 .exit_latency = 10000, 420 420 .target_residency = 20000, 421 - .enter = &intel_idle, 421 + .enter = intel_idle, 422 422 .enter_s2idle = intel_idle_s2idle, }, 423 423 { 424 424 .enter = NULL } ··· 431 431 .flags = MWAIT2flg(0x00), 432 432 .exit_latency = 1, 433 433 .target_residency = 1, 434 - .enter = &intel_idle, 434 + .enter = intel_idle, 435 435 .enter_s2idle = intel_idle_s2idle, }, 436 436 { 437 437 .name = "C1E", ··· 439 439 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 440 440 .exit_latency = 10, 441 441 .target_residency = 20, 442 - .enter = &intel_idle, 442 + .enter = intel_idle, 443 443 .enter_s2idle = intel_idle_s2idle, }, 444 444 { 445 445 .name = "C3", ··· 447 447 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 448 448 .exit_latency = 59, 449 449 .target_residency = 156, 450 - .enter = &intel_idle, 450 + .enter = intel_idle, 451 451 .enter_s2idle = intel_idle_s2idle, }, 452 452 { 453 453 .name = "C6", ··· 455 455 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 456 456 .exit_latency = 80, 457 457 .target_residency = 300, 458 - .enter = &intel_idle, 458 + .enter = intel_idle, 459 459 .enter_s2idle = intel_idle_s2idle, }, 460 460 { 461 461 .name = "C7", ··· 463 463 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 464 464 .exit_latency = 87, 465 465 .target_residency = 300, 466 - .enter = &intel_idle, 466 + .enter = intel_idle, 467 467 .enter_s2idle = intel_idle_s2idle, }, 468 468 { 469 469 .enter = NULL } ··· 476 476 .flags = MWAIT2flg(0x00), 477 477 .exit_latency = 1, 478 478 .target_residency = 1, 479 - .enter = &intel_idle, 479 + .enter = intel_idle, 480 480 .enter_s2idle = intel_idle_s2idle, }, 481 481 { 482 482 .name = "C1E", ··· 484 484 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 485 485 .exit_latency = 10, 486 486 .target_residency = 80, 487 - .enter = &intel_idle, 487 + .enter = intel_idle, 488 488 .enter_s2idle = intel_idle_s2idle, }, 489 489 { 490 490 .name = "C3", ··· 492 492 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 493 493 .exit_latency = 59, 494 494 .target_residency = 156, 495 - .enter = &intel_idle, 495 + .enter = intel_idle, 496 496 .enter_s2idle = intel_idle_s2idle, }, 497 497 { 498 498 .name = "C6", ··· 500 500 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 501 501 .exit_latency = 82, 502 502 .target_residency = 300, 503 - .enter = &intel_idle, 503 + .enter = intel_idle, 504 504 .enter_s2idle = intel_idle_s2idle, }, 505 505 { 506 506 .enter = NULL } ··· 513 513 .flags = MWAIT2flg(0x00), 514 514 .exit_latency = 1, 515 515 .target_residency = 1, 516 - .enter = &intel_idle, 516 + .enter = intel_idle, 517 517 .enter_s2idle = intel_idle_s2idle, }, 518 518 { 519 519 .name = "C1E", ··· 521 521 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 522 522 .exit_latency = 10, 523 523 .target_residency = 250, 524 - .enter = &intel_idle, 524 + .enter = intel_idle, 525 525 .enter_s2idle = intel_idle_s2idle, }, 526 526 { 527 527 .name = "C3", ··· 529 529 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 530 530 .exit_latency = 59, 531 531 .target_residency = 300, 532 - .enter = &intel_idle, 532 + .enter = intel_idle, 533 533 .enter_s2idle = intel_idle_s2idle, }, 534 534 { 535 535 .name = "C6", ··· 537 537 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 538 538 .exit_latency = 84, 539 539 .target_residency = 400, 540 - .enter = &intel_idle, 540 + .enter = intel_idle, 541 541 .enter_s2idle = intel_idle_s2idle, }, 542 542 { 543 543 .enter = NULL } ··· 550 550 .flags = MWAIT2flg(0x00), 551 551 .exit_latency = 1, 552 552 .target_residency = 1, 553 - .enter = &intel_idle, 553 + .enter = intel_idle, 554 554 .enter_s2idle = intel_idle_s2idle, }, 555 555 { 556 556 .name = "C1E", ··· 558 558 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 559 559 .exit_latency = 10, 560 560 .target_residency = 500, 561 - .enter = &intel_idle, 561 + .enter = intel_idle, 562 562 .enter_s2idle = intel_idle_s2idle, }, 563 563 { 564 564 .name = "C3", ··· 566 566 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 567 567 .exit_latency = 59, 568 568 .target_residency = 600, 569 - .enter = &intel_idle, 569 + .enter = intel_idle, 570 570 .enter_s2idle = intel_idle_s2idle, }, 571 571 { 572 572 .name = "C6", ··· 574 574 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 575 575 .exit_latency = 88, 576 576 .target_residency = 700, 577 - .enter = &intel_idle, 577 + .enter = intel_idle, 578 578 .enter_s2idle = intel_idle_s2idle, }, 579 579 { 580 580 .enter = NULL } ··· 587 587 .flags = MWAIT2flg(0x00), 588 588 .exit_latency = 2, 589 589 .target_residency = 2, 590 - .enter = &intel_idle, 590 + .enter = intel_idle, 591 591 .enter_s2idle = intel_idle_s2idle, }, 592 592 { 593 593 .name = "C1E", ··· 595 595 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 596 596 .exit_latency = 10, 597 597 .target_residency = 20, 598 - .enter = &intel_idle, 598 + .enter = intel_idle, 599 599 .enter_s2idle = intel_idle_s2idle, }, 600 600 { 601 601 .name = "C3", ··· 603 603 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 604 604 .exit_latency = 33, 605 605 .target_residency = 100, 606 - .enter = &intel_idle, 606 + .enter = intel_idle, 607 607 .enter_s2idle = intel_idle_s2idle, }, 608 608 { 609 609 .name = "C6", ··· 611 611 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 612 612 .exit_latency = 133, 613 613 .target_residency = 400, 614 - .enter = &intel_idle, 614 + .enter = intel_idle, 615 615 .enter_s2idle = intel_idle_s2idle, }, 616 616 { 617 617 .name = "C7s", ··· 619 619 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 620 620 .exit_latency = 166, 621 621 .target_residency = 500, 622 - .enter = &intel_idle, 622 + .enter = intel_idle, 623 623 .enter_s2idle = intel_idle_s2idle, }, 624 624 { 625 625 .name = "C8", ··· 627 627 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 628 628 .exit_latency = 300, 629 629 .target_residency = 900, 630 - .enter = &intel_idle, 630 + .enter = intel_idle, 631 631 .enter_s2idle = intel_idle_s2idle, }, 632 632 { 633 633 .name = "C9", ··· 635 635 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 636 636 .exit_latency = 600, 637 637 .target_residency = 1800, 638 - .enter = &intel_idle, 638 + .enter = intel_idle, 639 639 .enter_s2idle = intel_idle_s2idle, }, 640 640 { 641 641 .name = "C10", ··· 643 643 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 644 644 .exit_latency = 2600, 645 645 .target_residency = 7700, 646 - .enter = &intel_idle, 646 + .enter = intel_idle, 647 647 .enter_s2idle = intel_idle_s2idle, }, 648 648 { 649 649 .enter = NULL } ··· 655 655 .flags = MWAIT2flg(0x00), 656 656 .exit_latency = 2, 657 657 .target_residency = 2, 658 - .enter = &intel_idle, 658 + .enter = intel_idle, 659 659 .enter_s2idle = intel_idle_s2idle, }, 660 660 { 661 661 .name = "C1E", ··· 663 663 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 664 664 .exit_latency = 10, 665 665 .target_residency = 20, 666 - .enter = &intel_idle, 666 + .enter = intel_idle, 667 667 .enter_s2idle = intel_idle_s2idle, }, 668 668 { 669 669 .name = "C3", ··· 671 671 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 672 672 .exit_latency = 40, 673 673 .target_residency = 100, 674 - .enter = &intel_idle, 674 + .enter = intel_idle, 675 675 .enter_s2idle = intel_idle_s2idle, }, 676 676 { 677 677 .name = "C6", ··· 679 679 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 680 680 .exit_latency = 133, 681 681 .target_residency = 400, 682 - .enter = &intel_idle, 682 + .enter = intel_idle, 683 683 .enter_s2idle = intel_idle_s2idle, }, 684 684 { 685 685 .name = "C7s", ··· 687 687 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 688 688 .exit_latency = 166, 689 689 .target_residency = 500, 690 - .enter = &intel_idle, 690 + .enter = intel_idle, 691 691 .enter_s2idle = intel_idle_s2idle, }, 692 692 { 693 693 .name = "C8", ··· 695 695 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 696 696 .exit_latency = 300, 697 697 .target_residency = 900, 698 - .enter = &intel_idle, 698 + .enter = intel_idle, 699 699 .enter_s2idle = intel_idle_s2idle, }, 700 700 { 701 701 .name = "C9", ··· 703 703 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 704 704 .exit_latency = 600, 705 705 .target_residency = 1800, 706 - .enter = &intel_idle, 706 + .enter = intel_idle, 707 707 .enter_s2idle = intel_idle_s2idle, }, 708 708 { 709 709 .name = "C10", ··· 711 711 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 712 712 .exit_latency = 2600, 713 713 .target_residency = 7700, 714 - .enter = &intel_idle, 714 + .enter = intel_idle, 715 715 .enter_s2idle = intel_idle_s2idle, }, 716 716 { 717 717 .enter = NULL } ··· 724 724 .flags = MWAIT2flg(0x00), 725 725 .exit_latency = 2, 726 726 .target_residency = 2, 727 - .enter = &intel_idle, 727 + .enter = intel_idle, 728 728 .enter_s2idle = intel_idle_s2idle, }, 729 729 { 730 730 .name = "C1E", ··· 732 732 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 733 733 .exit_latency = 10, 734 734 .target_residency = 20, 735 - .enter = &intel_idle, 735 + .enter = intel_idle, 736 736 .enter_s2idle = intel_idle_s2idle, }, 737 737 { 738 738 .name = "C3", ··· 740 740 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 741 741 .exit_latency = 70, 742 742 .target_residency = 100, 743 - .enter = &intel_idle, 743 + .enter = intel_idle, 744 744 .enter_s2idle = intel_idle_s2idle, }, 745 745 { 746 746 .name = "C6", ··· 748 748 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 749 749 .exit_latency = 85, 750 750 .target_residency = 200, 751 - .enter = &intel_idle, 751 + .enter = intel_idle, 752 752 .enter_s2idle = intel_idle_s2idle, }, 753 753 { 754 754 .name = "C7s", ··· 756 756 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 757 757 .exit_latency = 124, 758 758 .target_residency = 800, 759 - .enter = &intel_idle, 759 + .enter = intel_idle, 760 760 .enter_s2idle = intel_idle_s2idle, }, 761 761 { 762 762 .name = "C8", ··· 764 764 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 765 765 .exit_latency = 200, 766 766 .target_residency = 800, 767 - .enter = &intel_idle, 767 + .enter = intel_idle, 768 768 .enter_s2idle = intel_idle_s2idle, }, 769 769 { 770 770 .name = "C9", ··· 772 772 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 773 773 .exit_latency = 480, 774 774 .target_residency = 5000, 775 - .enter = &intel_idle, 775 + .enter = intel_idle, 776 776 .enter_s2idle = intel_idle_s2idle, }, 777 777 { 778 778 .name = "C10", ··· 780 780 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 781 781 .exit_latency = 890, 782 782 .target_residency = 5000, 783 - .enter = &intel_idle, 783 + .enter = intel_idle, 784 784 .enter_s2idle = intel_idle_s2idle, }, 785 785 { 786 786 .enter = NULL } ··· 793 793 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, 794 794 .exit_latency = 2, 795 795 .target_residency = 2, 796 - .enter = &intel_idle, 796 + .enter = intel_idle, 797 797 .enter_s2idle = intel_idle_s2idle, }, 798 798 { 799 799 .name = "C1E", ··· 801 801 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 802 802 .exit_latency = 10, 803 803 .target_residency = 20, 804 - .enter = &intel_idle, 804 + .enter = intel_idle, 805 805 .enter_s2idle = intel_idle_s2idle, }, 806 806 { 807 807 .name = "C6", ··· 809 809 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | CPUIDLE_FLAG_IBRS, 810 810 .exit_latency = 133, 811 811 .target_residency = 600, 812 - .enter = &intel_idle, 812 + .enter = intel_idle, 813 813 .enter_s2idle = intel_idle_s2idle, }, 814 814 { 815 815 .enter = NULL } ··· 822 822 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE, 823 823 .exit_latency = 1, 824 824 .target_residency = 1, 825 - .enter = &intel_idle, 825 + .enter = intel_idle, 826 826 .enter_s2idle = intel_idle_s2idle, }, 827 827 { 828 828 .name = "C1E", ··· 830 830 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 831 831 .exit_latency = 4, 832 832 .target_residency = 4, 833 - .enter = &intel_idle, 833 + .enter = intel_idle, 834 834 .enter_s2idle = intel_idle_s2idle, }, 835 835 { 836 836 .name = "C6", ··· 838 838 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 839 839 .exit_latency = 170, 840 840 .target_residency = 600, 841 - .enter = &intel_idle, 841 + .enter = intel_idle, 842 842 .enter_s2idle = intel_idle_s2idle, }, 843 843 { 844 844 .enter = NULL } ··· 861 861 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE, 862 862 .exit_latency = 1, 863 863 .target_residency = 1, 864 - .enter = &intel_idle, 864 + .enter = intel_idle, 865 865 .enter_s2idle = intel_idle_s2idle, }, 866 866 { 867 867 .name = "C1E", ··· 869 869 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 870 870 .exit_latency = 2, 871 871 .target_residency = 4, 872 - .enter = &intel_idle, 872 + .enter = intel_idle, 873 873 .enter_s2idle = intel_idle_s2idle, }, 874 874 { 875 875 .name = "C6", ··· 877 877 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 878 878 .exit_latency = 220, 879 879 .target_residency = 600, 880 - .enter = &intel_idle, 880 + .enter = intel_idle, 881 881 .enter_s2idle = intel_idle_s2idle, }, 882 882 { 883 883 .name = "C8", ··· 885 885 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 886 886 .exit_latency = 280, 887 887 .target_residency = 800, 888 - .enter = &intel_idle, 888 + .enter = intel_idle, 889 889 .enter_s2idle = intel_idle_s2idle, }, 890 890 { 891 891 .name = "C10", ··· 893 893 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 894 894 .exit_latency = 680, 895 895 .target_residency = 2000, 896 - .enter = &intel_idle, 896 + .enter = intel_idle, 897 897 .enter_s2idle = intel_idle_s2idle, }, 898 898 { 899 899 .enter = NULL } ··· 906 906 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE, 907 907 .exit_latency = 1, 908 908 .target_residency = 1, 909 - .enter = &intel_idle, 909 + .enter = intel_idle, 910 910 .enter_s2idle = intel_idle_s2idle, }, 911 911 { 912 912 .name = "C1E", ··· 914 914 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 915 915 .exit_latency = 2, 916 916 .target_residency = 4, 917 - .enter = &intel_idle, 917 + .enter = intel_idle, 918 918 .enter_s2idle = intel_idle_s2idle, }, 919 919 { 920 920 .name = "C6", ··· 922 922 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 923 923 .exit_latency = 170, 924 924 .target_residency = 500, 925 - .enter = &intel_idle, 925 + .enter = intel_idle, 926 926 .enter_s2idle = intel_idle_s2idle, }, 927 927 { 928 928 .name = "C8", ··· 930 930 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 931 931 .exit_latency = 200, 932 932 .target_residency = 600, 933 - .enter = &intel_idle, 933 + .enter = intel_idle, 934 934 .enter_s2idle = intel_idle_s2idle, }, 935 935 { 936 936 .name = "C10", ··· 938 938 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 939 939 .exit_latency = 230, 940 940 .target_residency = 700, 941 - .enter = &intel_idle, 941 + .enter = intel_idle, 942 942 .enter_s2idle = intel_idle_s2idle, }, 943 943 { 944 944 .enter = NULL } ··· 951 951 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 952 952 .exit_latency = 1, 953 953 .target_residency = 1, 954 - .enter = &intel_idle, 954 + .enter = intel_idle, 955 955 .enter_s2idle = intel_idle_s2idle, }, 956 956 { 957 957 .name = "C6", ··· 959 959 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 960 960 .exit_latency = 140, 961 961 .target_residency = 420, 962 - .enter = &intel_idle, 962 + .enter = intel_idle, 963 963 .enter_s2idle = intel_idle_s2idle, }, 964 964 { 965 965 .name = "C10", ··· 967 967 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 968 968 .exit_latency = 310, 969 969 .target_residency = 930, 970 - .enter = &intel_idle, 970 + .enter = intel_idle, 971 971 .enter_s2idle = intel_idle_s2idle, }, 972 972 { 973 973 .enter = NULL } ··· 980 980 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_UNUSABLE, 981 981 .exit_latency = 1, 982 982 .target_residency = 1, 983 - .enter = &intel_idle, 983 + .enter = intel_idle, 984 984 .enter_s2idle = intel_idle_s2idle, }, 985 985 { 986 986 .name = "C1E", ··· 988 988 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 989 989 .exit_latency = 2, 990 990 .target_residency = 4, 991 - .enter = &intel_idle, 991 + .enter = intel_idle, 992 992 .enter_s2idle = intel_idle_s2idle, }, 993 993 { 994 994 .name = "C6", ··· 996 996 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 997 997 .exit_latency = 195, 998 998 .target_residency = 585, 999 - .enter = &intel_idle, 999 + .enter = intel_idle, 1000 1000 .enter_s2idle = intel_idle_s2idle, }, 1001 1001 { 1002 1002 .name = "C8", ··· 1004 1004 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 1005 1005 .exit_latency = 260, 1006 1006 .target_residency = 1040, 1007 - .enter = &intel_idle, 1007 + .enter = intel_idle, 1008 1008 .enter_s2idle = intel_idle_s2idle, }, 1009 1009 { 1010 1010 .name = "C10", ··· 1012 1012 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 1013 1013 .exit_latency = 660, 1014 1014 .target_residency = 1980, 1015 - .enter = &intel_idle, 1015 + .enter = intel_idle, 1016 1016 .enter_s2idle = intel_idle_s2idle, }, 1017 1017 { 1018 1018 .enter = NULL } ··· 1025 1025 .flags = MWAIT2flg(0x00), 1026 1026 .exit_latency = 1, 1027 1027 .target_residency = 1, 1028 - .enter = &intel_idle, 1028 + .enter = intel_idle, 1029 1029 .enter_s2idle = intel_idle_s2idle, }, 1030 1030 { 1031 1031 .name = "C1E", ··· 1033 1033 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1034 1034 .exit_latency = 2, 1035 1035 .target_residency = 4, 1036 - .enter = &intel_idle, 1036 + .enter = intel_idle, 1037 1037 .enter_s2idle = intel_idle_s2idle, }, 1038 1038 { 1039 1039 .name = "C6", ··· 1042 1042 CPUIDLE_FLAG_INIT_XSTATE, 1043 1043 .exit_latency = 290, 1044 1044 .target_residency = 800, 1045 - .enter = &intel_idle, 1045 + .enter = intel_idle, 1046 1046 .enter_s2idle = intel_idle_s2idle, }, 1047 1047 { 1048 1048 .enter = NULL } ··· 1055 1055 .flags = MWAIT2flg(0x00), 1056 1056 .exit_latency = 1, 1057 1057 .target_residency = 1, 1058 - .enter = &intel_idle, 1058 + .enter = intel_idle, 1059 1059 .enter_s2idle = intel_idle_s2idle, }, 1060 1060 { 1061 1061 .name = "C1E", ··· 1063 1063 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1064 1064 .exit_latency = 4, 1065 1065 .target_residency = 4, 1066 - .enter = &intel_idle, 1066 + .enter = intel_idle, 1067 1067 .enter_s2idle = intel_idle_s2idle, }, 1068 1068 { 1069 1069 .name = "C6", ··· 1073 1073 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1074 1074 .exit_latency = 170, 1075 1075 .target_residency = 650, 1076 - .enter = &intel_idle, 1076 + .enter = intel_idle, 1077 1077 .enter_s2idle = intel_idle_s2idle, }, 1078 1078 { 1079 1079 .name = "C6P", ··· 1083 1083 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1084 1084 .exit_latency = 210, 1085 1085 .target_residency = 1000, 1086 - .enter = &intel_idle, 1086 + .enter = intel_idle, 1087 1087 .enter_s2idle = intel_idle_s2idle, }, 1088 1088 { 1089 1089 .enter = NULL } ··· 1096 1096 .flags = MWAIT2flg(0x00), 1097 1097 .exit_latency = 1, 1098 1098 .target_residency = 1, 1099 - .enter = &intel_idle, 1099 + .enter = intel_idle, 1100 1100 .enter_s2idle = intel_idle_s2idle, }, 1101 1101 { 1102 1102 .name = "C1E", ··· 1104 1104 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1105 1105 .exit_latency = 4, 1106 1106 .target_residency = 4, 1107 - .enter = &intel_idle, 1107 + .enter = intel_idle, 1108 1108 .enter_s2idle = intel_idle_s2idle, }, 1109 1109 { 1110 1110 .name = "C6", ··· 1114 1114 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1115 1115 .exit_latency = 220, 1116 1116 .target_residency = 650, 1117 - .enter = &intel_idle, 1117 + .enter = intel_idle, 1118 1118 .enter_s2idle = intel_idle_s2idle, }, 1119 1119 { 1120 1120 .name = "C6P", ··· 1124 1124 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1125 1125 .exit_latency = 240, 1126 1126 .target_residency = 750, 1127 - .enter = &intel_idle, 1127 + .enter = intel_idle, 1128 1128 .enter_s2idle = intel_idle_s2idle, }, 1129 1129 { 1130 1130 .enter = NULL } ··· 1137 1137 .flags = MWAIT2flg(0x00), 1138 1138 .exit_latency = 10, 1139 1139 .target_residency = 20, 1140 - .enter = &intel_idle, 1140 + .enter = intel_idle, 1141 1141 .enter_s2idle = intel_idle_s2idle, }, 1142 1142 { 1143 1143 .name = "C2", ··· 1145 1145 .flags = MWAIT2flg(0x10), 1146 1146 .exit_latency = 20, 1147 1147 .target_residency = 80, 1148 - .enter = &intel_idle, 1148 + .enter = intel_idle, 1149 1149 .enter_s2idle = intel_idle_s2idle, }, 1150 1150 { 1151 1151 .name = "C4", ··· 1153 1153 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 1154 1154 .exit_latency = 100, 1155 1155 .target_residency = 400, 1156 - .enter = &intel_idle, 1156 + .enter = intel_idle, 1157 1157 .enter_s2idle = intel_idle_s2idle, }, 1158 1158 { 1159 1159 .name = "C6", ··· 1161 1161 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 1162 1162 .exit_latency = 140, 1163 1163 .target_residency = 560, 1164 - .enter = &intel_idle, 1164 + .enter = intel_idle, 1165 1165 .enter_s2idle = intel_idle_s2idle, }, 1166 1166 { 1167 1167 .enter = NULL } ··· 1173 1173 .flags = MWAIT2flg(0x00), 1174 1174 .exit_latency = 1, 1175 1175 .target_residency = 4, 1176 - .enter = &intel_idle, 1176 + .enter = intel_idle, 1177 1177 .enter_s2idle = intel_idle_s2idle, }, 1178 1178 { 1179 1179 .name = "C4", ··· 1181 1181 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 1182 1182 .exit_latency = 100, 1183 1183 .target_residency = 400, 1184 - .enter = &intel_idle, 1184 + .enter = intel_idle, 1185 1185 .enter_s2idle = intel_idle_s2idle, }, 1186 1186 { 1187 1187 .name = "C6", ··· 1189 1189 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 1190 1190 .exit_latency = 140, 1191 1191 .target_residency = 560, 1192 - .enter = &intel_idle, 1192 + .enter = intel_idle, 1193 1193 .enter_s2idle = intel_idle_s2idle, }, 1194 1194 { 1195 1195 .name = "C7", ··· 1197 1197 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 1198 1198 .exit_latency = 1200, 1199 1199 .target_residency = 4000, 1200 - .enter = &intel_idle, 1200 + .enter = intel_idle, 1201 1201 .enter_s2idle = intel_idle_s2idle, }, 1202 1202 { 1203 1203 .name = "C9", ··· 1205 1205 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 1206 1206 .exit_latency = 10000, 1207 1207 .target_residency = 20000, 1208 - .enter = &intel_idle, 1208 + .enter = intel_idle, 1209 1209 .enter_s2idle = intel_idle_s2idle, }, 1210 1210 { 1211 1211 .enter = NULL } ··· 1217 1217 .flags = MWAIT2flg(0x00), 1218 1218 .exit_latency = 2, 1219 1219 .target_residency = 2, 1220 - .enter = &intel_idle, 1220 + .enter = intel_idle, 1221 1221 .enter_s2idle = intel_idle_s2idle, }, 1222 1222 { 1223 1223 .name = "C6", ··· 1225 1225 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, 1226 1226 .exit_latency = 15, 1227 1227 .target_residency = 45, 1228 - .enter = &intel_idle, 1228 + .enter = intel_idle, 1229 1229 .enter_s2idle = intel_idle_s2idle, }, 1230 1230 { 1231 1231 .enter = NULL } ··· 1237 1237 .flags = MWAIT2flg(0x00), 1238 1238 .exit_latency = 1, 1239 1239 .target_residency = 2, 1240 - .enter = &intel_idle, 1240 + .enter = intel_idle, 1241 1241 .enter_s2idle = intel_idle_s2idle }, 1242 1242 { 1243 1243 .name = "C6", ··· 1245 1245 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 1246 1246 .exit_latency = 120, 1247 1247 .target_residency = 500, 1248 - .enter = &intel_idle, 1248 + .enter = intel_idle, 1249 1249 .enter_s2idle = intel_idle_s2idle }, 1250 1250 { 1251 1251 .enter = NULL } ··· 1258 1258 .flags = MWAIT2flg(0x00), 1259 1259 .exit_latency = 2, 1260 1260 .target_residency = 2, 1261 - .enter = &intel_idle, 1261 + .enter = intel_idle, 1262 1262 .enter_s2idle = intel_idle_s2idle, }, 1263 1263 { 1264 1264 .name = "C1E", ··· 1266 1266 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1267 1267 .exit_latency = 10, 1268 1268 .target_residency = 20, 1269 - .enter = &intel_idle, 1269 + .enter = intel_idle, 1270 1270 .enter_s2idle = intel_idle_s2idle, }, 1271 1271 { 1272 1272 .name = "C6", ··· 1274 1274 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 1275 1275 .exit_latency = 133, 1276 1276 .target_residency = 133, 1277 - .enter = &intel_idle, 1277 + .enter = intel_idle, 1278 1278 .enter_s2idle = intel_idle_s2idle, }, 1279 1279 { 1280 1280 .name = "C7s", ··· 1282 1282 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED, 1283 1283 .exit_latency = 155, 1284 1284 .target_residency = 155, 1285 - .enter = &intel_idle, 1285 + .enter = intel_idle, 1286 1286 .enter_s2idle = intel_idle_s2idle, }, 1287 1287 { 1288 1288 .name = "C8", ··· 1290 1290 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 1291 1291 .exit_latency = 1000, 1292 1292 .target_residency = 1000, 1293 - .enter = &intel_idle, 1293 + .enter = intel_idle, 1294 1294 .enter_s2idle = intel_idle_s2idle, }, 1295 1295 { 1296 1296 .name = "C9", ··· 1298 1298 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 1299 1299 .exit_latency = 2000, 1300 1300 .target_residency = 2000, 1301 - .enter = &intel_idle, 1301 + .enter = intel_idle, 1302 1302 .enter_s2idle = intel_idle_s2idle, }, 1303 1303 { 1304 1304 .name = "C10", ··· 1306 1306 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 1307 1307 .exit_latency = 10000, 1308 1308 .target_residency = 10000, 1309 - .enter = &intel_idle, 1309 + .enter = intel_idle, 1310 1310 .enter_s2idle = intel_idle_s2idle, }, 1311 1311 { 1312 1312 .enter = NULL } ··· 1319 1319 .flags = MWAIT2flg(0x00), 1320 1320 .exit_latency = 2, 1321 1321 .target_residency = 2, 1322 - .enter = &intel_idle, 1322 + .enter = intel_idle, 1323 1323 .enter_s2idle = intel_idle_s2idle, }, 1324 1324 { 1325 1325 .name = "C1E", ··· 1327 1327 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1328 1328 .exit_latency = 10, 1329 1329 .target_residency = 20, 1330 - .enter = &intel_idle, 1330 + .enter = intel_idle, 1331 1331 .enter_s2idle = intel_idle_s2idle, }, 1332 1332 { 1333 1333 .name = "C6", ··· 1335 1335 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 1336 1336 .exit_latency = 50, 1337 1337 .target_residency = 500, 1338 - .enter = &intel_idle, 1338 + .enter = intel_idle, 1339 1339 .enter_s2idle = intel_idle_s2idle, }, 1340 1340 { 1341 1341 .enter = NULL } ··· 1352 1352 .flags = MWAIT2flg(0x00), 1353 1353 .exit_latency = 2, 1354 1354 .target_residency = 2, 1355 - .enter = &intel_idle, 1355 + .enter = intel_idle, 1356 1356 .enter_s2idle = intel_idle_s2idle, }, 1357 1357 { 1358 1358 .name = "C1E", ··· 1360 1360 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1361 1361 .exit_latency = 15, 1362 1362 .target_residency = 25, 1363 - .enter = &intel_idle, 1363 + .enter = intel_idle, 1364 1364 .enter_s2idle = intel_idle_s2idle, }, 1365 1365 { 1366 1366 .name = "C6", ··· 1368 1368 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 1369 1369 .exit_latency = 130, 1370 1370 .target_residency = 500, 1371 - .enter = &intel_idle, 1371 + .enter = intel_idle, 1372 1372 .enter_s2idle = intel_idle_s2idle, }, 1373 1373 { 1374 1374 .enter = NULL } ··· 1381 1381 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1382 1382 .exit_latency = 1, 1383 1383 .target_residency = 1, 1384 - .enter = &intel_idle, 1384 + .enter = intel_idle, 1385 1385 .enter_s2idle = intel_idle_s2idle, }, 1386 1386 { 1387 1387 .name = "C1E", ··· 1389 1389 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1390 1390 .exit_latency = 2, 1391 1391 .target_residency = 10, 1392 - .enter = &intel_idle, 1392 + .enter = intel_idle, 1393 1393 .enter_s2idle = intel_idle_s2idle, }, 1394 1394 { 1395 1395 .name = "C6S", ··· 1397 1397 .flags = MWAIT2flg(0x22) | CPUIDLE_FLAG_TLB_FLUSHED, 1398 1398 .exit_latency = 140, 1399 1399 .target_residency = 500, 1400 - .enter = &intel_idle, 1400 + .enter = intel_idle, 1401 1401 .enter_s2idle = intel_idle_s2idle, }, 1402 1402 { 1403 1403 .enter = NULL } ··· 1410 1410 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1411 1411 .exit_latency = 1, 1412 1412 .target_residency = 1, 1413 - .enter = &intel_idle, 1413 + .enter = intel_idle, 1414 1414 .enter_s2idle = intel_idle_s2idle, }, 1415 1415 { 1416 1416 .name = "C1E", ··· 1418 1418 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE, 1419 1419 .exit_latency = 2, 1420 1420 .target_residency = 10, 1421 - .enter = &intel_idle, 1421 + .enter = intel_idle, 1422 1422 .enter_s2idle = intel_idle_s2idle, }, 1423 1423 { 1424 1424 .name = "C6S", ··· 1427 1427 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1428 1428 .exit_latency = 270, 1429 1429 .target_residency = 700, 1430 - .enter = &intel_idle, 1430 + .enter = intel_idle, 1431 1431 .enter_s2idle = intel_idle_s2idle, }, 1432 1432 { 1433 1433 .name = "C6SP", ··· 1436 1436 CPUIDLE_FLAG_PARTIAL_HINT_MATCH, 1437 1437 .exit_latency = 310, 1438 1438 .target_residency = 900, 1439 - .enter = &intel_idle, 1439 + .enter = intel_idle, 1440 1440 .enter_s2idle = intel_idle_s2idle, }, 1441 1441 { 1442 1442 .enter = NULL }
+2 -3
drivers/powercap/idle_inject.c
··· 133 133 duration_us = READ_ONCE(ii_dev->run_duration_us); 134 134 duration_us += READ_ONCE(ii_dev->idle_duration_us); 135 135 136 - hrtimer_forward_now(timer, ns_to_ktime(duration_us * NSEC_PER_USEC)); 136 + hrtimer_forward_now(timer, us_to_ktime(duration_us)); 137 137 138 138 return HRTIMER_RESTART; 139 139 } ··· 232 232 idle_inject_wakeup(ii_dev); 233 233 234 234 hrtimer_start(&ii_dev->timer, 235 - ns_to_ktime((idle_duration_us + run_duration_us) * 236 - NSEC_PER_USEC), 235 + us_to_ktime(idle_duration_us + run_duration_us), 237 236 HRTIMER_MODE_REL); 238 237 239 238 return 0;