Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-for-v4.11-rc3' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Bunch of fixes across the drivers, in a St Patrick's day pull request
(please turn terminal colors to green on black or black on green for
full effect).
On the arm side, tilcdc, omap and malidp got fixes, while amd has some
powermanagement fixes, and intel has a set of fixes across the driver.
Nothing seems to bad or scary at this point"
* tag 'drm-fixes-for-v4.11-rc3' of git://people.freedesktop.org/~airlied/linux: (27 commits)
drm/amd/amdgpu: Fix debugfs reg read/write address width
drm/amdgpu/si: add dpm quirk for Oland
drm/radeon/si: add dpm quirk for Oland
drm: amd: remove broken include path
drm/amd/powerplay: fix copy error in smu7_clockpoweragting.c
drm/tilcdc: Set framebuffer DMA address to HW only if CRTC is enabled
drm/tilcdc: Fix hardcoded fail-return value in tilcdc_crtc_create()
drm/i915: Fix forcewake active domain tracking
drm/i915: Nuke skl_update_plane debug message from the pipe update critical section
drm/i915: use correct node for handling cache domain eviction
uapi: fix drm/omap_drm.h userspace compilation errors
drm/omap: fix dmabuf mmap for dma_alloc'ed buffers
drm/amdgpu: fix parser init error path to avoid crash in parser fini
drm/amd/amdgpu: Disable GFX_PG on Carrizo until compute issues solved
drm: mali-dp: Fix smart layer not going to composition
drm: mali-dp: Remove mclk rate management
drm/i915: Drain the freed state from the tail of the next commit
drm/i915: Nuke debug messages from the pipe update critical section
drm/i915: Use pagecache write to prepopulate shmemfs from pwrite-ioctl
drm/i915: Store a permanent error in obj->mm.pages
...
+271
-123
-2
drivers/gpu/drm/amd/acp/Makefile
-2
drivers/gpu/drm/amd/acp/Makefile
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
···
2590
2590
use_bank = 0;
2591
2591
}
2592
2592
2593
-
*pos &= 0x3FFFF;
2593
+
*pos &= (1UL << 22) - 1;
2594
2594
2595
2595
if (use_bank) {
2596
2596
if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
···
2666
2666
use_bank = 0;
2667
2667
}
2668
2668
2669
-
*pos &= 0x3FFFF;
2669
+
*pos &= (1UL << 22) - 1;
2670
2670
2671
2671
if (use_bank) {
2672
2672
if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
+6
drivers/gpu/drm/amd/amdgpu/si_dpm.c
+6
drivers/gpu/drm/amd/amdgpu/si_dpm.c
···
3464
3464
(adev->pdev->device == 0x6667)) {
3465
3465
max_sclk = 75000;
3466
3466
}
3467
+
} else if (adev->asic_type == CHIP_OLAND) {
3468
+
if ((adev->pdev->device == 0x6604) &&
3469
+
(adev->pdev->subsystem_vendor == 0x1028) &&
3470
+
(adev->pdev->subsystem_device == 0x066F)) {
3471
+
max_sclk = 75000;
3472
+
}
3467
3473
}
3468
3474
3469
3475
if (rps->vce_active) {
+1
-1
drivers/gpu/drm/amd/amdgpu/vi.c
+1
-1
drivers/gpu/drm/amd/amdgpu/vi.c
···
1051
1051
/* rev0 hardware requires workarounds to support PG */
1052
1052
adev->pg_flags = 0;
1053
1053
if (adev->rev_id != 0x00) {
1054
-
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
1054
+
adev->pg_flags |=
1055
1055
AMD_PG_SUPPORT_GFX_SMG |
1056
1056
AMD_PG_SUPPORT_GFX_PIPELINE |
1057
1057
AMD_PG_SUPPORT_CP |
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+1
-1
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+1
-2
drivers/gpu/drm/arm/malidp_crtc.c
+1
-2
drivers/gpu/drm/arm/malidp_crtc.c
···
63
63
64
64
clk_prepare_enable(hwdev->pxlclk);
65
65
66
-
/* mclk needs to be set to the same or higher rate than pxlclk */
67
-
clk_set_rate(hwdev->mclk, crtc->state->adjusted_mode.crtc_clock * 1000);
66
+
/* We rely on firmware to set mclk to a sensible level. */
68
67
clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
69
68
70
69
hwdev->modeset(hwdev, &vm);
+1
-1
drivers/gpu/drm/arm/malidp_hw.c
+1
-1
drivers/gpu/drm/arm/malidp_hw.c
···
83
83
{ DE_VIDEO1, MALIDP550_DE_LV1_BASE, MALIDP550_DE_LV1_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
84
84
{ DE_GRAPHICS1, MALIDP550_DE_LG_BASE, MALIDP550_DE_LG_PTR_BASE, MALIDP_DE_LG_STRIDE },
85
85
{ DE_VIDEO2, MALIDP550_DE_LV2_BASE, MALIDP550_DE_LV2_PTR_BASE, MALIDP_DE_LV_STRIDE0 },
86
-
{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, 0 },
86
+
{ DE_SMART, MALIDP550_DE_LS_BASE, MALIDP550_DE_LS_PTR_BASE, MALIDP550_DE_LS_R1_STRIDE },
87
87
};
88
88
89
89
#define MALIDP_DE_DEFAULT_PREFETCH_START 5
+16
-2
drivers/gpu/drm/arm/malidp_planes.c
+16
-2
drivers/gpu/drm/arm/malidp_planes.c
···
37
37
#define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
38
38
#define MALIDP_LAYER_COMP_SIZE 0x010
39
39
#define MALIDP_LAYER_OFFSET 0x014
40
+
#define MALIDP550_LS_ENABLE 0x01c
41
+
#define MALIDP550_LS_R1_IN_SIZE 0x020
40
42
41
43
/*
42
44
* This 4-entry look-up-table is used to determine the full 8-bit alpha value
···
244
242
LAYER_V_VAL(plane->state->crtc_y),
245
243
mp->layer->base + MALIDP_LAYER_OFFSET);
246
244
245
+
if (mp->layer->id == DE_SMART)
246
+
malidp_hw_write(mp->hwdev,
247
+
LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
248
+
mp->layer->base + MALIDP550_LS_R1_IN_SIZE);
249
+
247
250
/* first clear the rotation bits */
248
251
val = malidp_hw_read(mp->hwdev, mp->layer->base + MALIDP_LAYER_CONTROL);
249
252
val &= ~LAYER_ROT_MASK;
···
337
330
plane->hwdev = malidp->dev;
338
331
plane->layer = &map->layers[i];
339
332
340
-
/* Skip the features which the SMART layer doesn't have */
341
-
if (id == DE_SMART)
333
+
if (id == DE_SMART) {
334
+
/*
335
+
* Enable the first rectangle in the SMART layer to be
336
+
* able to use it as a drm plane.
337
+
*/
338
+
malidp_hw_write(malidp->dev, 1,
339
+
plane->layer->base + MALIDP550_LS_ENABLE);
340
+
/* Skip the features which the SMART layer doesn't have. */
342
341
continue;
342
+
}
343
343
344
344
drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags);
345
345
malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
+1
drivers/gpu/drm/arm/malidp_regs.h
+1
drivers/gpu/drm/arm/malidp_regs.h
+1
drivers/gpu/drm/i915/i915_drv.h
+1
drivers/gpu/drm/i915/i915_drv.h
+94
-3
drivers/gpu/drm/i915/i915_gem.c
+94
-3
drivers/gpu/drm/i915/i915_gem.c
···
1434
1434
1435
1435
trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1436
1436
1437
+
ret = -ENODEV;
1438
+
if (obj->ops->pwrite)
1439
+
ret = obj->ops->pwrite(obj, args);
1440
+
if (ret != -ENODEV)
1441
+
goto err;
1442
+
1437
1443
ret = i915_gem_object_wait(obj,
1438
1444
I915_WAIT_INTERRUPTIBLE |
1439
1445
I915_WAIT_ALL,
···
2125
2119
*/
2126
2120
shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2127
2121
obj->mm.madv = __I915_MADV_PURGED;
2122
+
obj->mm.pages = ERR_PTR(-EFAULT);
2128
2123
}
2129
2124
2130
2125
/* Try to discard unwanted pages */
···
2225
2218
2226
2219
__i915_gem_object_reset_page_iter(obj);
2227
2220
2228
-
obj->ops->put_pages(obj, pages);
2221
+
if (!IS_ERR(pages))
2222
+
obj->ops->put_pages(obj, pages);
2223
+
2229
2224
unlock:
2230
2225
mutex_unlock(&obj->mm.lock);
2231
2226
}
···
2446
2437
if (err)
2447
2438
return err;
2448
2439
2449
-
if (unlikely(!obj->mm.pages)) {
2440
+
if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2450
2441
err = ____i915_gem_object_get_pages(obj);
2451
2442
if (err)
2452
2443
goto unlock;
···
2524
2515
2525
2516
pinned = true;
2526
2517
if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {
2527
-
if (unlikely(!obj->mm.pages)) {
2518
+
if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {
2528
2519
ret = ____i915_gem_object_get_pages(obj);
2529
2520
if (ret)
2530
2521
goto err_unlock;
···
2570
2561
err_unlock:
2571
2562
ptr = ERR_PTR(ret);
2572
2563
goto out_unlock;
2564
+
}
2565
+
2566
+
static int
2567
+
i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj,
2568
+
const struct drm_i915_gem_pwrite *arg)
2569
+
{
2570
+
struct address_space *mapping = obj->base.filp->f_mapping;
2571
+
char __user *user_data = u64_to_user_ptr(arg->data_ptr);
2572
+
u64 remain, offset;
2573
+
unsigned int pg;
2574
+
2575
+
/* Before we instantiate/pin the backing store for our use, we
2576
+
* can prepopulate the shmemfs filp efficiently using a write into
2577
+
* the pagecache. We avoid the penalty of instantiating all the
2578
+
* pages, important if the user is just writing to a few and never
2579
+
* uses the object on the GPU, and using a direct write into shmemfs
2580
+
* allows it to avoid the cost of retrieving a page (either swapin
2581
+
* or clearing-before-use) before it is overwritten.
2582
+
*/
2583
+
if (READ_ONCE(obj->mm.pages))
2584
+
return -ENODEV;
2585
+
2586
+
/* Before the pages are instantiated the object is treated as being
2587
+
* in the CPU domain. The pages will be clflushed as required before
2588
+
* use, and we can freely write into the pages directly. If userspace
2589
+
* races pwrite with any other operation; corruption will ensue -
2590
+
* that is userspace's prerogative!
2591
+
*/
2592
+
2593
+
remain = arg->size;
2594
+
offset = arg->offset;
2595
+
pg = offset_in_page(offset);
2596
+
2597
+
do {
2598
+
unsigned int len, unwritten;
2599
+
struct page *page;
2600
+
void *data, *vaddr;
2601
+
int err;
2602
+
2603
+
len = PAGE_SIZE - pg;
2604
+
if (len > remain)
2605
+
len = remain;
2606
+
2607
+
err = pagecache_write_begin(obj->base.filp, mapping,
2608
+
offset, len, 0,
2609
+
&page, &data);
2610
+
if (err < 0)
2611
+
return err;
2612
+
2613
+
vaddr = kmap(page);
2614
+
unwritten = copy_from_user(vaddr + pg, user_data, len);
2615
+
kunmap(page);
2616
+
2617
+
err = pagecache_write_end(obj->base.filp, mapping,
2618
+
offset, len, len - unwritten,
2619
+
page, data);
2620
+
if (err < 0)
2621
+
return err;
2622
+
2623
+
if (unwritten)
2624
+
return -EFAULT;
2625
+
2626
+
remain -= len;
2627
+
user_data += len;
2628
+
offset += len;
2629
+
pg = 0;
2630
+
} while (remain);
2631
+
2632
+
return 0;
2573
2633
}
2574
2634
2575
2635
static bool ban_context(const struct i915_gem_context *ctx)
···
3106
3028
if (args->timeout_ns > 0) {
3107
3029
args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start));
3108
3030
if (args->timeout_ns < 0)
3031
+
args->timeout_ns = 0;
3032
+
3033
+
/*
3034
+
* Apparently ktime isn't accurate enough and occasionally has a
3035
+
* bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
3036
+
* things up to make the test happy. We allow up to 1 jiffy.
3037
+
*
3038
+
* This is a regression from the timespec->ktime conversion.
3039
+
*/
3040
+
if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns))
3109
3041
args->timeout_ns = 0;
3110
3042
}
3111
3043
···
4062
3974
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4063
3975
.flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE |
4064
3976
I915_GEM_OBJECT_IS_SHRINKABLE,
3977
+
4065
3978
.get_pages = i915_gem_object_get_pages_gtt,
4066
3979
.put_pages = i915_gem_object_put_pages_gtt,
3980
+
3981
+
.pwrite = i915_gem_object_pwrite_gtt,
4067
3982
};
4068
3983
4069
3984
struct drm_i915_gem_object *
+4
-4
drivers/gpu/drm/i915/i915_gem_evict.c
+4
-4
drivers/gpu/drm/i915/i915_gem_evict.c
···
293
293
* those as well to make room for our guard pages.
294
294
*/
295
295
if (check_color) {
296
-
if (vma->node.start + vma->node.size == node->start) {
297
-
if (vma->node.color == node->color)
296
+
if (node->start + node->size == target->start) {
297
+
if (node->color == target->color)
298
298
continue;
299
299
}
300
-
if (vma->node.start == node->start + node->size) {
301
-
if (vma->node.color == node->color)
300
+
if (node->start == target->start + target->size) {
301
+
if (node->color == target->color)
302
302
continue;
303
303
}
304
304
}
+3
drivers/gpu/drm/i915/i915_gem_object.h
+3
drivers/gpu/drm/i915/i915_gem_object.h
···
54
54
struct sg_table *(*get_pages)(struct drm_i915_gem_object *);
55
55
void (*put_pages)(struct drm_i915_gem_object *, struct sg_table *);
56
56
57
+
int (*pwrite)(struct drm_i915_gem_object *,
58
+
const struct drm_i915_gem_pwrite *);
59
+
57
60
int (*dmabuf_export)(struct drm_i915_gem_object *);
58
61
void (*release)(struct drm_i915_gem_object *);
59
62
};
+37
-20
drivers/gpu/drm/i915/i915_vma.c
+37
-20
drivers/gpu/drm/i915/i915_vma.c
···
512
512
return ret;
513
513
}
514
514
515
+
static void
516
+
i915_vma_remove(struct i915_vma *vma)
517
+
{
518
+
struct drm_i915_gem_object *obj = vma->obj;
519
+
520
+
GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
521
+
GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND));
522
+
523
+
drm_mm_remove_node(&vma->node);
524
+
list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
525
+
526
+
/* Since the unbound list is global, only move to that list if
527
+
* no more VMAs exist.
528
+
*/
529
+
if (--obj->bind_count == 0)
530
+
list_move_tail(&obj->global_link,
531
+
&to_i915(obj->base.dev)->mm.unbound_list);
532
+
533
+
/* And finally now the object is completely decoupled from this vma,
534
+
* we can drop its hold on the backing storage and allow it to be
535
+
* reaped by the shrinker.
536
+
*/
537
+
i915_gem_object_unpin_pages(obj);
538
+
GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
539
+
}
540
+
515
541
int __i915_vma_do_pin(struct i915_vma *vma,
516
542
u64 size, u64 alignment, u64 flags)
517
543
{
518
-
unsigned int bound = vma->flags;
544
+
const unsigned int bound = vma->flags;
519
545
int ret;
520
546
521
547
lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
···
550
524
551
525
if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) {
552
526
ret = -EBUSY;
553
-
goto err;
527
+
goto err_unpin;
554
528
}
555
529
556
530
if ((bound & I915_VMA_BIND_MASK) == 0) {
557
531
ret = i915_vma_insert(vma, size, alignment, flags);
558
532
if (ret)
559
-
goto err;
533
+
goto err_unpin;
560
534
}
561
535
562
536
ret = i915_vma_bind(vma, vma->obj->cache_level, flags);
563
537
if (ret)
564
-
goto err;
538
+
goto err_remove;
565
539
566
540
if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND)
567
541
__i915_vma_set_map_and_fenceable(vma);
···
570
544
GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags));
571
545
return 0;
572
546
573
-
err:
547
+
err_remove:
548
+
if ((bound & I915_VMA_BIND_MASK) == 0) {
549
+
GEM_BUG_ON(vma->pages);
550
+
i915_vma_remove(vma);
551
+
}
552
+
err_unpin:
574
553
__i915_vma_unpin(vma);
575
554
return ret;
576
555
}
···
688
657
}
689
658
vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND);
690
659
691
-
drm_mm_remove_node(&vma->node);
692
-
list_move_tail(&vma->vm_link, &vma->vm->unbound_list);
693
-
694
660
if (vma->pages != obj->mm.pages) {
695
661
GEM_BUG_ON(!vma->pages);
696
662
sg_free_table(vma->pages);
···
695
667
}
696
668
vma->pages = NULL;
697
669
698
-
/* Since the unbound list is global, only move to that list if
699
-
* no more VMAs exist. */
700
-
if (--obj->bind_count == 0)
701
-
list_move_tail(&obj->global_link,
702
-
&to_i915(obj->base.dev)->mm.unbound_list);
703
-
704
-
/* And finally now the object is completely decoupled from this vma,
705
-
* we can drop its hold on the backing storage and allow it to be
706
-
* reaped by the shrinker.
707
-
*/
708
-
i915_gem_object_unpin_pages(obj);
709
-
GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
670
+
i915_vma_remove(vma);
710
671
711
672
destroy:
712
673
if (unlikely(i915_vma_is_closed(vma)))
+29
-29
drivers/gpu/drm/i915/intel_display.c
+29
-29
drivers/gpu/drm/i915/intel_display.c
···
3669
3669
/* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3670
3670
crtc->base.mode = crtc->base.state->mode;
3671
3671
3672
-
DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3673
-
old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3674
-
pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3675
-
3676
3672
/*
3677
3673
* Update pipe size and adjust fitter if needed: the reason for this is
3678
3674
* that in compute_mode_changes we check the native mode (not the pfit
···
4792
4796
struct intel_crtc_scaler_state *scaler_state =
4793
4797
&crtc->config->scaler_state;
4794
4798
4795
-
DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4796
-
4797
4799
if (crtc->config->pch_pfit.enabled) {
4798
4800
int id;
4799
4801
4800
-
if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4801
-
DRM_ERROR("Requesting pfit without getting a scaler first\n");
4802
+
if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4802
4803
return;
4803
-
}
4804
4804
4805
4805
id = scaler_state->scaler_id;
4806
4806
I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4807
4807
PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4808
4808
I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4809
4809
I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4810
-
4811
-
DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4812
4810
}
4813
4811
}
4814
4812
···
14369
14379
} while (progress);
14370
14380
}
14371
14381
14382
+
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
14383
+
{
14384
+
struct intel_atomic_state *state, *next;
14385
+
struct llist_node *freed;
14386
+
14387
+
freed = llist_del_all(&dev_priv->atomic_helper.free_list);
14388
+
llist_for_each_entry_safe(state, next, freed, freed)
14389
+
drm_atomic_state_put(&state->base);
14390
+
}
14391
+
14392
+
static void intel_atomic_helper_free_state_worker(struct work_struct *work)
14393
+
{
14394
+
struct drm_i915_private *dev_priv =
14395
+
container_of(work, typeof(*dev_priv), atomic_helper.free_work);
14396
+
14397
+
intel_atomic_helper_free_state(dev_priv);
14398
+
}
14399
+
14372
14400
static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14373
14401
{
14374
14402
struct drm_device *dev = state->dev;
···
14553
14545
* can happen also when the device is completely off.
14554
14546
*/
14555
14547
intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14548
+
14549
+
intel_atomic_helper_free_state(dev_priv);
14556
14550
}
14557
14551
14558
14552
static void intel_atomic_commit_work(struct work_struct *work)
···
14956
14946
to_intel_atomic_state(old_crtc_state->state);
14957
14947
bool modeset = needs_modeset(crtc->state);
14958
14948
14949
+
if (!modeset &&
14950
+
(intel_cstate->base.color_mgmt_changed ||
14951
+
intel_cstate->update_pipe)) {
14952
+
intel_color_set_csc(crtc->state);
14953
+
intel_color_load_luts(crtc->state);
14954
+
}
14955
+
14959
14956
/* Perform vblank evasion around commit operation */
14960
14957
intel_pipe_update_start(intel_crtc);
14961
14958
14962
14959
if (modeset)
14963
14960
goto out;
14964
-
14965
-
if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14966
-
intel_color_set_csc(crtc->state);
14967
-
intel_color_load_luts(crtc->state);
14968
-
}
14969
14961
14970
14962
if (intel_cstate->update_pipe)
14971
14963
intel_update_pipe_config(intel_crtc, old_intel_cstate);
···
16611
16599
drm_modeset_acquire_fini(&ctx);
16612
16600
}
16613
16601
16614
-
static void intel_atomic_helper_free_state(struct work_struct *work)
16615
-
{
16616
-
struct drm_i915_private *dev_priv =
16617
-
container_of(work, typeof(*dev_priv), atomic_helper.free_work);
16618
-
struct intel_atomic_state *state, *next;
16619
-
struct llist_node *freed;
16620
-
16621
-
freed = llist_del_all(&dev_priv->atomic_helper.free_list);
16622
-
llist_for_each_entry_safe(state, next, freed, freed)
16623
-
drm_atomic_state_put(&state->base);
16624
-
}
16625
-
16626
16602
int intel_modeset_init(struct drm_device *dev)
16627
16603
{
16628
16604
struct drm_i915_private *dev_priv = to_i915(dev);
···
16631
16631
dev->mode_config.funcs = &intel_mode_funcs;
16632
16632
16633
16633
INIT_WORK(&dev_priv->atomic_helper.free_work,
16634
-
intel_atomic_helper_free_state);
16634
+
intel_atomic_helper_free_state_worker);
16635
16635
16636
16636
intel_init_quirks(dev);
16637
16637
+4
-6
drivers/gpu/drm/i915/intel_fbdev.c
+4
-6
drivers/gpu/drm/i915/intel_fbdev.c
···
357
357
bool *enabled, int width, int height)
358
358
{
359
359
struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
360
-
unsigned long conn_configured, mask;
360
+
unsigned long conn_configured, conn_seq, mask;
361
361
unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
362
362
int i, j;
363
363
bool *save_enabled;
364
364
bool fallback = true;
365
365
int num_connectors_enabled = 0;
366
366
int num_connectors_detected = 0;
367
-
int pass = 0;
368
367
369
368
save_enabled = kcalloc(count, sizeof(bool), GFP_KERNEL);
370
369
if (!save_enabled)
···
373
374
mask = BIT(count) - 1;
374
375
conn_configured = 0;
375
376
retry:
377
+
conn_seq = conn_configured;
376
378
for (i = 0; i < count; i++) {
377
379
struct drm_fb_helper_connector *fb_conn;
378
380
struct drm_connector *connector;
···
387
387
if (conn_configured & BIT(i))
388
388
continue;
389
389
390
-
if (pass == 0 && !connector->has_tile)
390
+
if (conn_seq == 0 && !connector->has_tile)
391
391
continue;
392
392
393
393
if (connector->status == connector_status_connected)
···
498
498
conn_configured |= BIT(i);
499
499
}
500
500
501
-
if ((conn_configured & mask) != mask) {
502
-
pass++;
501
+
if ((conn_configured & mask) != mask && conn_configured != conn_seq)
503
502
goto retry;
504
-
}
505
503
506
504
/*
507
505
* If the BIOS didn't enable everything it could, fall back to have the
+13
-5
drivers/gpu/drm/i915/intel_pm.c
+13
-5
drivers/gpu/drm/i915/intel_pm.c
···
4891
4891
break;
4892
4892
}
4893
4893
4894
+
/* When byt can survive without system hang with dynamic
4895
+
* sw freq adjustments, this restriction can be lifted.
4896
+
*/
4897
+
if (IS_VALLEYVIEW(dev_priv))
4898
+
goto skip_hw_write;
4899
+
4894
4900
I915_WRITE(GEN6_RP_UP_EI,
4895
4901
GT_INTERVAL_FROM_US(dev_priv, ei_up));
4896
4902
I915_WRITE(GEN6_RP_UP_THRESHOLD,
···
4917
4911
GEN6_RP_UP_BUSY_AVG |
4918
4912
GEN6_RP_DOWN_IDLE_AVG);
4919
4913
4914
+
skip_hw_write:
4920
4915
dev_priv->rps.power = new_power;
4921
4916
dev_priv->rps.up_threshold = threshold_up;
4922
4917
dev_priv->rps.down_threshold = threshold_down;
···
7923
7916
* @timeout_base_ms: timeout for polling with preemption enabled
7924
7917
*
7925
7918
* Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
7926
-
* reports an error or an overall timeout of @timeout_base_ms+10 ms expires.
7919
+
* reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
7927
7920
* The request is acknowledged once the PCODE reply dword equals @reply after
7928
7921
* applying @reply_mask. Polling is first attempted with preemption enabled
7929
-
* for @timeout_base_ms and if this times out for another 10 ms with
7922
+
* for @timeout_base_ms and if this times out for another 50 ms with
7930
7923
* preemption disabled.
7931
7924
*
7932
7925
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
···
7962
7955
* worst case) _and_ PCODE was busy for some reason even after a
7963
7956
* (queued) request and @timeout_base_ms delay. As a workaround retry
7964
7957
* the poll with preemption disabled to maximize the number of
7965
-
* requests. Increase the timeout from @timeout_base_ms to 10ms to
7958
+
* requests. Increase the timeout from @timeout_base_ms to 50ms to
7966
7959
* account for interrupts that could reduce the number of these
7967
-
* requests.
7960
+
* requests, and for any quirks of the PCODE firmware that delays
7961
+
* the request completion.
7968
7962
*/
7969
7963
DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
7970
7964
WARN_ON_ONCE(timeout_base_ms > 3);
7971
7965
preempt_disable();
7972
-
ret = wait_for_atomic(COND, 10);
7966
+
ret = wait_for_atomic(COND, 50);
7973
7967
preempt_enable();
7974
7968
7975
7969
out:
-3
drivers/gpu/drm/i915/intel_sprite.c
-3
drivers/gpu/drm/i915/intel_sprite.c
···
254
254
int scaler_id = plane_state->scaler_id;
255
255
const struct intel_scaler *scaler;
256
256
257
-
DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n",
258
-
plane_id, PS_PLANE_SEL(plane_id));
259
-
260
257
scaler = &crtc_state->scaler_state.scalers[scaler_id];
261
258
262
259
I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
+6
-7
drivers/gpu/drm/i915/intel_uncore.c
+6
-7
drivers/gpu/drm/i915/intel_uncore.c
···
119
119
120
120
for_each_fw_domain_masked(d, fw_domains, dev_priv)
121
121
fw_domain_wait_ack(d);
122
+
123
+
dev_priv->uncore.fw_domains_active |= fw_domains;
122
124
}
123
125
124
126
static void
···
132
130
fw_domain_put(d);
133
131
fw_domain_posting_read(d);
134
132
}
133
+
134
+
dev_priv->uncore.fw_domains_active &= ~fw_domains;
135
135
}
136
136
137
137
static void
···
244
240
if (WARN_ON(domain->wake_count == 0))
245
241
domain->wake_count++;
246
242
247
-
if (--domain->wake_count == 0) {
243
+
if (--domain->wake_count == 0)
248
244
dev_priv->uncore.funcs.force_wake_put(dev_priv, domain->mask);
249
-
dev_priv->uncore.fw_domains_active &= ~domain->mask;
250
-
}
251
245
252
246
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
253
247
···
456
454
fw_domains &= ~domain->mask;
457
455
}
458
456
459
-
if (fw_domains) {
457
+
if (fw_domains)
460
458
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
461
-
dev_priv->uncore.fw_domains_active |= fw_domains;
462
-
}
463
459
}
464
460
465
461
/**
···
968
968
fw_domain_arm_timer(domain);
969
969
970
970
dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
971
-
dev_priv->uncore.fw_domains_active |= fw_domains;
972
971
}
973
972
974
973
static inline void __force_wake_auto(struct drm_i915_private *dev_priv,
-3
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
-3
drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
+6
drivers/gpu/drm/radeon/si_dpm.c
+6
drivers/gpu/drm/radeon/si_dpm.c
···
2984
2984
(rdev->pdev->device == 0x6667)) {
2985
2985
max_sclk = 75000;
2986
2986
}
2987
+
} else if (rdev->family == CHIP_OLAND) {
2988
+
if ((rdev->pdev->device == 0x6604) &&
2989
+
(rdev->pdev->subsystem_vendor == 0x1028) &&
2990
+
(rdev->pdev->subsystem_device == 0x066F)) {
2991
+
max_sclk = 75000;
2992
+
}
2987
2993
}
2988
2994
2989
2995
if (rps->vce_active) {
+24
-13
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+24
-13
drivers/gpu/drm/tilcdc/tilcdc_crtc.c
···
464
464
{
465
465
struct drm_device *dev = crtc->dev;
466
466
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
467
+
unsigned long flags;
467
468
468
469
WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
469
470
mutex_lock(&tilcdc_crtc->enable_lock);
···
485
484
tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
486
485
LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
487
486
LCDC_PALETTE_LOAD_MODE_MASK);
487
+
488
+
/* There is no real chance for a race here as the time stamp
489
+
* is taken before the raster DMA is started. The spin-lock is
490
+
* taken to have a memory barrier after taking the time-stamp
491
+
* and to avoid a context switch between taking the stamp and
492
+
* enabling the raster.
493
+
*/
494
+
spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
495
+
tilcdc_crtc->last_vblank = ktime_get();
488
496
tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
497
+
spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
489
498
490
499
drm_crtc_vblank_on(crtc);
491
500
···
550
539
}
551
540
552
541
drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
553
-
tilcdc_crtc->last_vblank = 0;
554
542
555
543
tilcdc_crtc->enabled = false;
556
544
mutex_unlock(&tilcdc_crtc->enable_lock);
···
612
602
{
613
603
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
614
604
struct drm_device *dev = crtc->dev;
615
-
unsigned long flags;
616
605
617
606
WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
618
607
···
623
614
drm_framebuffer_reference(fb);
624
615
625
616
crtc->primary->fb = fb;
617
+
tilcdc_crtc->event = event;
626
618
627
-
spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
619
+
mutex_lock(&tilcdc_crtc->enable_lock);
628
620
629
-
if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
621
+
if (tilcdc_crtc->enabled) {
622
+
unsigned long flags;
630
623
ktime_t next_vblank;
631
624
s64 tdiff;
632
625
633
-
next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
634
-
1000000 / crtc->hwmode.vrefresh);
626
+
spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
635
627
628
+
next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
629
+
1000000 / crtc->hwmode.vrefresh);
636
630
tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
637
631
638
632
if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
639
633
tilcdc_crtc->next_fb = fb;
634
+
else
635
+
set_scanout(crtc, fb);
636
+
637
+
spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
640
638
}
641
639
642
-
if (tilcdc_crtc->next_fb != fb)
643
-
set_scanout(crtc, fb);
644
-
645
-
tilcdc_crtc->event = event;
646
-
647
-
spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
640
+
mutex_unlock(&tilcdc_crtc->enable_lock);
648
641
649
642
return 0;
650
643
}
···
1047
1036
1048
1037
fail:
1049
1038
tilcdc_crtc_destroy(crtc);
1050
-
return -ENOMEM;
1039
+
return ret;
1051
1040
}
+19
-19
include/uapi/drm/omap_drm.h
+19
-19
include/uapi/drm/omap_drm.h
···
33
33
#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */
34
34
35
35
struct drm_omap_param {
36
-
uint64_t param; /* in */
37
-
uint64_t value; /* in (set_param), out (get_param) */
36
+
__u64 param; /* in */
37
+
__u64 value; /* in (set_param), out (get_param) */
38
38
};
39
39
40
40
#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */
···
53
53
#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32)
54
54
55
55
union omap_gem_size {
56
-
uint32_t bytes; /* (for non-tiled formats) */
56
+
__u32 bytes; /* (for non-tiled formats) */
57
57
struct {
58
-
uint16_t width;
59
-
uint16_t height;
58
+
__u16 width;
59
+
__u16 height;
60
60
} tiled; /* (for tiled formats) */
61
61
};
62
62
63
63
struct drm_omap_gem_new {
64
64
union omap_gem_size size; /* in */
65
-
uint32_t flags; /* in */
66
-
uint32_t handle; /* out */
67
-
uint32_t __pad;
65
+
__u32 flags; /* in */
66
+
__u32 handle; /* out */
67
+
__u32 __pad;
68
68
};
69
69
70
70
/* mask of operations: */
···
74
74
};
75
75
76
76
struct drm_omap_gem_cpu_prep {
77
-
uint32_t handle; /* buffer handle (in) */
78
-
uint32_t op; /* mask of omap_gem_op (in) */
77
+
__u32 handle; /* buffer handle (in) */
78
+
__u32 op; /* mask of omap_gem_op (in) */
79
79
};
80
80
81
81
struct drm_omap_gem_cpu_fini {
82
-
uint32_t handle; /* buffer handle (in) */
83
-
uint32_t op; /* mask of omap_gem_op (in) */
82
+
__u32 handle; /* buffer handle (in) */
83
+
__u32 op; /* mask of omap_gem_op (in) */
84
84
/* TODO maybe here we pass down info about what regions are touched
85
85
* by sw so we can be clever about cache ops? For now a placeholder,
86
86
* set to zero and we just do full buffer flush..
87
87
*/
88
-
uint32_t nregions;
89
-
uint32_t __pad;
88
+
__u32 nregions;
89
+
__u32 __pad;
90
90
};
91
91
92
92
struct drm_omap_gem_info {
93
-
uint32_t handle; /* buffer handle (in) */
94
-
uint32_t pad;
95
-
uint64_t offset; /* mmap offset (out) */
93
+
__u32 handle; /* buffer handle (in) */
94
+
__u32 pad;
95
+
__u64 offset; /* mmap offset (out) */
96
96
/* note: in case of tiled buffers, the user virtual size can be
97
97
* different from the physical size (ie. how many pages are needed
98
98
* to back the object) which is returned in DRM_IOCTL_GEM_OPEN..
99
99
* This size here is the one that should be used if you want to
100
100
* mmap() the buffer:
101
101
*/
102
-
uint32_t size; /* virtual size for mmap'ing (out) */
103
-
uint32_t __pad;
102
+
__u32 size; /* virtual size for mmap'ing (out) */
103
+
__u32 __pad;
104
104
};
105
105
106
106
#define DRM_OMAP_GET_PARAM 0x00