+1 -1

drivers/iio/adc/ad4030.c

reviewed

··· 629 629 /* Add one byte if we are using a differential + common byte mode */ 630 630 bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM || 631 631 st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0; 632 632 - /* Mulitiply by the number of hardware channels */ 632 632 + /* Multiply by the number of hardware channels */ 633 633 bytes_to_read *= st->chip->num_voltage_inputs; 634 634 635 635 for (i = 0; i < cnv_nb; i++) {

+3 -3

drivers/iio/adc/ad4170-4.c

reviewed

··· 275 275 }; 276 276 277 277 enum ad4170_ref_buf { 278 278 - AD4170_REF_BUF_PRE, /* Pre-charge referrence buffer */ 279 279 - AD4170_REF_BUF_FULL, /* Full referrence buffering */ 280 280 - AD4170_REF_BUF_BYPASS, /* Bypass referrence buffering */ 278 278 + AD4170_REF_BUF_PRE, /* Pre-charge reference buffer */ 279 279 + AD4170_REF_BUF_FULL, /* Full reference buffering */ 280 280 + AD4170_REF_BUF_BYPASS, /* Bypass reference buffering */ 281 281 }; 282 282 283 283 /* maps adi,positive/negative-reference-buffer property values to enum */

+1 -1

drivers/iio/adc/ad7380.c

reviewed

··· 1862 1862 1863 1863 /* 1864 1864 * Starting with a quite low frequency, to allow oversampling x32, 1865 1865 - * user is then reponsible to adjust the frequency for the specific case. 1865 1865 + * user is then responsible to adjust the frequency for the specific case. 1866 1866 */ 1867 1867 ret = ad7380_set_sample_freq(st, sample_rate / 32); 1868 1868 if (ret)

+1 -1

drivers/iio/adc/ad7793.c

reviewed

··· 805 805 806 806 vref_mv = ret / 1000; 807 807 } else { 808 808 - vref_mv = 1170; /* Build-in ref */ 808 808 + vref_mv = 1170; /* Built-in ref */ 809 809 } 810 810 811 811 st->chip_info =

+1 -1

drivers/iio/adc/ad7887.c

reviewed

··· 104 104 { 105 105 struct ad7887_state *st = iio_priv(indio_dev); 106 106 107 107 - /* dummy read: restore default CH0 settin */ 107 107 + /* dummy read: restore default CH0 settings */ 108 108 return spi_sync(st->spi, &st->msg[AD7887_CH0]); 109 109 } 110 110

+2 -2

drivers/iio/adc/ad7923.c

reviewed

··· 30 30 #define AD7923_PM_MODE_AS (1) /* auto shutdown */ 31 31 #define AD7923_PM_MODE_FS (2) /* full shutdown */ 32 32 #define AD7923_PM_MODE_OPS (3) /* normal operation */ 33 33 - #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */ 33 33 + #define AD7923_SEQUENCE_OFF (0) /* no sequence function */ 34 34 #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */ 35 35 #define AD7923_SEQUENCE_ON (3) /* continuous sequence */ 36 36 ··· 39 39 #define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */ 40 40 #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \ 41 41 + (((sequence) & 2) << 9)) 42 42 - /* write sequence fonction */ 42 42 + /* write sequence function */ 43 43 /* left shift for CR : bit 11 transmit in first */ 44 44 #define AD7923_SHIFT_REGISTER 4 45 45

+1 -1

drivers/iio/adc/ade9000.c

reviewed

··· 1548 1548 1549 1549 ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts); 1550 1550 if (ret) { 1551 1551 - dev_err(dev, "Post-disable update maks0 fail\n"); 1551 1551 + dev_err(dev, "Post-disable update mask0 fail\n"); 1552 1552 return ret; 1553 1553 } 1554 1554

+1 -1

drivers/iio/adc/at91-sama5d2_adc.c

reviewed

··· 2507 2507 at91_adc_buffer_postdisable(indio_dev); 2508 2508 2509 2509 /* 2510 2510 - * Do a sofware reset of the ADC before we go to suspend. 2510 2510 + * Do a software reset of the ADC before we go to suspend. 2511 2511 * this will ensure that all pins are free from being muxed by the ADC 2512 2512 * and can be used by for other devices. 2513 2513 * Otherwise, ADC will hog them and we can't go to suspend mode.

+2 -2

drivers/iio/adc/at91_adc.c

reviewed

··· 171 171 }; 172 172 173 173 /** 174 174 - * struct at91_adc_reg_desc - Various informations relative to registers 174 174 + * struct at91_adc_reg_desc - Various information relative to registers 175 175 * @channel_base: Base offset for the channel data registers 176 176 * @drdy_mask: Mask of the DRDY field in the relevant registers 177 177 * (Interruptions registers mostly) ··· 231 231 struct iio_trigger **trig; 232 232 bool use_external; 233 233 u32 vref_mv; 234 234 - u32 res; /* resolution used for convertions */ 234 234 + u32 res; /* resolution used for conversions */ 235 235 wait_queue_head_t wq_data_avail; 236 236 const struct at91_adc_caps *caps; 237 237

+1 -1

drivers/iio/adc/fsl-imx25-gcq.c

reviewed

··· 47 47 * of register writes, then a wait for a completion callback, 48 48 * and finally a register read, during which userspace could issue 49 49 * another read request. This lock protects a read access from 50 50 - * ocurring before another one has finished. 50 50 + * occurring before another one has finished. 51 51 */ 52 52 struct mutex lock; 53 53 };

+1 -1

drivers/iio/adc/max1363.c

reviewed

··· 121 121 }; 122 122 123 123 /** 124 124 - * struct max1363_chip_info - chip specifc information 124 124 + * struct max1363_chip_info - chip specific information 125 125 * @info: iio core function callbacks structure 126 126 * @channels: channel specification 127 127 * @num_channels: number of channels

+1 -1

drivers/iio/adc/mcp3564.c

reviewed

··· 349 349 * struct mcp3564_state - working data for a ADC device 350 350 * @chip_info: chip specific data 351 351 * @spi: SPI device structure 352 352 - * @vref_mv: voltage reference value in miliVolts 352 352 + * @vref_mv: voltage reference value in millivolts 353 353 * @lock: synchronize access to driver's state members 354 354 * @dev_addr: hardware device address 355 355 * @oversampling: the index inside oversampling list of the ADC

+1 -1

drivers/iio/adc/men_z188_adc.c

reviewed

··· 1 1 // SPDX-License-Identifier: GPL-2.0-only 2 2 /* 3 3 - * MEN 16z188 Analog to Digial Converter 3 3 + * MEN 16z188 Analog to Digital Converter 4 4 * 5 5 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) 6 6 * Author: Johannes Thumshirn <johannes.thumshirn@men.de>

+1 -1

drivers/iio/adc/nau7802.c

reviewed

··· 257 257 /* 258 258 * Because there is actually only one ADC for both channels, we have to 259 259 * wait for enough conversions to happen before getting a significant 260 260 - * value when changing channels and the values are far appart. 260 260 + * value when changing channels and the values are far apart. 261 261 */ 262 262 do { 263 263 ret = i2c_smbus_read_byte_data(st->client, NAU7802_REG_PUCTRL);

+1 -1

drivers/iio/adc/npcm_adc.c

reviewed

··· 38 38 * read access from userspace. Reading a raw value requires a sequence 39 39 * of register writes, then a wait for a event and finally a register 40 40 * read, during which userspace could issue another read request. 41 41 - * This lock protects a read access from ocurring before another one 41 41 + * This lock protects a read access from occurring before another one 42 42 * has finished. 43 43 */ 44 44 struct mutex lock;

+1 -1

drivers/iio/adc/pac1921.c

reviewed

··· 856 856 /* 857 857 * Read available scales for a specific channel 858 858 * 859 859 - * NOTE: using extended info insted of iio.read_avail() because access to 859 859 + * NOTE: using extended info instead of iio.read_avail() because access to 860 860 * current scales must be locked as they depend on shunt resistor which may 861 861 * change runtime. Caller of iio.read_avail() would access the table unlocked 862 862 * instead.

+1 -1

drivers/iio/adc/palmas_gpadc.c

reviewed

··· 105 105 * of register writes, then a wait for a completion callback, 106 106 * and finally a register read, during which userspace could issue 107 107 * another read request. This lock protects a read access from 108 108 - * ocurring before another one has finished. 108 108 + * occurring before another one has finished. 109 109 * 110 110 * This is the palmas_gpadc structure to store run-time information 111 111 * and pointers for this driver instance.

+2 -2

drivers/iio/adc/rohm-bd79124.c

reviewed

··· 75 75 76 76 /* 77 77 * The high limit, low limit and last measurement result are each stored in 78 78 - * 2 consequtive registers. 4 bits are in the high bits of the first register 78 78 + * 2 consecutive registers. 4 bits are in the high bits of the first register 79 79 * and 8 bits in the next register. 80 80 * 81 81 * These macros return the address of the first reg for the given channel. ··· 962 962 if (ret) 963 963 return ret; 964 964 965 965 - /* Enable writing the measured values to the regsters */ 965 965 + /* Enable writing the measured values to the registers */ 966 966 ret = regmap_set_bits(data->map, BD79124_REG_GEN_CFG, 967 967 BD79124_MSK_STATS_EN); 968 968 if (ret)

+1 -1

drivers/iio/adc/spear_adc.c

reviewed

··· 82 82 * of register writes, then a wait for a completion callback, 83 83 * and finally a register read, during which userspace could issue 84 84 * another read request. This lock protects a read access from 85 85 - * ocurring before another one has finished. 85 85 + * occurring before another one has finished. 86 86 */ 87 87 struct mutex lock; 88 88 u32 current_clk;

+1 -1

drivers/iio/adc/stm32-adc-core.c

reviewed

··· 227 227 if (priv->aclk) { 228 228 /* 229 229 * Asynchronous clock modes (e.g. ckmode == 0) 230 230 - * From spec: PLL output musn't exceed max rate 230 230 + * From spec: PLL output mustn't exceed max rate 231 231 */ 232 232 rate = clk_get_rate(priv->aclk); 233 233 if (!rate) {

+1 -1

drivers/iio/adc/stm32-adc.c

reviewed

··· 1662 1662 /* 1663 1663 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1664 1664 * This requires to stop ADC first. OVR bit state in ISR, 1665 1665 - * is propaged to CSR register by hardware. 1665 1665 + * is propagated to CSR register by hardware. 1666 1666 */ 1667 1667 adc->cfg->stop_conv(indio_dev); 1668 1668 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask);

+1 -1

drivers/iio/adc/sun20i-gpadc-iio.c

reviewed

··· 55 55 * of register writes, then a wait for a completion callback, 56 56 * and finally a register read, during which userspace could issue 57 57 * another read request. This lock protects a read access from 58 58 - * ocurring before another one has finished. 58 58 + * occurring before another one has finished. 59 59 */ 60 60 struct mutex lock; 61 61 };

+1 -1

drivers/iio/adc/twl4030-madc.c

reviewed

··· 252 252 {5, 11}, /* CHANNEL 15 */ 253 253 }; 254 254 255 255 - /* Conversion table from -3 to 55 degrees Celcius */ 255 255 + /* Conversion table from -3 to 55 degrees Celsius */ 256 256 static int twl4030_therm_tbl[] = { 257 257 30800, 29500, 28300, 27100, 258 258 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700,

+1 -1

drivers/iio/adc/twl6030-gpadc.c

reviewed

··· 416 416 { 417 417 /* 418 418 * for any prior chosen channel, when the conversion is ready 419 419 - * the result is avalable in GPCH0_LSB, GPCH0_MSB. 419 419 + * the result is available in GPCH0_LSB, GPCH0_MSB. 420 420 */ 421 421 422 422 return TWL6032_GPADC_GPCH0_LSB;