Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'pci/dt-bindings'
- Update socionext,uniphier-pcie binding pcie_intc name to
'legacy-interrupt-controller' to match .dts files (Rob Herring)
- Merge SC8180x binding into SM8150 (Krzysztof Kozlowski)
- Move SDX55, SDM845, QCS404, IPQ5018, IPQ6018, IPQ8074 Gen3, IPQ8074,
IPQ4019, IPQ9574, APQ8064, MSM8996, APQ8084 to dedicated schema
(Krzysztof Kozlowski)
- Add MT7981 compatible to mediatek-pcie-gen3 binding (Sjoerd Simons)
- Document Loongson msi-parent property (Yao Zi)
- Add Glymur compatible to qcom,pcie-x1e80100 binding (Prudhvi Yarlagadda)
* pci/dt-bindings:
dt-bindings: PCI: qcom: Document the Glymur PCIe Controller
dt-bindings: PCI: loongson: Document msi-parent property
dt-bindings: PCI: mediatek-gen3: Add MT7981 PCIe compatible
dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema
dt-bindings: PCI: qcom,pcie-msm8996: Move MSM8996 to dedicated schema
dt-bindings: PCI: qcom,pcie-apq8064: Move APQ8064 to dedicated schema
dt-bindings: PCI: qcom,pcie-ipq9574: Move IPQ9574 to dedicated schema
dt-bindings: PCI: qcom,pcie-ipq4019: Move IPQ4019 to dedicated schema
dt-bindings: PCI: qcom,pcie-ipq8074: Move IPQ8074 to dedicated schema
dt-bindings: PCI: qcom,pcie-ipq6018: Move IPQ6018 and IPQ8074 Gen3 to dedicated schema
dt-bindings: PCI: qcom,pcie-ipq5018: Move IPQ5018 to dedicated schema
dt-bindings: PCI: qcom,pcie-qcs404: Move QCS404 to dedicated schema
dt-bindings: PCI: qcom,pcie-sdm845: Move SDM845 to dedicated schema
dt-bindings: PCI: qcom,pcie-sdx55: Move SDX55 to dedicated schema
dt-bindings: PCI: qcom,pcie-sm8150: Merge SC8180x into SM8150
dt-bindings: PCI: socionext,uniphier-pcie: Fix interrupt controller node name
+1802
-953
+2
Documentation/devicetree/bindings/pci/loongson.yaml
+2
Documentation/devicetree/bindings/pci/loongson.yaml
+1
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+1
Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+170
Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml
+170
Documentation/devicetree/bindings/pci/qcom,pcie-apq8064.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8064.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm APQ8064/IPQ8064 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-apq8064
17
+
- qcom,pcie-ipq8064
18
+
- qcom,pcie-ipq8064-v2
19
+
20
+
reg:
21
+
maxItems: 4
22
+
23
+
reg-names:
24
+
items:
25
+
- const: dbi
26
+
- const: elbi
27
+
- const: parf
28
+
- const: config
29
+
30
+
clocks:
31
+
minItems: 3
32
+
maxItems: 5
33
+
34
+
clock-names:
35
+
minItems: 3
36
+
items:
37
+
- const: core # Clocks the pcie hw block
38
+
- const: iface # Configuration AHB clock
39
+
- const: phy
40
+
- const: aux
41
+
- const: ref
42
+
43
+
interrupts:
44
+
maxItems: 1
45
+
46
+
interrupt-names:
47
+
items:
48
+
- const: msi
49
+
50
+
resets:
51
+
minItems: 5
52
+
maxItems: 6
53
+
54
+
reset-names:
55
+
minItems: 5
56
+
items:
57
+
- const: axi
58
+
- const: ahb
59
+
- const: por
60
+
- const: pci
61
+
- const: phy
62
+
- const: ext
63
+
64
+
vdda-supply:
65
+
description: A phandle to the core analog power supply
66
+
67
+
vdda_phy-supply:
68
+
description: A phandle to the core analog power supply for PHY
69
+
70
+
vdda_refclk-supply:
71
+
description: A phandle to the core analog power supply for IC which generates reference clock
72
+
73
+
required:
74
+
- resets
75
+
- reset-names
76
+
- vdda-supply
77
+
- vdda_phy-supply
78
+
- vdda_refclk-supply
79
+
80
+
allOf:
81
+
- $ref: qcom,pcie-common.yaml#
82
+
- if:
83
+
properties:
84
+
compatible:
85
+
contains:
86
+
enum:
87
+
- qcom,pcie-apq8064
88
+
then:
89
+
properties:
90
+
clocks:
91
+
maxItems: 3
92
+
clock-names:
93
+
maxItems: 3
94
+
resets:
95
+
maxItems: 5
96
+
reset-names:
97
+
maxItems: 5
98
+
else:
99
+
properties:
100
+
clocks:
101
+
minItems: 5
102
+
clock-names:
103
+
minItems: 5
104
+
resets:
105
+
minItems: 6
106
+
reset-names:
107
+
minItems: 6
108
+
109
+
unevaluatedProperties: false
110
+
111
+
examples:
112
+
- |
113
+
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
114
+
#include <dt-bindings/gpio/gpio.h>
115
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
116
+
#include <dt-bindings/reset/qcom,gcc-msm8960.h>
117
+
118
+
pcie@1b500000 {
119
+
compatible = "qcom,pcie-apq8064";
120
+
reg = <0x1b500000 0x1000>,
121
+
<0x1b502000 0x80>,
122
+
<0x1b600000 0x100>,
123
+
<0x0ff00000 0x100000>;
124
+
reg-names = "dbi", "elbi", "parf", "config";
125
+
ranges = <0x81000000 0x0 0x00000000 0x0fe00000 0x0 0x00100000>, /* I/O */
126
+
<0x82000000 0x0 0x08000000 0x08000000 0x0 0x07e00000>; /* mem */
127
+
128
+
device_type = "pci";
129
+
linux,pci-domain = <0>;
130
+
bus-range = <0x00 0xff>;
131
+
num-lanes = <1>;
132
+
#address-cells = <3>;
133
+
#size-cells = <2>;
134
+
135
+
clocks = <&gcc PCIE_A_CLK>,
136
+
<&gcc PCIE_H_CLK>,
137
+
<&gcc PCIE_PHY_REF_CLK>;
138
+
clock-names = "core", "iface", "phy";
139
+
140
+
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
141
+
interrupt-names = "msi";
142
+
#interrupt-cells = <1>;
143
+
interrupt-map-mask = <0 0 0 0x7>;
144
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
145
+
<0 0 0 2 &intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
146
+
<0 0 0 3 &intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
147
+
<0 0 0 4 &intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
148
+
149
+
resets = <&gcc PCIE_ACLK_RESET>,
150
+
<&gcc PCIE_HCLK_RESET>,
151
+
<&gcc PCIE_POR_RESET>,
152
+
<&gcc PCIE_PCI_RESET>,
153
+
<&gcc PCIE_PHY_RESET>;
154
+
reset-names = "axi", "ahb", "por", "pci", "phy";
155
+
156
+
perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>;
157
+
vdda-supply = <&pm8921_s3>;
158
+
vdda_phy-supply = <&pm8921_lvs6>;
159
+
vdda_refclk-supply = <&v3p3_fixed>;
160
+
161
+
pcie@0 {
162
+
device_type = "pci";
163
+
reg = <0x0 0x0 0x0 0x0 0x0>;
164
+
bus-range = <0x01 0xff>;
165
+
166
+
#address-cells = <3>;
167
+
#size-cells = <2>;
168
+
ranges;
169
+
};
170
+
};
+109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
+109
Documentation/devicetree/bindings/pci/qcom,pcie-apq8084.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm APQ8084 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-apq8084
17
+
18
+
reg:
19
+
minItems: 4
20
+
maxItems: 5
21
+
22
+
reg-names:
23
+
minItems: 4
24
+
items:
25
+
- const: parf
26
+
- const: dbi
27
+
- const: elbi
28
+
- const: config
29
+
- const: mhi
30
+
31
+
clocks:
32
+
maxItems: 4
33
+
34
+
clock-names:
35
+
items:
36
+
- const: iface # Configuration AHB clock
37
+
- const: master_bus # Master AXI clock
38
+
- const: slave_bus # Slave AXI clock
39
+
- const: aux
40
+
41
+
interrupts:
42
+
maxItems: 1
43
+
44
+
interrupt-names:
45
+
items:
46
+
- const: msi
47
+
48
+
resets:
49
+
maxItems: 1
50
+
51
+
reset-names:
52
+
items:
53
+
- const: core
54
+
55
+
vdda-supply:
56
+
description: A phandle to the core analog power supply
57
+
58
+
required:
59
+
- power-domains
60
+
- resets
61
+
- reset-names
62
+
63
+
allOf:
64
+
- $ref: qcom,pcie-common.yaml#
65
+
66
+
unevaluatedProperties: false
67
+
68
+
examples:
69
+
- |
70
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
71
+
#include <dt-bindings/gpio/gpio.h>
72
+
pcie@fc520000 {
73
+
compatible = "qcom,pcie-apq8084";
74
+
reg = <0xfc520000 0x2000>,
75
+
<0xff000000 0x1000>,
76
+
<0xff001000 0x1000>,
77
+
<0xff002000 0x2000>;
78
+
reg-names = "parf", "dbi", "elbi", "config";
79
+
device_type = "pci";
80
+
linux,pci-domain = <0>;
81
+
bus-range = <0x00 0xff>;
82
+
num-lanes = <1>;
83
+
#address-cells = <3>;
84
+
#size-cells = <2>;
85
+
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
86
+
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
87
+
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
88
+
interrupt-names = "msi";
89
+
#interrupt-cells = <1>;
90
+
interrupt-map-mask = <0 0 0 0x7>;
91
+
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
92
+
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
93
+
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
94
+
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
95
+
clocks = <&gcc 324>,
96
+
<&gcc 325>,
97
+
<&gcc 327>,
98
+
<&gcc 323>;
99
+
clock-names = "iface", "master_bus", "slave_bus", "aux";
100
+
resets = <&gcc 81>;
101
+
reset-names = "core";
102
+
power-domains = <&gcc 1>;
103
+
vdda-supply = <&pma8084_l3>;
104
+
phys = <&pciephy0>;
105
+
phy-names = "pciephy";
106
+
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
107
+
pinctrl-0 = <&pcie0_pins_default>;
108
+
pinctrl-names = "default";
109
+
};
+146
Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml
+146
Documentation/devicetree/bindings/pci/qcom,pcie-ipq4019.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq4019.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ4019 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-ipq4019
17
+
18
+
reg:
19
+
maxItems: 4
20
+
21
+
reg-names:
22
+
items:
23
+
- const: dbi
24
+
- const: elbi
25
+
- const: parf
26
+
- const: config
27
+
28
+
clocks:
29
+
maxItems: 3
30
+
31
+
clock-names:
32
+
items:
33
+
- const: aux
34
+
- const: master_bus # Master AXI clock
35
+
- const: slave_bus # Slave AXI clock
36
+
37
+
interrupts:
38
+
maxItems: 1
39
+
40
+
interrupt-names:
41
+
items:
42
+
- const: msi
43
+
44
+
resets:
45
+
maxItems: 12
46
+
47
+
reset-names:
48
+
items:
49
+
- const: axi_m # AXI master reset
50
+
- const: axi_s # AXI slave reset
51
+
- const: pipe
52
+
- const: axi_m_vmid
53
+
- const: axi_s_xpu
54
+
- const: parf
55
+
- const: phy
56
+
- const: axi_m_sticky # AXI master sticky reset
57
+
- const: pipe_sticky
58
+
- const: pwr
59
+
- const: ahb
60
+
- const: phy_ahb
61
+
62
+
required:
63
+
- resets
64
+
- reset-names
65
+
66
+
allOf:
67
+
- $ref: qcom,pcie-common.yaml#
68
+
69
+
unevaluatedProperties: false
70
+
71
+
examples:
72
+
- |
73
+
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
74
+
#include <dt-bindings/gpio/gpio.h>
75
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
76
+
77
+
pcie@40000000 {
78
+
compatible = "qcom,pcie-ipq4019";
79
+
reg = <0x40000000 0xf1d>,
80
+
<0x40000f20 0xa8>,
81
+
<0x80000 0x2000>,
82
+
<0x40100000 0x1000>;
83
+
reg-names = "dbi", "elbi", "parf", "config";
84
+
ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>,
85
+
<0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>;
86
+
87
+
device_type = "pci";
88
+
linux,pci-domain = <0>;
89
+
bus-range = <0x00 0xff>;
90
+
num-lanes = <1>;
91
+
#address-cells = <3>;
92
+
#size-cells = <2>;
93
+
94
+
clocks = <&gcc GCC_PCIE_AHB_CLK>,
95
+
<&gcc GCC_PCIE_AXI_M_CLK>,
96
+
<&gcc GCC_PCIE_AXI_S_CLK>;
97
+
clock-names = "aux",
98
+
"master_bus",
99
+
"slave_bus";
100
+
101
+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
102
+
interrupt-names = "msi";
103
+
#interrupt-cells = <1>;
104
+
interrupt-map-mask = <0 0 0 0x7>;
105
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
106
+
<0 0 0 2 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
107
+
<0 0 0 3 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
108
+
<0 0 0 4 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
109
+
110
+
resets = <&gcc PCIE_AXI_M_ARES>,
111
+
<&gcc PCIE_AXI_S_ARES>,
112
+
<&gcc PCIE_PIPE_ARES>,
113
+
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
114
+
<&gcc PCIE_AXI_S_XPU_ARES>,
115
+
<&gcc PCIE_PARF_XPU_ARES>,
116
+
<&gcc PCIE_PHY_ARES>,
117
+
<&gcc PCIE_AXI_M_STICKY_ARES>,
118
+
<&gcc PCIE_PIPE_STICKY_ARES>,
119
+
<&gcc PCIE_PWR_ARES>,
120
+
<&gcc PCIE_AHB_ARES>,
121
+
<&gcc PCIE_PHY_AHB_ARES>;
122
+
reset-names = "axi_m",
123
+
"axi_s",
124
+
"pipe",
125
+
"axi_m_vmid",
126
+
"axi_s_xpu",
127
+
"parf",
128
+
"phy",
129
+
"axi_m_sticky",
130
+
"pipe_sticky",
131
+
"pwr",
132
+
"ahb",
133
+
"phy_ahb";
134
+
135
+
perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
136
+
137
+
pcie@0 {
138
+
device_type = "pci";
139
+
reg = <0x0 0x0 0x0 0x0 0x0>;
140
+
bus-range = <0x01 0xff>;
141
+
142
+
#address-cells = <3>;
143
+
#size-cells = <2>;
144
+
ranges;
145
+
};
146
+
};
+189
Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml
+189
Documentation/devicetree/bindings/pci/qcom,pcie-ipq5018.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq5018.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ5018 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-ipq5018
17
+
18
+
reg:
19
+
minItems: 5
20
+
maxItems: 6
21
+
22
+
reg-names:
23
+
minItems: 5
24
+
items:
25
+
- const: dbi
26
+
- const: elbi
27
+
- const: atu
28
+
- const: parf
29
+
- const: config
30
+
- const: mhi
31
+
32
+
clocks:
33
+
maxItems: 6
34
+
35
+
clock-names:
36
+
items:
37
+
- const: iface # PCIe to SysNOC BIU clock
38
+
- const: axi_m # AXI Master clock
39
+
- const: axi_s # AXI Slave clock
40
+
- const: ahb
41
+
- const: aux
42
+
- const: axi_bridge
43
+
44
+
interrupts:
45
+
maxItems: 9
46
+
47
+
interrupt-names:
48
+
items:
49
+
- const: msi0
50
+
- const: msi1
51
+
- const: msi2
52
+
- const: msi3
53
+
- const: msi4
54
+
- const: msi5
55
+
- const: msi6
56
+
- const: msi7
57
+
- const: global
58
+
59
+
resets:
60
+
maxItems: 8
61
+
62
+
reset-names:
63
+
items:
64
+
- const: pipe
65
+
- const: sleep
66
+
- const: sticky # Core sticky reset
67
+
- const: axi_m # AXI master reset
68
+
- const: axi_s # AXI slave reset
69
+
- const: ahb
70
+
- const: axi_m_sticky # AXI master sticky reset
71
+
- const: axi_s_sticky # AXI slave sticky reset
72
+
73
+
required:
74
+
- resets
75
+
- reset-names
76
+
77
+
allOf:
78
+
- $ref: qcom,pcie-common.yaml#
79
+
80
+
unevaluatedProperties: false
81
+
82
+
examples:
83
+
- |
84
+
#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
85
+
#include <dt-bindings/gpio/gpio.h>
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
88
+
89
+
pcie@a0000000 {
90
+
compatible = "qcom,pcie-ipq5018";
91
+
reg = <0xa0000000 0xf1d>,
92
+
<0xa0000f20 0xa8>,
93
+
<0xa0001000 0x1000>,
94
+
<0x00080000 0x3000>,
95
+
<0xa0100000 0x1000>,
96
+
<0x00083000 0x1000>;
97
+
reg-names = "dbi",
98
+
"elbi",
99
+
"atu",
100
+
"parf",
101
+
"config",
102
+
"mhi";
103
+
ranges = <0x01000000 0 0x00000000 0xa0200000 0 0x00100000>,
104
+
<0x02000000 0 0xa0300000 0xa0300000 0 0x10000000>;
105
+
106
+
device_type = "pci";
107
+
linux,pci-domain = <0>;
108
+
bus-range = <0x00 0xff>;
109
+
num-lanes = <2>;
110
+
#address-cells = <3>;
111
+
#size-cells = <2>;
112
+
113
+
/* The controller supports Gen3, but the connected PHY is Gen2-capable */
114
+
max-link-speed = <2>;
115
+
116
+
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
117
+
<&gcc GCC_PCIE0_AXI_M_CLK>,
118
+
<&gcc GCC_PCIE0_AXI_S_CLK>,
119
+
<&gcc GCC_PCIE0_AHB_CLK>,
120
+
<&gcc GCC_PCIE0_AUX_CLK>,
121
+
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>;
122
+
clock-names = "iface",
123
+
"axi_m",
124
+
"axi_s",
125
+
"ahb",
126
+
"aux",
127
+
"axi_bridge";
128
+
129
+
msi-map = <0x0 &v2m0 0x0 0xff8>;
130
+
131
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
132
+
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
133
+
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
134
+
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
135
+
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
136
+
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
137
+
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
138
+
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
139
+
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
140
+
interrupt-names = "msi0",
141
+
"msi1",
142
+
"msi2",
143
+
"msi3",
144
+
"msi4",
145
+
"msi5",
146
+
"msi6",
147
+
"msi7",
148
+
"global";
149
+
150
+
#interrupt-cells = <1>;
151
+
interrupt-map-mask = <0 0 0 0x7>;
152
+
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
153
+
<0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
154
+
<0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
155
+
<0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
156
+
157
+
phys = <&pcie0_phy>;
158
+
phy-names = "pciephy";
159
+
160
+
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
161
+
<&gcc GCC_PCIE0_SLEEP_ARES>,
162
+
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
163
+
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
164
+
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
165
+
<&gcc GCC_PCIE0_AHB_ARES>,
166
+
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
167
+
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
168
+
reset-names = "pipe",
169
+
"sleep",
170
+
"sticky",
171
+
"axi_m",
172
+
"axi_s",
173
+
"ahb",
174
+
"axi_m_sticky",
175
+
"axi_s_sticky";
176
+
177
+
perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
178
+
wake-gpios = <&tlmm 16 GPIO_ACTIVE_LOW>;
179
+
180
+
pcie@0 {
181
+
device_type = "pci";
182
+
reg = <0x0 0x0 0x0 0x0 0x0>;
183
+
bus-range = <0x01 0xff>;
184
+
185
+
#address-cells = <3>;
186
+
#size-cells = <2>;
187
+
ranges;
188
+
};
189
+
};
+179
Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml
+179
Documentation/devicetree/bindings/pci/qcom,pcie-ipq6018.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq6018.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ6018 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-ipq6018
17
+
- qcom,pcie-ipq8074-gen3
18
+
19
+
reg:
20
+
minItems: 5
21
+
maxItems: 6
22
+
23
+
reg-names:
24
+
minItems: 5
25
+
items:
26
+
- const: dbi
27
+
- const: elbi
28
+
- const: atu
29
+
- const: parf
30
+
- const: config
31
+
- const: mhi
32
+
33
+
clocks:
34
+
maxItems: 5
35
+
36
+
clock-names:
37
+
items:
38
+
- const: iface # PCIe to SysNOC BIU clock
39
+
- const: axi_m # AXI Master clock
40
+
- const: axi_s # AXI Slave clock
41
+
- const: axi_bridge
42
+
- const: rchng
43
+
44
+
interrupts:
45
+
maxItems: 9
46
+
47
+
interrupt-names:
48
+
items:
49
+
- const: msi0
50
+
- const: msi1
51
+
- const: msi2
52
+
- const: msi3
53
+
- const: msi4
54
+
- const: msi5
55
+
- const: msi6
56
+
- const: msi7
57
+
- const: global
58
+
59
+
resets:
60
+
maxItems: 8
61
+
62
+
reset-names:
63
+
items:
64
+
- const: pipe
65
+
- const: sleep
66
+
- const: sticky # Core sticky reset
67
+
- const: axi_m # AXI master reset
68
+
- const: axi_s # AXI slave reset
69
+
- const: ahb
70
+
- const: axi_m_sticky # AXI master sticky reset
71
+
- const: axi_s_sticky # AXI slave sticky reset
72
+
73
+
required:
74
+
- resets
75
+
- reset-names
76
+
77
+
allOf:
78
+
- $ref: qcom,pcie-common.yaml#
79
+
80
+
unevaluatedProperties: false
81
+
82
+
examples:
83
+
- |
84
+
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
85
+
#include <dt-bindings/gpio/gpio.h>
86
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
87
+
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
88
+
89
+
soc {
90
+
#address-cells = <2>;
91
+
#size-cells = <2>;
92
+
93
+
pcie@20000000 {
94
+
compatible = "qcom,pcie-ipq6018";
95
+
reg = <0x0 0x20000000 0x0 0xf1d>,
96
+
<0x0 0x20000f20 0x0 0xa8>,
97
+
<0x0 0x20001000 0x0 0x1000>,
98
+
<0x0 0x80000 0x0 0x4000>,
99
+
<0x0 0x20100000 0x0 0x1000>;
100
+
reg-names = "dbi", "elbi", "atu", "parf", "config";
101
+
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
102
+
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
103
+
104
+
device_type = "pci";
105
+
linux,pci-domain = <0>;
106
+
bus-range = <0x00 0xff>;
107
+
num-lanes = <1>;
108
+
max-link-speed = <3>;
109
+
#address-cells = <3>;
110
+
#size-cells = <2>;
111
+
112
+
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
113
+
<&gcc GCC_PCIE0_AXI_M_CLK>,
114
+
<&gcc GCC_PCIE0_AXI_S_CLK>,
115
+
<&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
116
+
<&gcc PCIE0_RCHNG_CLK>;
117
+
clock-names = "iface",
118
+
"axi_m",
119
+
"axi_s",
120
+
"axi_bridge",
121
+
"rchng";
122
+
123
+
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
124
+
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
125
+
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
126
+
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
127
+
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
128
+
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
129
+
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
130
+
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
131
+
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
132
+
interrupt-names = "msi0",
133
+
"msi1",
134
+
"msi2",
135
+
"msi3",
136
+
"msi4",
137
+
"msi5",
138
+
"msi6",
139
+
"msi7",
140
+
"global";
141
+
142
+
#interrupt-cells = <1>;
143
+
interrupt-map-mask = <0 0 0 0x7>;
144
+
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
145
+
<0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
146
+
<0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
147
+
<0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
148
+
149
+
phys = <&pcie_phy>;
150
+
phy-names = "pciephy";
151
+
152
+
resets = <&gcc GCC_PCIE0_PIPE_ARES>,
153
+
<&gcc GCC_PCIE0_SLEEP_ARES>,
154
+
<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
155
+
<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
156
+
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
157
+
<&gcc GCC_PCIE0_AHB_ARES>,
158
+
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
159
+
<&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
160
+
reset-names = "pipe",
161
+
"sleep",
162
+
"sticky",
163
+
"axi_m",
164
+
"axi_s",
165
+
"ahb",
166
+
"axi_m_sticky",
167
+
"axi_s_sticky";
168
+
169
+
pcie@0 {
170
+
device_type = "pci";
171
+
reg = <0x0 0x0 0x0 0x0 0x0>;
172
+
bus-range = <0x01 0xff>;
173
+
174
+
#address-cells = <3>;
175
+
#size-cells = <2>;
176
+
ranges;
177
+
};
178
+
};
179
+
};
+165
Documentation/devicetree/bindings/pci/qcom,pcie-ipq8074.yaml
+165
Documentation/devicetree/bindings/pci/qcom,pcie-ipq8074.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq8074.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ8074 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-ipq8074
17
+
18
+
reg:
19
+
maxItems: 4
20
+
21
+
reg-names:
22
+
items:
23
+
- const: dbi
24
+
- const: elbi
25
+
- const: parf
26
+
- const: config
27
+
28
+
clocks:
29
+
maxItems: 5
30
+
31
+
clock-names:
32
+
items:
33
+
- const: iface # PCIe to SysNOC BIU clock
34
+
- const: axi_m # AXI Master clock
35
+
- const: axi_s # AXI Slave clock
36
+
- const: ahb
37
+
- const: aux
38
+
39
+
interrupts:
40
+
maxItems: 9
41
+
42
+
interrupt-names:
43
+
items:
44
+
- const: msi0
45
+
- const: msi1
46
+
- const: msi2
47
+
- const: msi3
48
+
- const: msi4
49
+
- const: msi5
50
+
- const: msi6
51
+
- const: msi7
52
+
- const: global
53
+
54
+
resets:
55
+
maxItems: 7
56
+
57
+
reset-names:
58
+
items:
59
+
- const: pipe
60
+
- const: sleep
61
+
- const: sticky # Core sticky reset
62
+
- const: axi_m # AXI master reset
63
+
- const: axi_s # AXI slave reset
64
+
- const: ahb
65
+
- const: axi_m_sticky # AXI master sticky reset
66
+
67
+
required:
68
+
- resets
69
+
- reset-names
70
+
71
+
allOf:
72
+
- $ref: qcom,pcie-common.yaml#
73
+
74
+
unevaluatedProperties: false
75
+
76
+
examples:
77
+
- |
78
+
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
79
+
#include <dt-bindings/gpio/gpio.h>
80
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
81
+
82
+
pcie@10000000 {
83
+
compatible = "qcom,pcie-ipq8074";
84
+
reg = <0x10000000 0xf1d>,
85
+
<0x10000f20 0xa8>,
86
+
<0x00088000 0x2000>,
87
+
<0x10100000 0x1000>;
88
+
reg-names = "dbi", "elbi", "parf", "config";
89
+
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
90
+
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
91
+
92
+
device_type = "pci";
93
+
linux,pci-domain = <1>;
94
+
bus-range = <0x00 0xff>;
95
+
num-lanes = <1>;
96
+
max-link-speed = <2>;
97
+
#address-cells = <3>;
98
+
#size-cells = <2>;
99
+
100
+
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
101
+
<&gcc GCC_PCIE1_AXI_M_CLK>,
102
+
<&gcc GCC_PCIE1_AXI_S_CLK>,
103
+
<&gcc GCC_PCIE1_AHB_CLK>,
104
+
<&gcc GCC_PCIE1_AUX_CLK>;
105
+
clock-names = "iface",
106
+
"axi_m",
107
+
"axi_s",
108
+
"ahb",
109
+
"aux";
110
+
111
+
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
112
+
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
113
+
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
114
+
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
115
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
116
+
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
117
+
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
118
+
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
119
+
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
120
+
interrupt-names = "msi0",
121
+
"msi1",
122
+
"msi2",
123
+
"msi3",
124
+
"msi4",
125
+
"msi5",
126
+
"msi6",
127
+
"msi7",
128
+
"global";
129
+
#interrupt-cells = <1>;
130
+
interrupt-map-mask = <0 0 0 0x7>;
131
+
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
132
+
<0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
133
+
<0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
134
+
<0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
135
+
136
+
phys = <&pcie_qmp1>;
137
+
phy-names = "pciephy";
138
+
139
+
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
140
+
<&gcc GCC_PCIE1_SLEEP_ARES>,
141
+
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
142
+
<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
143
+
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
144
+
<&gcc GCC_PCIE1_AHB_ARES>,
145
+
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
146
+
reset-names = "pipe",
147
+
"sleep",
148
+
"sticky",
149
+
"axi_m",
150
+
"axi_s",
151
+
"ahb",
152
+
"axi_m_sticky";
153
+
154
+
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
155
+
156
+
pcie@0 {
157
+
device_type = "pci";
158
+
reg = <0x0 0x0 0x0 0x0 0x0>;
159
+
bus-range = <0x01 0xff>;
160
+
161
+
#address-cells = <3>;
162
+
#size-cells = <2>;
163
+
ranges;
164
+
};
165
+
};
+183
Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml
+183
Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq9574.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm IPQ9574 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- qcom,pcie-ipq9574
18
+
- items:
19
+
- enum:
20
+
- qcom,pcie-ipq5332
21
+
- qcom,pcie-ipq5424
22
+
- const: qcom,pcie-ipq9574
23
+
24
+
reg:
25
+
maxItems: 6
26
+
27
+
reg-names:
28
+
items:
29
+
- const: dbi
30
+
- const: elbi
31
+
- const: atu
32
+
- const: parf
33
+
- const: config
34
+
- const: mhi
35
+
36
+
clocks:
37
+
maxItems: 6
38
+
39
+
clock-names:
40
+
items:
41
+
- const: axi_m # AXI Master clock
42
+
- const: axi_s # AXI Slave clock
43
+
- const: axi_bridge
44
+
- const: rchng
45
+
- const: ahb
46
+
- const: aux
47
+
48
+
interrupts:
49
+
minItems: 8
50
+
maxItems: 9
51
+
52
+
interrupt-names:
53
+
minItems: 8
54
+
items:
55
+
- const: msi0
56
+
- const: msi1
57
+
- const: msi2
58
+
- const: msi3
59
+
- const: msi4
60
+
- const: msi5
61
+
- const: msi6
62
+
- const: msi7
63
+
- const: global
64
+
65
+
resets:
66
+
maxItems: 8
67
+
68
+
reset-names:
69
+
items:
70
+
- const: pipe
71
+
- const: sticky # Core sticky reset
72
+
- const: axi_s_sticky # AXI Slave Sticky reset
73
+
- const: axi_s # AXI slave reset
74
+
- const: axi_m_sticky # AXI Master Sticky reset
75
+
- const: axi_m # AXI master reset
76
+
- const: aux
77
+
- const: ahb
78
+
79
+
required:
80
+
- resets
81
+
- reset-names
82
+
83
+
allOf:
84
+
- $ref: qcom,pcie-common.yaml#
85
+
86
+
unevaluatedProperties: false
87
+
88
+
examples:
89
+
- |
90
+
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
91
+
#include <dt-bindings/gpio/gpio.h>
92
+
#include <dt-bindings/interconnect/qcom,ipq9574.h>
93
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
94
+
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
95
+
96
+
pcie@10000000 {
97
+
compatible = "qcom,pcie-ipq9574";
98
+
reg = <0x10000000 0xf1d>,
99
+
<0x10000f20 0xa8>,
100
+
<0x10001000 0x1000>,
101
+
<0x000f8000 0x4000>,
102
+
<0x10100000 0x1000>,
103
+
<0x000fe000 0x1000>;
104
+
reg-names = "dbi",
105
+
"elbi",
106
+
"atu",
107
+
"parf",
108
+
"config",
109
+
"mhi";
110
+
ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>,
111
+
<0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>;
112
+
113
+
device_type = "pci";
114
+
linux,pci-domain = <1>;
115
+
bus-range = <0x00 0xff>;
116
+
num-lanes = <1>;
117
+
#address-cells = <3>;
118
+
#size-cells = <2>;
119
+
120
+
clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
121
+
<&gcc GCC_PCIE1_AXI_S_CLK>,
122
+
<&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
123
+
<&gcc GCC_PCIE1_RCHNG_CLK>,
124
+
<&gcc GCC_PCIE1_AHB_CLK>,
125
+
<&gcc GCC_PCIE1_AUX_CLK>;
126
+
clock-names = "axi_m",
127
+
"axi_s",
128
+
"axi_bridge",
129
+
"rchng",
130
+
"ahb",
131
+
"aux";
132
+
133
+
interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
134
+
<&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>;
135
+
interconnect-names = "pcie-mem", "cpu-pcie";
136
+
137
+
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
138
+
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
139
+
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
140
+
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
141
+
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
142
+
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
143
+
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
144
+
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
145
+
interrupt-names = "msi0",
146
+
"msi1",
147
+
"msi2",
148
+
"msi3",
149
+
"msi4",
150
+
"msi5",
151
+
"msi6",
152
+
"msi7";
153
+
154
+
#interrupt-cells = <1>;
155
+
interrupt-map-mask = <0 0 0 0x7>;
156
+
interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
157
+
<0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
158
+
<0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
159
+
<0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
160
+
161
+
resets = <&gcc GCC_PCIE1_PIPE_ARES>,
162
+
<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
163
+
<&gcc GCC_PCIE1_AXI_S_STICKY_ARES>,
164
+
<&gcc GCC_PCIE1_AXI_S_ARES>,
165
+
<&gcc GCC_PCIE1_AXI_M_STICKY_ARES>,
166
+
<&gcc GCC_PCIE1_AXI_M_ARES>,
167
+
<&gcc GCC_PCIE1_AUX_ARES>,
168
+
<&gcc GCC_PCIE1_AHB_ARES>;
169
+
reset-names = "pipe",
170
+
"sticky",
171
+
"axi_s_sticky",
172
+
"axi_s",
173
+
"axi_m_sticky",
174
+
"axi_m",
175
+
"aux",
176
+
"ahb";
177
+
178
+
phys = <&pcie1_phy>;
179
+
phy-names = "pciephy";
180
+
181
+
perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
182
+
wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
183
+
};
+156
Documentation/devicetree/bindings/pci/qcom,pcie-msm8996.yaml
+156
Documentation/devicetree/bindings/pci/qcom,pcie-msm8996.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-msm8996.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm MSM8996 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- qcom,pcie-msm8996
18
+
- items:
19
+
- const: qcom,pcie-msm8998
20
+
- const: qcom,pcie-msm8996
21
+
22
+
reg:
23
+
minItems: 4
24
+
maxItems: 5
25
+
26
+
reg-names:
27
+
minItems: 4
28
+
items:
29
+
- const: parf
30
+
- const: dbi
31
+
- const: elbi
32
+
- const: config
33
+
- const: mhi
34
+
35
+
clocks:
36
+
maxItems: 5
37
+
38
+
clock-names:
39
+
items:
40
+
- const: pipe # Pipe Clock driving internal logic
41
+
- const: aux
42
+
- const: cfg
43
+
- const: bus_master # Master AXI clock
44
+
- const: bus_slave # Slave AXI clock
45
+
46
+
interrupts:
47
+
minItems: 8
48
+
maxItems: 9
49
+
50
+
interrupt-names:
51
+
minItems: 8
52
+
items:
53
+
- const: msi0
54
+
- const: msi1
55
+
- const: msi2
56
+
- const: msi3
57
+
- const: msi4
58
+
- const: msi5
59
+
- const: msi6
60
+
- const: msi7
61
+
- const: global
62
+
63
+
vdda-supply:
64
+
description: A phandle to the core analog power supply
65
+
66
+
vddpe-3v3-supply:
67
+
description: A phandle to the PCIe endpoint power supply
68
+
69
+
required:
70
+
- power-domains
71
+
72
+
allOf:
73
+
- $ref: qcom,pcie-common.yaml#
74
+
75
+
unevaluatedProperties: false
76
+
77
+
examples:
78
+
- |
79
+
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
80
+
#include <dt-bindings/gpio/gpio.h>
81
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
82
+
83
+
pcie@600000 {
84
+
compatible = "qcom,pcie-msm8996";
85
+
reg = <0x00600000 0x2000>,
86
+
<0x0c000000 0xf1d>,
87
+
<0x0c000f20 0xa8>,
88
+
<0x0c100000 0x100000>;
89
+
reg-names = "parf", "dbi", "elbi", "config";
90
+
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
91
+
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
92
+
93
+
device_type = "pci";
94
+
bus-range = <0x00 0xff>;
95
+
num-lanes = <1>;
96
+
#address-cells = <3>;
97
+
#size-cells = <2>;
98
+
linux,pci-domain = <0>;
99
+
100
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
101
+
<&gcc GCC_PCIE_0_AUX_CLK>,
102
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
103
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
104
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
105
+
clock-names = "pipe",
106
+
"aux",
107
+
"cfg",
108
+
"bus_master",
109
+
"bus_slave";
110
+
111
+
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
112
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
113
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
114
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
115
+
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
116
+
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
117
+
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
118
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
119
+
interrupt-names = "msi0",
120
+
"msi1",
121
+
"msi2",
122
+
"msi3",
123
+
"msi4",
124
+
"msi5",
125
+
"msi6",
126
+
"msi7";
127
+
#interrupt-cells = <1>;
128
+
interrupt-map-mask = <0 0 0 0x7>;
129
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
130
+
<0 0 0 2 &intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
131
+
<0 0 0 3 &intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
132
+
<0 0 0 4 &intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
133
+
134
+
pinctrl-names = "default", "sleep";
135
+
pinctrl-0 = <&pcie0_state_on>;
136
+
pinctrl-1 = <&pcie0_state_off>;
137
+
138
+
phys = <&pciephy_0>;
139
+
phy-names = "pciephy";
140
+
141
+
power-domains = <&gcc PCIE0_GDSC>;
142
+
143
+
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
144
+
vddpe-3v3-supply = <&wlan_en>;
145
+
vdda-supply = <&vreg_l28a_0p925>;
146
+
147
+
pcie@0 {
148
+
device_type = "pci";
149
+
reg = <0x0 0x0 0x0 0x0 0x0>;
150
+
bus-range = <0x01 0xff>;
151
+
152
+
#address-cells = <3>;
153
+
#size-cells = <2>;
154
+
ranges;
155
+
};
156
+
};
+131
Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
+131
Documentation/devicetree/bindings/pci/qcom,pcie-qcs404.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-qcs404.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm QCS404 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-qcs404
17
+
18
+
reg:
19
+
maxItems: 4
20
+
21
+
reg-names:
22
+
items:
23
+
- const: dbi
24
+
- const: elbi
25
+
- const: parf
26
+
- const: config
27
+
28
+
clocks:
29
+
maxItems: 4
30
+
31
+
clock-names:
32
+
items:
33
+
- const: iface # AHB clock
34
+
- const: aux
35
+
- const: master_bus # AXI Master clock
36
+
- const: slave_bus # AXI Slave clock
37
+
38
+
interrupts:
39
+
maxItems: 1
40
+
41
+
interrupt-names:
42
+
items:
43
+
- const: msi
44
+
45
+
resets:
46
+
maxItems: 6
47
+
48
+
reset-names:
49
+
items:
50
+
- const: axi_m # AXI Master reset
51
+
- const: axi_s # AXI Slave reset
52
+
- const: axi_m_sticky # AXI Master Sticky reset
53
+
- const: pipe_sticky
54
+
- const: pwr
55
+
- const: ahb
56
+
57
+
required:
58
+
- resets
59
+
- reset-names
60
+
61
+
allOf:
62
+
- $ref: qcom,pcie-common.yaml#
63
+
64
+
unevaluatedProperties: false
65
+
66
+
examples:
67
+
- |
68
+
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
69
+
#include <dt-bindings/gpio/gpio.h>
70
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
71
+
72
+
pcie@10000000 {
73
+
compatible = "qcom,pcie-qcs404";
74
+
reg = <0x10000000 0xf1d>,
75
+
<0x10000f20 0xa8>,
76
+
<0x07780000 0x2000>,
77
+
<0x10001000 0x2000>;
78
+
reg-names = "dbi", "elbi", "parf", "config";
79
+
ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
80
+
<0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
81
+
82
+
device_type = "pci";
83
+
linux,pci-domain = <0>;
84
+
bus-range = <0x00 0xff>;
85
+
num-lanes = <1>;
86
+
#address-cells = <3>;
87
+
#size-cells = <2>;
88
+
89
+
clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
90
+
<&gcc GCC_PCIE_0_AUX_CLK>,
91
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
92
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
93
+
clock-names = "iface", "aux", "master_bus", "slave_bus";
94
+
95
+
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
96
+
interrupt-names = "msi";
97
+
#interrupt-cells = <1>;
98
+
interrupt-map-mask = <0 0 0 0x7>;
99
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
100
+
<0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
101
+
<0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
102
+
<0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
103
+
104
+
phys = <&pcie_phy>;
105
+
phy-names = "pciephy";
106
+
107
+
perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
108
+
109
+
resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
110
+
<&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
111
+
<&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
112
+
<&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
113
+
<&gcc GCC_PCIE_0_BCR>,
114
+
<&gcc GCC_PCIE_0_AHB_ARES>;
115
+
reset-names = "axi_m",
116
+
"axi_s",
117
+
"axi_m_sticky",
118
+
"pipe_sticky",
119
+
"pwr",
120
+
"ahb";
121
+
122
+
pcie@0 {
123
+
device_type = "pci";
124
+
reg = <0x0 0x0 0x0 0x0 0x0>;
125
+
bus-range = <0x01 0xff>;
126
+
127
+
#address-cells = <3>;
128
+
#size-cells = <2>;
129
+
ranges;
130
+
};
131
+
};
-168
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
-168
Documentation/devicetree/bindings/pci/qcom,pcie-sc8180x.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/pci/qcom,pcie-sc8180x.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Qualcomm SC8180x PCI Express Root Complex
8
-
9
-
maintainers:
10
-
- Bjorn Andersson <andersson@kernel.org>
11
-
- Manivannan Sadhasivam <mani@kernel.org>
12
-
13
-
description:
14
-
Qualcomm SC8180x SoC PCIe root complex controller is based on the Synopsys
15
-
DesignWare PCIe IP.
16
-
17
-
properties:
18
-
compatible:
19
-
const: qcom,pcie-sc8180x
20
-
21
-
reg:
22
-
minItems: 5
23
-
maxItems: 6
24
-
25
-
reg-names:
26
-
minItems: 5
27
-
items:
28
-
- const: parf # Qualcomm specific registers
29
-
- const: dbi # DesignWare PCIe registers
30
-
- const: elbi # External local bus interface registers
31
-
- const: atu # ATU address space
32
-
- const: config # PCIe configuration space
33
-
- const: mhi # MHI registers
34
-
35
-
clocks:
36
-
minItems: 6
37
-
maxItems: 6
38
-
39
-
clock-names:
40
-
items:
41
-
- const: pipe # PIPE clock
42
-
- const: aux # Auxiliary clock
43
-
- const: cfg # Configuration clock
44
-
- const: bus_master # Master AXI clock
45
-
- const: bus_slave # Slave AXI clock
46
-
- const: slave_q2a # Slave Q2A clock
47
-
48
-
interrupts:
49
-
minItems: 8
50
-
maxItems: 9
51
-
52
-
interrupt-names:
53
-
minItems: 8
54
-
items:
55
-
- const: msi0
56
-
- const: msi1
57
-
- const: msi2
58
-
- const: msi3
59
-
- const: msi4
60
-
- const: msi5
61
-
- const: msi6
62
-
- const: msi7
63
-
- const: global
64
-
65
-
resets:
66
-
maxItems: 1
67
-
68
-
reset-names:
69
-
items:
70
-
- const: pci
71
-
72
-
allOf:
73
-
- $ref: qcom,pcie-common.yaml#
74
-
75
-
unevaluatedProperties: false
76
-
77
-
examples:
78
-
- |
79
-
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
80
-
#include <dt-bindings/interconnect/qcom,sc8180x.h>
81
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
82
-
83
-
soc {
84
-
#address-cells = <2>;
85
-
#size-cells = <2>;
86
-
87
-
pcie@1c00000 {
88
-
compatible = "qcom,pcie-sc8180x";
89
-
reg = <0 0x01c00000 0 0x3000>,
90
-
<0 0x60000000 0 0xf1d>,
91
-
<0 0x60000f20 0 0xa8>,
92
-
<0 0x60001000 0 0x1000>,
93
-
<0 0x60100000 0 0x100000>;
94
-
reg-names = "parf",
95
-
"dbi",
96
-
"elbi",
97
-
"atu",
98
-
"config";
99
-
ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>,
100
-
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101
-
102
-
bus-range = <0x00 0xff>;
103
-
device_type = "pci";
104
-
linux,pci-domain = <0>;
105
-
num-lanes = <2>;
106
-
107
-
#address-cells = <3>;
108
-
#size-cells = <2>;
109
-
110
-
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
111
-
assigned-clock-rates = <19200000>;
112
-
113
-
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
114
-
<&gcc GCC_PCIE_0_AUX_CLK>,
115
-
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
116
-
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
117
-
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
118
-
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
119
-
clock-names = "pipe",
120
-
"aux",
121
-
"cfg",
122
-
"bus_master",
123
-
"bus_slave",
124
-
"slave_q2a";
125
-
126
-
dma-coherent;
127
-
128
-
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
129
-
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
130
-
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
131
-
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
132
-
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
133
-
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
134
-
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
135
-
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
136
-
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
137
-
interrupt-names = "msi0",
138
-
"msi1",
139
-
"msi2",
140
-
"msi3",
141
-
"msi4",
142
-
"msi5",
143
-
"msi6",
144
-
"msi7",
145
-
"global";
146
-
#interrupt-cells = <1>;
147
-
interrupt-map-mask = <0 0 0 0x7>;
148
-
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
149
-
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
150
-
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
151
-
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
152
-
153
-
interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>,
154
-
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>;
155
-
interconnect-names = "pcie-mem", "cpu-pcie";
156
-
157
-
iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
158
-
<0x100 &apps_smmu 0x1d81 0x1>;
159
-
160
-
phys = <&pcie0_phy>;
161
-
phy-names = "pciephy";
162
-
163
-
power-domains = <&gcc PCIE_0_GDSC>;
164
-
165
-
resets = <&gcc GCC_PCIE_0_BCR>;
166
-
reset-names = "pci";
167
-
};
168
-
};
+190
Documentation/devicetree/bindings/pci/qcom,pcie-sdm845.yaml
+190
Documentation/devicetree/bindings/pci/qcom,pcie-sdm845.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdm845.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDM845 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-sdm845
17
+
18
+
reg:
19
+
minItems: 4
20
+
maxItems: 5
21
+
22
+
reg-names:
23
+
minItems: 4
24
+
items:
25
+
- const: parf
26
+
- const: dbi
27
+
- const: elbi
28
+
- const: config
29
+
- const: mhi
30
+
31
+
clocks:
32
+
minItems: 7
33
+
maxItems: 8
34
+
35
+
clock-names:
36
+
minItems: 7
37
+
items:
38
+
- const: pipe
39
+
- const: aux
40
+
- const: cfg
41
+
- const: bus_master # Master AXI clock
42
+
- const: bus_slave # Slave AXI clock
43
+
- const: slave_q2a
44
+
- enum: [ ref, tbu ]
45
+
- const: tbu
46
+
47
+
interrupts:
48
+
minItems: 8
49
+
maxItems: 9
50
+
51
+
interrupt-names:
52
+
minItems: 8
53
+
items:
54
+
- const: msi0
55
+
- const: msi1
56
+
- const: msi2
57
+
- const: msi3
58
+
- const: msi4
59
+
- const: msi5
60
+
- const: msi6
61
+
- const: msi7
62
+
- const: global
63
+
64
+
resets:
65
+
maxItems: 1
66
+
67
+
reset-names:
68
+
items:
69
+
- const: pci
70
+
71
+
required:
72
+
- power-domains
73
+
- resets
74
+
- reset-names
75
+
76
+
allOf:
77
+
- $ref: qcom,pcie-common.yaml#
78
+
79
+
unevaluatedProperties: false
80
+
81
+
examples:
82
+
- |
83
+
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
84
+
#include <dt-bindings/gpio/gpio.h>
85
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
86
+
87
+
soc {
88
+
#address-cells = <2>;
89
+
#size-cells = <2>;
90
+
91
+
pcie@1c00000 {
92
+
compatible = "qcom,pcie-sdm845";
93
+
reg = <0x0 0x01c00000 0x0 0x2000>,
94
+
<0x0 0x60000000 0x0 0xf1d>,
95
+
<0x0 0x60000f20 0x0 0xa8>,
96
+
<0x0 0x60100000 0x0 0x100000>,
97
+
<0x0 0x01c07000 0x0 0x1000>;
98
+
reg-names = "parf", "dbi", "elbi", "config", "mhi";
99
+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
100
+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
101
+
102
+
device_type = "pci";
103
+
linux,pci-domain = <0>;
104
+
bus-range = <0x00 0xff>;
105
+
num-lanes = <1>;
106
+
107
+
#address-cells = <3>;
108
+
#size-cells = <2>;
109
+
110
+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
111
+
<&gcc GCC_PCIE_0_AUX_CLK>,
112
+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
113
+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
114
+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
115
+
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
116
+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
117
+
clock-names = "pipe",
118
+
"aux",
119
+
"cfg",
120
+
"bus_master",
121
+
"bus_slave",
122
+
"slave_q2a",
123
+
"tbu";
124
+
125
+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
126
+
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
127
+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
128
+
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
129
+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
130
+
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
131
+
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
132
+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
133
+
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
134
+
interrupt-names = "msi0",
135
+
"msi1",
136
+
"msi2",
137
+
"msi3",
138
+
"msi4",
139
+
"msi5",
140
+
"msi6",
141
+
"msi7",
142
+
"global";
143
+
#interrupt-cells = <1>;
144
+
interrupt-map-mask = <0 0 0 0x7>;
145
+
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
146
+
<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
147
+
<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
148
+
<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
149
+
150
+
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
151
+
<0x100 &apps_smmu 0x1c11 0x1>,
152
+
<0x200 &apps_smmu 0x1c12 0x1>,
153
+
<0x300 &apps_smmu 0x1c13 0x1>,
154
+
<0x400 &apps_smmu 0x1c14 0x1>,
155
+
<0x500 &apps_smmu 0x1c15 0x1>,
156
+
<0x600 &apps_smmu 0x1c16 0x1>,
157
+
<0x700 &apps_smmu 0x1c17 0x1>,
158
+
<0x800 &apps_smmu 0x1c18 0x1>,
159
+
<0x900 &apps_smmu 0x1c19 0x1>,
160
+
<0xa00 &apps_smmu 0x1c1a 0x1>,
161
+
<0xb00 &apps_smmu 0x1c1b 0x1>,
162
+
<0xc00 &apps_smmu 0x1c1c 0x1>,
163
+
<0xd00 &apps_smmu 0x1c1d 0x1>,
164
+
<0xe00 &apps_smmu 0x1c1e 0x1>,
165
+
<0xf00 &apps_smmu 0x1c1f 0x1>;
166
+
167
+
power-domains = <&gcc PCIE_0_GDSC>;
168
+
169
+
phys = <&pcie0_phy>;
170
+
phy-names = "pciephy";
171
+
172
+
resets = <&gcc GCC_PCIE_0_BCR>;
173
+
reset-names = "pci";
174
+
175
+
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
176
+
wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
177
+
178
+
vddpe-3v3-supply = <&pcie0_3p3v_dual>;
179
+
180
+
pcie@0 {
181
+
device_type = "pci";
182
+
reg = <0x0 0x0 0x0 0x0 0x0>;
183
+
bus-range = <0x01 0xff>;
184
+
185
+
#address-cells = <3>;
186
+
#size-cells = <2>;
187
+
ranges;
188
+
};
189
+
};
190
+
};
+172
Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml
+172
Documentation/devicetree/bindings/pci/qcom,pcie-sdx55.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm SDX55 PCI Express Root Complex
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Manivannan Sadhasivam <mani@kernel.org>
12
+
13
+
properties:
14
+
compatible:
15
+
enum:
16
+
- qcom,pcie-sdx55
17
+
18
+
reg:
19
+
minItems: 5
20
+
maxItems: 6
21
+
22
+
reg-names:
23
+
minItems: 5
24
+
items:
25
+
- const: parf
26
+
- const: dbi
27
+
- const: elbi
28
+
- const: atu
29
+
- const: config
30
+
- const: mhi
31
+
32
+
clocks:
33
+
maxItems: 7
34
+
35
+
clock-names:
36
+
items:
37
+
- const: pipe
38
+
- const: aux
39
+
- const: cfg
40
+
- const: bus_master # Master AXI clock
41
+
- const: bus_slave # Slave AXI clock
42
+
- const: slave_q2a
43
+
- const: sleep
44
+
45
+
interrupts:
46
+
maxItems: 8
47
+
48
+
interrupt-names:
49
+
items:
50
+
- const: msi
51
+
- const: msi2
52
+
- const: msi3
53
+
- const: msi4
54
+
- const: msi5
55
+
- const: msi6
56
+
- const: msi7
57
+
- const: msi8
58
+
59
+
resets:
60
+
maxItems: 1
61
+
62
+
reset-names:
63
+
items:
64
+
- const: pci
65
+
66
+
required:
67
+
- power-domains
68
+
- resets
69
+
- reset-names
70
+
71
+
allOf:
72
+
- $ref: qcom,pcie-common.yaml#
73
+
74
+
unevaluatedProperties: false
75
+
76
+
examples:
77
+
- |
78
+
#include <dt-bindings/clock/qcom,gcc-sdx55.h>
79
+
#include <dt-bindings/gpio/gpio.h>
80
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
81
+
82
+
pcie@1c00000 {
83
+
compatible = "qcom,pcie-sdx55";
84
+
reg = <0x01c00000 0x3000>,
85
+
<0x40000000 0xf1d>,
86
+
<0x40000f20 0xc8>,
87
+
<0x40001000 0x1000>,
88
+
<0x40100000 0x100000>;
89
+
reg-names = "parf",
90
+
"dbi",
91
+
"elbi",
92
+
"atu",
93
+
"config";
94
+
ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
95
+
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
96
+
97
+
device_type = "pci";
98
+
linux,pci-domain = <0>;
99
+
bus-range = <0x00 0xff>;
100
+
num-lanes = <1>;
101
+
102
+
#address-cells = <3>;
103
+
#size-cells = <2>;
104
+
105
+
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
106
+
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
107
+
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
108
+
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
109
+
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
110
+
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
111
+
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
112
+
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
113
+
interrupt-names = "msi",
114
+
"msi2",
115
+
"msi3",
116
+
"msi4",
117
+
"msi5",
118
+
"msi6",
119
+
"msi7",
120
+
"msi8";
121
+
#interrupt-cells = <1>;
122
+
interrupt-map-mask = <0 0 0 0x7>;
123
+
interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
124
+
<0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
125
+
<0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
126
+
<0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
127
+
128
+
clocks = <&gcc GCC_PCIE_PIPE_CLK>,
129
+
<&gcc GCC_PCIE_AUX_CLK>,
130
+
<&gcc GCC_PCIE_CFG_AHB_CLK>,
131
+
<&gcc GCC_PCIE_MSTR_AXI_CLK>,
132
+
<&gcc GCC_PCIE_SLV_AXI_CLK>,
133
+
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
134
+
<&gcc GCC_PCIE_SLEEP_CLK>;
135
+
clock-names = "pipe",
136
+
"aux",
137
+
"cfg",
138
+
"bus_master",
139
+
"bus_slave",
140
+
"slave_q2a",
141
+
"sleep";
142
+
143
+
assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
144
+
assigned-clock-rates = <19200000>;
145
+
146
+
iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
147
+
<0x100 &apps_smmu 0x0201 0x1>,
148
+
<0x200 &apps_smmu 0x0202 0x1>,
149
+
<0x300 &apps_smmu 0x0203 0x1>,
150
+
<0x400 &apps_smmu 0x0204 0x1>;
151
+
152
+
power-domains = <&gcc PCIE_GDSC>;
153
+
154
+
phys = <&pcie_phy>;
155
+
phy-names = "pciephy";
156
+
157
+
resets = <&gcc GCC_PCIE_BCR>;
158
+
reset-names = "pci";
159
+
160
+
perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
161
+
wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
162
+
163
+
pcie@0 {
164
+
device_type = "pci";
165
+
reg = <0x0 0x0 0x0 0x0 0x0>;
166
+
bus-range = <0x01 0xff>;
167
+
168
+
#address-cells = <3>;
169
+
#size-cells = <2>;
170
+
ranges;
171
+
};
172
+
};
+1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
+1
Documentation/devicetree/bindings/pci/qcom,pcie-sm8150.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+6
-1
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
-782
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
-782
Documentation/devicetree/bindings/pci/qcom,pcie.yaml
···
1
-
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
-
%YAML 1.2
3
-
---
4
-
$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5
-
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
-
7
-
title: Qualcomm PCI express root complex
8
-
9
-
maintainers:
10
-
- Bjorn Andersson <bjorn.andersson@linaro.org>
11
-
- Manivannan Sadhasivam <mani@kernel.org>
12
-
13
-
description: |
14
-
Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15
-
PCIe IP.
16
-
17
-
properties:
18
-
compatible:
19
-
oneOf:
20
-
- enum:
21
-
- qcom,pcie-apq8064
22
-
- qcom,pcie-apq8084
23
-
- qcom,pcie-ipq4019
24
-
- qcom,pcie-ipq5018
25
-
- qcom,pcie-ipq6018
26
-
- qcom,pcie-ipq8064
27
-
- qcom,pcie-ipq8064-v2
28
-
- qcom,pcie-ipq8074
29
-
- qcom,pcie-ipq8074-gen3
30
-
- qcom,pcie-ipq9574
31
-
- qcom,pcie-msm8996
32
-
- qcom,pcie-qcs404
33
-
- qcom,pcie-sdm845
34
-
- qcom,pcie-sdx55
35
-
- items:
36
-
- enum:
37
-
- qcom,pcie-ipq5332
38
-
- qcom,pcie-ipq5424
39
-
- const: qcom,pcie-ipq9574
40
-
- items:
41
-
- const: qcom,pcie-msm8998
42
-
- const: qcom,pcie-msm8996
43
-
44
-
reg:
45
-
minItems: 4
46
-
maxItems: 6
47
-
48
-
reg-names:
49
-
minItems: 4
50
-
maxItems: 6
51
-
52
-
interrupts:
53
-
minItems: 1
54
-
maxItems: 9
55
-
56
-
interrupt-names:
57
-
minItems: 1
58
-
maxItems: 9
59
-
60
-
iommu-map:
61
-
minItems: 1
62
-
maxItems: 16
63
-
64
-
# Common definitions for clocks, clock-names and reset.
65
-
# Platform constraints are described later.
66
-
clocks:
67
-
minItems: 3
68
-
maxItems: 13
69
-
70
-
clock-names:
71
-
minItems: 3
72
-
maxItems: 13
73
-
74
-
dma-coherent: true
75
-
76
-
interconnects:
77
-
maxItems: 2
78
-
79
-
interconnect-names:
80
-
items:
81
-
- const: pcie-mem
82
-
- const: cpu-pcie
83
-
84
-
resets:
85
-
minItems: 1
86
-
maxItems: 12
87
-
88
-
reset-names:
89
-
minItems: 1
90
-
maxItems: 12
91
-
92
-
vdda-supply:
93
-
description: A phandle to the core analog power supply
94
-
95
-
vdda_phy-supply:
96
-
description: A phandle to the core analog power supply for PHY
97
-
98
-
vdda_refclk-supply:
99
-
description: A phandle to the core analog power supply for IC which generates reference clock
100
-
101
-
vddpe-3v3-supply:
102
-
description: A phandle to the PCIe endpoint power supply
103
-
104
-
phys:
105
-
maxItems: 1
106
-
107
-
phy-names:
108
-
items:
109
-
- const: pciephy
110
-
111
-
power-domains:
112
-
maxItems: 1
113
-
114
-
perst-gpios:
115
-
description: GPIO controlled connection to PERST# signal
116
-
maxItems: 1
117
-
118
-
required-opps:
119
-
maxItems: 1
120
-
121
-
wake-gpios:
122
-
description: GPIO controlled connection to WAKE# signal
123
-
maxItems: 1
124
-
125
-
required:
126
-
- compatible
127
-
- reg
128
-
- reg-names
129
-
- interrupt-map-mask
130
-
- interrupt-map
131
-
- clocks
132
-
- clock-names
133
-
134
-
anyOf:
135
-
- required:
136
-
- interrupts
137
-
- interrupt-names
138
-
- "#interrupt-cells"
139
-
- required:
140
-
- msi-map
141
-
142
-
allOf:
143
-
- $ref: /schemas/pci/pci-host-bridge.yaml#
144
-
- if:
145
-
properties:
146
-
compatible:
147
-
contains:
148
-
enum:
149
-
- qcom,pcie-apq8064
150
-
- qcom,pcie-ipq4019
151
-
- qcom,pcie-ipq8064
152
-
- qcom,pcie-ipq8064v2
153
-
- qcom,pcie-ipq8074
154
-
- qcom,pcie-qcs404
155
-
then:
156
-
properties:
157
-
reg:
158
-
minItems: 4
159
-
maxItems: 4
160
-
reg-names:
161
-
items:
162
-
- const: dbi # DesignWare PCIe registers
163
-
- const: elbi # External local bus interface registers
164
-
- const: parf # Qualcomm specific registers
165
-
- const: config # PCIe configuration space
166
-
167
-
- if:
168
-
properties:
169
-
compatible:
170
-
contains:
171
-
enum:
172
-
- qcom,pcie-ipq5018
173
-
- qcom,pcie-ipq6018
174
-
- qcom,pcie-ipq8074-gen3
175
-
- qcom,pcie-ipq9574
176
-
then:
177
-
properties:
178
-
reg:
179
-
minItems: 5
180
-
maxItems: 6
181
-
reg-names:
182
-
minItems: 5
183
-
items:
184
-
- const: dbi # DesignWare PCIe registers
185
-
- const: elbi # External local bus interface registers
186
-
- const: atu # ATU address space
187
-
- const: parf # Qualcomm specific registers
188
-
- const: config # PCIe configuration space
189
-
- const: mhi # MHI registers
190
-
191
-
- if:
192
-
properties:
193
-
compatible:
194
-
contains:
195
-
enum:
196
-
- qcom,pcie-apq8084
197
-
- qcom,pcie-msm8996
198
-
- qcom,pcie-sdm845
199
-
then:
200
-
properties:
201
-
reg:
202
-
minItems: 4
203
-
maxItems: 5
204
-
reg-names:
205
-
minItems: 4
206
-
items:
207
-
- const: parf # Qualcomm specific registers
208
-
- const: dbi # DesignWare PCIe registers
209
-
- const: elbi # External local bus interface registers
210
-
- const: config # PCIe configuration space
211
-
- const: mhi # MHI registers
212
-
213
-
- if:
214
-
properties:
215
-
compatible:
216
-
contains:
217
-
enum:
218
-
- qcom,pcie-sdx55
219
-
then:
220
-
properties:
221
-
reg:
222
-
minItems: 5
223
-
maxItems: 6
224
-
reg-names:
225
-
minItems: 5
226
-
items:
227
-
- const: parf # Qualcomm specific registers
228
-
- const: dbi # DesignWare PCIe registers
229
-
- const: elbi # External local bus interface registers
230
-
- const: atu # ATU address space
231
-
- const: config # PCIe configuration space
232
-
- const: mhi # MHI registers
233
-
234
-
- if:
235
-
properties:
236
-
compatible:
237
-
contains:
238
-
enum:
239
-
- qcom,pcie-apq8064
240
-
- qcom,pcie-ipq8064
241
-
- qcom,pcie-ipq8064v2
242
-
then:
243
-
properties:
244
-
clocks:
245
-
minItems: 3
246
-
maxItems: 5
247
-
clock-names:
248
-
minItems: 3
249
-
items:
250
-
- const: core # Clocks the pcie hw block
251
-
- const: iface # Configuration AHB clock
252
-
- const: phy # Clocks the pcie PHY block
253
-
- const: aux # Clocks the pcie AUX block, not on apq8064
254
-
- const: ref # Clocks the pcie ref block, not on apq8064
255
-
resets:
256
-
minItems: 5
257
-
maxItems: 6
258
-
reset-names:
259
-
minItems: 5
260
-
items:
261
-
- const: axi # AXI reset
262
-
- const: ahb # AHB reset
263
-
- const: por # POR reset
264
-
- const: pci # PCI reset
265
-
- const: phy # PHY reset
266
-
- const: ext # EXT reset, not on apq8064
267
-
required:
268
-
- vdda-supply
269
-
- vdda_phy-supply
270
-
- vdda_refclk-supply
271
-
272
-
- if:
273
-
properties:
274
-
compatible:
275
-
contains:
276
-
enum:
277
-
- qcom,pcie-apq8084
278
-
then:
279
-
properties:
280
-
clocks:
281
-
minItems: 4
282
-
maxItems: 4
283
-
clock-names:
284
-
items:
285
-
- const: iface # Configuration AHB clock
286
-
- const: master_bus # Master AXI clock
287
-
- const: slave_bus # Slave AXI clock
288
-
- const: aux # Auxiliary (AUX) clock
289
-
resets:
290
-
maxItems: 1
291
-
reset-names:
292
-
items:
293
-
- const: core # Core reset
294
-
295
-
- if:
296
-
properties:
297
-
compatible:
298
-
contains:
299
-
enum:
300
-
- qcom,pcie-ipq4019
301
-
then:
302
-
properties:
303
-
clocks:
304
-
minItems: 3
305
-
maxItems: 3
306
-
clock-names:
307
-
items:
308
-
- const: aux # Auxiliary (AUX) clock
309
-
- const: master_bus # Master AXI clock
310
-
- const: slave_bus # Slave AXI clock
311
-
resets:
312
-
minItems: 12
313
-
maxItems: 12
314
-
reset-names:
315
-
items:
316
-
- const: axi_m # AXI master reset
317
-
- const: axi_s # AXI slave reset
318
-
- const: pipe # PIPE reset
319
-
- const: axi_m_vmid # VMID reset
320
-
- const: axi_s_xpu # XPU reset
321
-
- const: parf # PARF reset
322
-
- const: phy # PHY reset
323
-
- const: axi_m_sticky # AXI sticky reset
324
-
- const: pipe_sticky # PIPE sticky reset
325
-
- const: pwr # PWR reset
326
-
- const: ahb # AHB reset
327
-
- const: phy_ahb # PHY AHB reset
328
-
329
-
- if:
330
-
properties:
331
-
compatible:
332
-
contains:
333
-
enum:
334
-
- qcom,pcie-ipq5018
335
-
then:
336
-
properties:
337
-
clocks:
338
-
minItems: 6
339
-
maxItems: 6
340
-
clock-names:
341
-
items:
342
-
- const: iface # PCIe to SysNOC BIU clock
343
-
- const: axi_m # AXI Master clock
344
-
- const: axi_s # AXI Slave clock
345
-
- const: ahb # AHB clock
346
-
- const: aux # Auxiliary clock
347
-
- const: axi_bridge # AXI bridge clock
348
-
resets:
349
-
minItems: 8
350
-
maxItems: 8
351
-
reset-names:
352
-
items:
353
-
- const: pipe # PIPE reset
354
-
- const: sleep # Sleep reset
355
-
- const: sticky # Core sticky reset
356
-
- const: axi_m # AXI master reset
357
-
- const: axi_s # AXI slave reset
358
-
- const: ahb # AHB reset
359
-
- const: axi_m_sticky # AXI master sticky reset
360
-
- const: axi_s_sticky # AXI slave sticky reset
361
-
interrupts:
362
-
minItems: 9
363
-
maxItems: 9
364
-
interrupt-names:
365
-
items:
366
-
- const: msi0
367
-
- const: msi1
368
-
- const: msi2
369
-
- const: msi3
370
-
- const: msi4
371
-
- const: msi5
372
-
- const: msi6
373
-
- const: msi7
374
-
- const: global
375
-
376
-
- if:
377
-
properties:
378
-
compatible:
379
-
contains:
380
-
enum:
381
-
- qcom,pcie-msm8996
382
-
then:
383
-
properties:
384
-
clocks:
385
-
minItems: 5
386
-
maxItems: 5
387
-
clock-names:
388
-
items:
389
-
- const: pipe # Pipe Clock driving internal logic
390
-
- const: aux # Auxiliary (AUX) clock
391
-
- const: cfg # Configuration clock
392
-
- const: bus_master # Master AXI clock
393
-
- const: bus_slave # Slave AXI clock
394
-
resets: false
395
-
reset-names: false
396
-
397
-
- if:
398
-
properties:
399
-
compatible:
400
-
contains:
401
-
enum:
402
-
- qcom,pcie-ipq8074
403
-
then:
404
-
properties:
405
-
clocks:
406
-
minItems: 5
407
-
maxItems: 5
408
-
clock-names:
409
-
items:
410
-
- const: iface # PCIe to SysNOC BIU clock
411
-
- const: axi_m # AXI Master clock
412
-
- const: axi_s # AXI Slave clock
413
-
- const: ahb # AHB clock
414
-
- const: aux # Auxiliary clock
415
-
resets:
416
-
minItems: 7
417
-
maxItems: 7
418
-
reset-names:
419
-
items:
420
-
- const: pipe # PIPE reset
421
-
- const: sleep # Sleep reset
422
-
- const: sticky # Core Sticky reset
423
-
- const: axi_m # AXI Master reset
424
-
- const: axi_s # AXI Slave reset
425
-
- const: ahb # AHB Reset
426
-
- const: axi_m_sticky # AXI Master Sticky reset
427
-
428
-
- if:
429
-
properties:
430
-
compatible:
431
-
contains:
432
-
enum:
433
-
- qcom,pcie-ipq6018
434
-
- qcom,pcie-ipq8074-gen3
435
-
then:
436
-
properties:
437
-
clocks:
438
-
minItems: 5
439
-
maxItems: 5
440
-
clock-names:
441
-
items:
442
-
- const: iface # PCIe to SysNOC BIU clock
443
-
- const: axi_m # AXI Master clock
444
-
- const: axi_s # AXI Slave clock
445
-
- const: axi_bridge # AXI bridge clock
446
-
- const: rchng
447
-
resets:
448
-
minItems: 8
449
-
maxItems: 8
450
-
reset-names:
451
-
items:
452
-
- const: pipe # PIPE reset
453
-
- const: sleep # Sleep reset
454
-
- const: sticky # Core Sticky reset
455
-
- const: axi_m # AXI Master reset
456
-
- const: axi_s # AXI Slave reset
457
-
- const: ahb # AHB Reset
458
-
- const: axi_m_sticky # AXI Master Sticky reset
459
-
- const: axi_s_sticky # AXI Slave Sticky reset
460
-
461
-
- if:
462
-
properties:
463
-
compatible:
464
-
contains:
465
-
enum:
466
-
- qcom,pcie-ipq9574
467
-
then:
468
-
properties:
469
-
clocks:
470
-
minItems: 6
471
-
maxItems: 6
472
-
clock-names:
473
-
items:
474
-
- const: axi_m # AXI Master clock
475
-
- const: axi_s # AXI Slave clock
476
-
- const: axi_bridge
477
-
- const: rchng
478
-
- const: ahb
479
-
- const: aux
480
-
481
-
resets:
482
-
minItems: 8
483
-
maxItems: 8
484
-
reset-names:
485
-
items:
486
-
- const: pipe # PIPE reset
487
-
- const: sticky # Core Sticky reset
488
-
- const: axi_s_sticky # AXI Slave Sticky reset
489
-
- const: axi_s # AXI Slave reset
490
-
- const: axi_m_sticky # AXI Master Sticky reset
491
-
- const: axi_m # AXI Master reset
492
-
- const: aux # AUX Reset
493
-
- const: ahb # AHB Reset
494
-
495
-
interrupts:
496
-
minItems: 8
497
-
interrupt-names:
498
-
minItems: 8
499
-
items:
500
-
- const: msi0
501
-
- const: msi1
502
-
- const: msi2
503
-
- const: msi3
504
-
- const: msi4
505
-
- const: msi5
506
-
- const: msi6
507
-
- const: msi7
508
-
- const: global
509
-
510
-
- if:
511
-
properties:
512
-
compatible:
513
-
contains:
514
-
enum:
515
-
- qcom,pcie-qcs404
516
-
then:
517
-
properties:
518
-
clocks:
519
-
minItems: 4
520
-
maxItems: 4
521
-
clock-names:
522
-
items:
523
-
- const: iface # AHB clock
524
-
- const: aux # Auxiliary clock
525
-
- const: master_bus # AXI Master clock
526
-
- const: slave_bus # AXI Slave clock
527
-
resets:
528
-
minItems: 6
529
-
maxItems: 6
530
-
reset-names:
531
-
items:
532
-
- const: axi_m # AXI Master reset
533
-
- const: axi_s # AXI Slave reset
534
-
- const: axi_m_sticky # AXI Master Sticky reset
535
-
- const: pipe_sticky # PIPE sticky reset
536
-
- const: pwr # PWR reset
537
-
- const: ahb # AHB reset
538
-
539
-
- if:
540
-
properties:
541
-
compatible:
542
-
contains:
543
-
enum:
544
-
- qcom,pcie-sdm845
545
-
then:
546
-
oneOf:
547
-
# Unfortunately the "optional" ref clock is used in the middle of the list
548
-
- properties:
549
-
clocks:
550
-
minItems: 8
551
-
maxItems: 8
552
-
clock-names:
553
-
items:
554
-
- const: pipe # PIPE clock
555
-
- const: aux # Auxiliary clock
556
-
- const: cfg # Configuration clock
557
-
- const: bus_master # Master AXI clock
558
-
- const: bus_slave # Slave AXI clock
559
-
- const: slave_q2a # Slave Q2A clock
560
-
- const: ref # REFERENCE clock
561
-
- const: tbu # PCIe TBU clock
562
-
- properties:
563
-
clocks:
564
-
minItems: 7
565
-
maxItems: 7
566
-
clock-names:
567
-
items:
568
-
- const: pipe # PIPE clock
569
-
- const: aux # Auxiliary clock
570
-
- const: cfg # Configuration clock
571
-
- const: bus_master # Master AXI clock
572
-
- const: bus_slave # Slave AXI clock
573
-
- const: slave_q2a # Slave Q2A clock
574
-
- const: tbu # PCIe TBU clock
575
-
properties:
576
-
resets:
577
-
maxItems: 1
578
-
reset-names:
579
-
items:
580
-
- const: pci # PCIe core reset
581
-
582
-
- if:
583
-
properties:
584
-
compatible:
585
-
contains:
586
-
enum:
587
-
- qcom,pcie-sdx55
588
-
then:
589
-
properties:
590
-
clocks:
591
-
minItems: 7
592
-
maxItems: 7
593
-
clock-names:
594
-
items:
595
-
- const: pipe # PIPE clock
596
-
- const: aux # Auxiliary clock
597
-
- const: cfg # Configuration clock
598
-
- const: bus_master # Master AXI clock
599
-
- const: bus_slave # Slave AXI clock
600
-
- const: slave_q2a # Slave Q2A clock
601
-
- const: sleep # PCIe Sleep clock
602
-
resets:
603
-
maxItems: 1
604
-
reset-names:
605
-
items:
606
-
- const: pci # PCIe core reset
607
-
608
-
- if:
609
-
not:
610
-
properties:
611
-
compatible:
612
-
contains:
613
-
enum:
614
-
- qcom,pcie-apq8064
615
-
- qcom,pcie-ipq4019
616
-
- qcom,pcie-ipq5018
617
-
- qcom,pcie-ipq8064
618
-
- qcom,pcie-ipq8064v2
619
-
- qcom,pcie-ipq8074
620
-
- qcom,pcie-ipq8074-gen3
621
-
- qcom,pcie-ipq9574
622
-
- qcom,pcie-qcs404
623
-
then:
624
-
required:
625
-
- power-domains
626
-
627
-
- if:
628
-
not:
629
-
properties:
630
-
compatible:
631
-
contains:
632
-
enum:
633
-
- qcom,pcie-msm8996
634
-
then:
635
-
required:
636
-
- resets
637
-
- reset-names
638
-
639
-
- if:
640
-
properties:
641
-
compatible:
642
-
contains:
643
-
enum:
644
-
- qcom,pcie-ipq6018
645
-
- qcom,pcie-ipq8074
646
-
- qcom,pcie-ipq8074-gen3
647
-
- qcom,pcie-msm8996
648
-
- qcom,pcie-msm8998
649
-
- qcom,pcie-sdm845
650
-
then:
651
-
oneOf:
652
-
- properties:
653
-
interrupts:
654
-
maxItems: 1
655
-
interrupt-names:
656
-
items:
657
-
- const: msi
658
-
- properties:
659
-
interrupts:
660
-
minItems: 8
661
-
maxItems: 9
662
-
interrupt-names:
663
-
minItems: 8
664
-
items:
665
-
- const: msi0
666
-
- const: msi1
667
-
- const: msi2
668
-
- const: msi3
669
-
- const: msi4
670
-
- const: msi5
671
-
- const: msi6
672
-
- const: msi7
673
-
- const: global
674
-
675
-
- if:
676
-
properties:
677
-
compatible:
678
-
contains:
679
-
enum:
680
-
- qcom,pcie-apq8064
681
-
- qcom,pcie-apq8084
682
-
- qcom,pcie-ipq4019
683
-
- qcom,pcie-ipq8064
684
-
- qcom,pcie-ipq8064-v2
685
-
- qcom,pcie-qcs404
686
-
then:
687
-
properties:
688
-
interrupts:
689
-
maxItems: 1
690
-
interrupt-names:
691
-
items:
692
-
- const: msi
693
-
694
-
unevaluatedProperties: false
695
-
696
-
examples:
697
-
- |
698
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
699
-
pcie@1b500000 {
700
-
compatible = "qcom,pcie-ipq8064";
701
-
reg = <0x1b500000 0x1000>,
702
-
<0x1b502000 0x80>,
703
-
<0x1b600000 0x100>,
704
-
<0x0ff00000 0x100000>;
705
-
reg-names = "dbi", "elbi", "parf", "config";
706
-
device_type = "pci";
707
-
linux,pci-domain = <0>;
708
-
bus-range = <0x00 0xff>;
709
-
num-lanes = <1>;
710
-
#address-cells = <3>;
711
-
#size-cells = <2>;
712
-
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
713
-
<0x82000000 0 0 0x08000000 0 0x07e00000>;
714
-
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
715
-
interrupt-names = "msi";
716
-
#interrupt-cells = <1>;
717
-
interrupt-map-mask = <0 0 0 0x7>;
718
-
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
719
-
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
720
-
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
721
-
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
722
-
clocks = <&gcc 41>,
723
-
<&gcc 43>,
724
-
<&gcc 44>,
725
-
<&gcc 42>,
726
-
<&gcc 248>;
727
-
clock-names = "core", "iface", "phy", "aux", "ref";
728
-
resets = <&gcc 27>,
729
-
<&gcc 26>,
730
-
<&gcc 25>,
731
-
<&gcc 24>,
732
-
<&gcc 23>,
733
-
<&gcc 22>;
734
-
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
735
-
pinctrl-0 = <&pcie_pins_default>;
736
-
pinctrl-names = "default";
737
-
vdda-supply = <&pm8921_s3>;
738
-
vdda_phy-supply = <&pm8921_lvs6>;
739
-
vdda_refclk-supply = <&ext_3p3v>;
740
-
};
741
-
- |
742
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
743
-
#include <dt-bindings/gpio/gpio.h>
744
-
pcie@fc520000 {
745
-
compatible = "qcom,pcie-apq8084";
746
-
reg = <0xfc520000 0x2000>,
747
-
<0xff000000 0x1000>,
748
-
<0xff001000 0x1000>,
749
-
<0xff002000 0x2000>;
750
-
reg-names = "parf", "dbi", "elbi", "config";
751
-
device_type = "pci";
752
-
linux,pci-domain = <0>;
753
-
bus-range = <0x00 0xff>;
754
-
num-lanes = <1>;
755
-
#address-cells = <3>;
756
-
#size-cells = <2>;
757
-
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
758
-
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
759
-
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
760
-
interrupt-names = "msi";
761
-
#interrupt-cells = <1>;
762
-
interrupt-map-mask = <0 0 0 0x7>;
763
-
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
764
-
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
765
-
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
766
-
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
767
-
clocks = <&gcc 324>,
768
-
<&gcc 325>,
769
-
<&gcc 327>,
770
-
<&gcc 323>;
771
-
clock-names = "iface", "master_bus", "slave_bus", "aux";
772
-
resets = <&gcc 81>;
773
-
reset-names = "core";
774
-
power-domains = <&gcc 1>;
775
-
vdda-supply = <&pma8084_l3>;
776
-
phys = <&pciephy0>;
777
-
phy-names = "pciephy";
778
-
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
779
-
pinctrl-0 = <&pcie0_pins_default>;
780
-
pinctrl-names = "default";
781
-
};
782
-
...
+2
-2
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml
+2
-2
Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml
···
51
51
phy-names:
52
52
const: pcie-phy
53
53
54
-
interrupt-controller:
54
+
legacy-interrupt-controller:
55
55
type: object
56
56
additionalProperties: false
57
57
···
111
111
<0 0 0 3 &pcie_intc 2>,
112
112
<0 0 0 4 &pcie_intc 3>;
113
113
114
-
pcie_intc: interrupt-controller {
114
+
pcie_intc: legacy-interrupt-controller {
115
115
#address-cells = <0>;
116
116
interrupt-controller;
117
117
#interrupt-cells = <1>;