Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-fixes-2026-02-05' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
- Fix the pixel normalization handling for xe3p_lpd display
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patch.msgid.link/aYROngKfyUIyoQW0@jlahtine-mobl
+26
-24
+1
drivers/gpu/drm/i915/display/intel_display_device.h
+1
drivers/gpu/drm/i915/display/intel_display_device.h
···
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#define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
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#define HAS_OVERLAY(__display) (DISPLAY_INFO(__display)->has_overlay)
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#define HAS_PIPEDMC(__display) (DISPLAY_VER(__display) >= 12)
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+
#define HAS_PIXEL_NORMALIZER(__display) (DISPLAY_VER(__display) >= 35)
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#define HAS_PSR(__display) (DISPLAY_INFO(__display)->has_psr)
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#define HAS_PSR_HW_TRACKING(__display) (DISPLAY_INFO(__display)->has_psr_hw_tracking)
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#define HAS_PSR2_SEL_FETCH(__display) (DISPLAY_VER(__display) >= 12)
+6
-4
drivers/gpu/drm/i915/display/intel_fbc.c
+6
-4
drivers/gpu/drm/i915/display/intel_fbc.c
···
1215
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}
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}
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1218
-
bool
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-
intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state)
1218
+
bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state)
1220
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{
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struct intel_display *display = to_intel_display(plane_state);
1222
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1223
-
return DISPLAY_VER(display) >= 35 &&
1224
-
xe3p_lpd_fbc_fp16_format_is_valid(plane_state);
1222
+
if (HAS_PIXEL_NORMALIZER(display) &&
1223
+
xe3p_lpd_fbc_fp16_format_is_valid(plane_state))
1224
+
return true;
1225
+
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+
return false;
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}
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static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
+1
-2
drivers/gpu/drm/i915/display/intel_fbc.h
+1
-2
drivers/gpu/drm/i915/display/intel_fbc.h
···
56
56
struct intel_crtc *crtc);
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void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
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struct intel_plane *plane);
59
-
bool
60
-
intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state);
59
+
bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state);
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#endif /* __INTEL_FBC_H__ */
+18
-18
drivers/gpu/drm/i915/display/skl_universal_plane.c
+18
-18
drivers/gpu/drm/i915/display/skl_universal_plane.c
···
891
891
intel_de_write_dsb(display, dsb, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
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}
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-
static void x3p_lpd_plane_update_pixel_normalizer(struct intel_dsb *dsb,
895
-
struct intel_plane *plane,
896
-
bool enable)
894
+
static bool plane_has_normalizer(struct intel_plane *plane)
897
895
{
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struct intel_display *display = to_intel_display(plane);
899
-
enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
900
-
u32 val;
901
897
902
-
/* Only HDR planes have pixel normalizer and don't matter if no FBC */
903
-
if (!skl_plane_has_fbc(display, fbc_id, plane->id))
904
-
return;
898
+
return HAS_PIXEL_NORMALIZER(display) && icl_is_hdr_plane(display, plane->id);
899
+
}
905
900
906
-
val = enable ? PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |
907
-
PLANE_PIXEL_NORMALIZE_ENABLE : 0;
901
+
static u32 pixel_normalizer_value(const struct intel_plane_state *plane_state)
902
+
{
903
+
if (!intel_fbc_need_pixel_normalizer(plane_state))
904
+
return 0;
908
905
909
-
intel_de_write_dsb(display, dsb,
910
-
PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), val);
906
+
return PLANE_PIXEL_NORMALIZE_ENABLE |
907
+
PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0);
911
908
}
912
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910
static void
···
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icl_plane_disable_sel_fetch_arm(dsb, plane, crtc_state);
925
928
926
-
if (DISPLAY_VER(display) >= 35)
927
-
x3p_lpd_plane_update_pixel_normalizer(dsb, plane, false);
929
+
if (plane_has_normalizer(plane))
930
+
intel_de_write_dsb(display, dsb,
931
+
PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id), 0);
928
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intel_de_write_dsb(display, dsb, PLANE_CTL(pipe, plane_id), 0);
930
934
intel_de_write_dsb(display, dsb, PLANE_SURF(pipe, plane_id), 0);
···
1674
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/*
1676
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* In order to have FBC for fp16 formats pixel normalizer block must be
1677
-
* active. Check if pixel normalizer block need to be enabled for FBC.
1678
-
* If needed, use normalization factor as 1.0 and enable the block.
1679
+
* active. For FP16 formats, use normalization factor as 1.0 and enable
1680
+
* the block.
1679
1681
*/
1680
-
if (intel_fbc_is_enable_pixel_normalizer(plane_state))
1681
-
x3p_lpd_plane_update_pixel_normalizer(dsb, plane, true);
1682
+
if (plane_has_normalizer(plane))
1683
+
intel_de_write_dsb(display, dsb,
1684
+
PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),
1685
+
pixel_normalizer_value(plane_state));
1682
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1687
/*
1684
1688
* The control register self-arms if the plane was previously