+4 -9

drivers/dma-buf/dma-fence-unwrap.c

reviewed

··· 76 76 dma_fence_unwrap_for_each(tmp, &iter[i], fences[i]) { 77 77 if (!dma_fence_is_signaled(tmp)) { 78 78 ++count; 79 79 - } else if (test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, 80 80 - &tmp->flags)) { 81 81 - if (ktime_after(tmp->timestamp, timestamp)) 82 82 - timestamp = tmp->timestamp; 83 79 } else { 84 84 - /* 85 85 - * Use the current time if the fence is 86 86 - * currently signaling. 87 87 - */ 88 88 - timestamp = ktime_get(); 80 80 + ktime_t t = dma_fence_timestamp(tmp); 81 81 + 82 82 + if (ktime_after(t, timestamp)) 83 83 + timestamp = t; 89 84 } 90 85 } 91 86 }

+3 -6

drivers/dma-buf/sync_file.c

reviewed

··· 268 268 sizeof(info->driver_name)); 269 269 270 270 info->status = dma_fence_get_status(fence); 271 271 - while (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && 272 272 - !test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags)) 273 273 - cpu_relax(); 274 271 info->timestamp_ns = 275 275 - test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags) ? 276 276 - ktime_to_ns(fence->timestamp) : 277 277 - ktime_set(0, 0); 272 272 + dma_fence_is_signaled(fence) ? 273 273 + ktime_to_ns(dma_fence_timestamp(fence)) : 274 274 + ktime_set(0, 0); 278 275 279 276 return info->status; 280 277 }

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.c

reviewed

··· 142 142 int r; 143 143 int size; 144 144 145 145 + /* SI HW does not have doorbells, skip allocation */ 146 146 + if (adev->doorbell.num_kernel_doorbells == 0) 147 147 + return 0; 148 148 + 145 149 /* Reserve first num_kernel_doorbells (page-aligned) for kernel ops */ 146 150 size = ALIGN(adev->doorbell.num_kernel_doorbells * sizeof(u32), PAGE_SIZE); 147 151

+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

reviewed

··· 252 252 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 253 253 struct amdgpu_res_cursor cursor; 254 254 255 255 - if (bo->tbo.resource->mem_type != TTM_PL_VRAM) 255 255 + if (!bo->tbo.resource || bo->tbo.resource->mem_type != TTM_PL_VRAM) 256 256 return false; 257 257 258 258 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);

+3

drivers/gpu/drm/amd/display/dc/core/dc.c

reviewed

··· 1262 1262 if (stream == NULL) 1263 1263 continue; 1264 1264 1265 1265 + if (stream->apply_seamless_boot_optimization) 1266 1266 + continue; 1267 1267 + 1265 1268 // only looking for first odm pipe 1266 1269 if (pipe->prev_odm_pipe) 1267 1270 continue;

+13 -4

drivers/gpu/drm/drm_atomic_helper.c

reviewed

··· 290 290 update_connector_routing(struct drm_atomic_state *state, 291 291 struct drm_connector *connector, 292 292 struct drm_connector_state *old_connector_state, 293 293 - struct drm_connector_state *new_connector_state) 293 293 + struct drm_connector_state *new_connector_state, 294 294 + bool added_by_user) 294 295 { 295 296 const struct drm_connector_helper_funcs *funcs; 296 297 struct drm_encoder *new_encoder; ··· 340 339 * there's a chance the connector may have been destroyed during the 341 340 * process, but it's better to ignore that then cause 342 341 * drm_atomic_helper_resume() to fail. 342 342 + * 343 343 + * Last, we want to ignore connector registration when the connector 344 344 + * was not pulled in the atomic state by user-space (ie, was pulled 345 345 + * in by the driver, e.g. when updating a DP-MST stream). 343 346 */ 344 347 if (!state->duplicated && drm_connector_is_unregistered(connector) && 345 345 - crtc_state->active) { 348 348 + added_by_user && crtc_state->active) { 346 349 drm_dbg_atomic(connector->dev, 347 350 "[CONNECTOR:%d:%s] is not registered\n", 348 351 connector->base.id, connector->name); ··· 625 620 struct drm_connector *connector; 626 621 struct drm_connector_state *old_connector_state, *new_connector_state; 627 622 int i, ret; 628 628 - unsigned int connectors_mask = 0; 623 623 + unsigned int connectors_mask = 0, user_connectors_mask = 0; 624 624 + 625 625 + for_each_oldnew_connector_in_state(state, connector, old_connector_state, new_connector_state, i) 626 626 + user_connectors_mask |= BIT(i); 629 627 630 628 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 631 629 bool has_connectors = ··· 693 685 */ 694 686 ret = update_connector_routing(state, connector, 695 687 old_connector_state, 696 696 - new_connector_state); 688 688 + new_connector_state, 689 689 + BIT(i) & user_connectors_mask); 697 690 if (ret) 698 691 return ret; 699 692 if (old_connector_state->crtc) {

+4 -2

drivers/gpu/drm/drm_gem.c

reviewed

··· 540 540 struct page **pages; 541 541 struct folio *folio; 542 542 struct folio_batch fbatch; 543 543 - int i, j, npages; 543 543 + long i, j, npages; 544 544 545 545 if (WARN_ON(!obj->filp)) 546 546 return ERR_PTR(-EINVAL); ··· 564 564 565 565 i = 0; 566 566 while (i < npages) { 567 567 + long nr; 567 568 folio = shmem_read_folio_gfp(mapping, i, 568 569 mapping_gfp_mask(mapping)); 569 570 if (IS_ERR(folio)) 570 571 goto fail; 571 571 - for (j = 0; j < folio_nr_pages(folio); j++, i++) 572 572 + nr = min(npages - i, folio_nr_pages(folio)); 573 573 + for (j = 0; j < nr; j++, i++) 572 574 pages[i] = folio_file_page(folio, i); 573 575 574 576 /* Make sure shmem keeps __GFP_DMA32 allocated pages in the

+18 -9

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

reviewed

··· 119 119 struct dpu_sw_pipe_cfg *pipe_cfg) 120 120 { 121 121 int src_width, src_height, dst_height, fps; 122 122 + u64 plane_pixel_rate, plane_bit_rate; 122 123 u64 plane_prefill_bw; 123 124 u64 plane_bw; 124 125 u32 hw_latency_lines; ··· 137 136 scale_factor = src_height > dst_height ? 138 137 mult_frac(src_height, 1, dst_height) : 1; 139 138 140 140 - plane_bw = 141 141 - src_width * mode->vtotal * fps * fmt->bpp * 142 142 - scale_factor; 139 139 + plane_pixel_rate = src_width * mode->vtotal * fps; 140 140 + plane_bit_rate = plane_pixel_rate * fmt->bpp; 143 141 144 144 - plane_prefill_bw = 145 145 - src_width * hw_latency_lines * fps * fmt->bpp * 146 146 - scale_factor * mode->vtotal; 142 142 + plane_bw = plane_bit_rate * scale_factor; 143 143 + 144 144 + plane_prefill_bw = plane_bw * hw_latency_lines; 147 145 148 146 if ((vbp+vpw) > hw_latency_lines) 149 147 do_div(plane_prefill_bw, (vbp+vpw)); ··· 733 733 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, 734 734 struct dpu_sw_pipe *pipe, 735 735 struct dpu_sw_pipe_cfg *pipe_cfg, 736 736 - const struct dpu_format *fmt) 736 736 + const struct dpu_format *fmt, 737 737 + const struct drm_display_mode *mode) 737 738 { 738 739 uint32_t min_src_size; 740 740 + struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); 739 741 740 742 min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; 741 743 ··· 774 772 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n", 775 773 DRM_RECT_ARG(&pipe_cfg->dst_rect)); 776 774 return -EINVAL; 775 775 + } 776 776 + 777 777 + /* max clk check */ 778 778 + if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { 779 779 + DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); 780 780 + return -E2BIG; 777 781 } 778 782 779 783 return 0; ··· 907 899 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; 908 900 } 909 901 910 910 - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt); 902 902 + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); 911 903 if (ret) 912 904 return ret; 913 905 914 906 if (r_pipe->sspp) { 915 915 - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt); 907 907 + ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, 908 908 + &crtc_state->adjusted_mode); 916 909 if (ret) 917 910 return ret; 918 911 }

+6 -7

drivers/gpu/drm/msm/dp/dp_ctrl.c

reviewed

··· 1774 1774 return rc; 1775 1775 1776 1776 while (--link_train_max_retries) { 1777 1777 - rc = dp_ctrl_reinitialize_mainlink(ctrl); 1778 1778 - if (rc) { 1779 1779 - DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", 1780 1780 - rc); 1781 1781 - break; 1782 1782 - } 1783 1783 - 1784 1777 training_step = DP_TRAINING_NONE; 1785 1778 rc = dp_ctrl_setup_main_link(ctrl, &training_step); 1786 1779 if (rc == 0) { ··· 1824 1831 1825 1832 /* stop link training before start re training */ 1826 1833 dp_ctrl_clear_training_pattern(ctrl); 1834 1834 + } 1835 1835 + 1836 1836 + rc = dp_ctrl_reinitialize_mainlink(ctrl); 1837 1837 + if (rc) { 1838 1838 + DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n", rc); 1839 1839 + break; 1827 1840 } 1828 1841 } 1829 1842

+2 -2

drivers/gpu/drm/msm/dp/dp_link.c

reviewed

··· 1090 1090 } else if (dp_link_read_psr_error_status(link)) { 1091 1091 DRM_ERROR("PSR IRQ_HPD received\n"); 1092 1092 } else if (dp_link_psr_capability_changed(link)) { 1093 1093 - drm_dbg_dp(link->drm_dev, "PSR Capability changed"); 1093 1093 + drm_dbg_dp(link->drm_dev, "PSR Capability changed\n"); 1094 1094 } else { 1095 1095 ret = dp_link_process_link_status_update(link); 1096 1096 if (!ret) { ··· 1107 1107 } 1108 1108 } 1109 1109 1110 1110 - drm_dbg_dp(link->drm_dev, "sink request=%#x", 1110 1110 + drm_dbg_dp(link->drm_dev, "sink request=%#x\n", 1111 1111 dp_link->sink_request); 1112 1112 return ret; 1113 1113 }

+15 -4

drivers/gpu/drm/msm/dsi/dsi_host.c

reviewed

··· 1082 1082 1083 1083 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1084 1084 { 1085 1085 + u32 data; 1086 1086 + 1085 1087 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1088 1088 + return; 1089 1089 + 1090 1090 + data = dsi_read(msm_host, REG_DSI_STATUS0); 1091 1091 + 1092 1092 + /* if video mode engine is not busy, its because 1093 1093 + * either timing engine was not turned on or the 1094 1094 + * DSI controller has finished transmitting the video 1095 1095 + * data already, so no need to wait in those cases 1096 1096 + */ 1097 1097 + if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1086 1098 return; 1087 1099 1088 1100 if (msm_host->power_on && msm_host->enabled) { ··· 1906 1894 } 1907 1895 1908 1896 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1909 1909 - if (msm_host->irq < 0) { 1910 1910 - ret = msm_host->irq; 1911 1911 - dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 1912 1912 - return ret; 1897 1897 + if (!msm_host->irq) { 1898 1898 + dev_err(&pdev->dev, "failed to get irq\n"); 1899 1899 + return -EINVAL; 1913 1900 } 1914 1901 1915 1902 /* do not autoenable, will be enabled later */

+1 -1

drivers/gpu/drm/msm/msm_mdss.c

reviewed

··· 511 511 static const struct msm_mdss_data msm8998_data = { 512 512 .ubwc_enc_version = UBWC_1_0, 513 513 .ubwc_dec_version = UBWC_1_0, 514 514 - .highest_bank_bit = 1, 514 514 + .highest_bank_bit = 2, 515 515 }; 516 516 517 517 static const struct msm_mdss_data qcm2290_data = {

+1 -3

drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c

reviewed

··· 1342 1342 _INIT_DCS_CMD(0xB1, 0x01, 0xBF, 0x11), 1343 1343 _INIT_DCS_CMD(0xCB, 0x86), 1344 1344 _INIT_DCS_CMD(0xD2, 0x3C, 0xFA), 1345 1345 - _INIT_DCS_CMD(0xE9, 0xC5), 1346 1346 - _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), 1347 1347 - _INIT_DCS_CMD(0xE9, 0x3F), 1345 1345 + _INIT_DCS_CMD(0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), 1348 1346 _INIT_DCS_CMD(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40), 1349 1347 _INIT_DCS_CMD(0xBD, 0x02), 1350 1348 _INIT_DCS_CMD(0xD8, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0, 0xFF, 0xFF, 0xBF, 0xFE, 0xAA, 0xA0),

+1 -1

drivers/gpu/drm/scheduler/sched_main.c

reviewed

··· 929 929 930 930 if (next) { 931 931 next->s_fence->scheduled.timestamp = 932 932 - job->s_fence->finished.timestamp; 932 932 + dma_fence_timestamp(&job->s_fence->finished); 933 933 /* start TO timer for next job */ 934 934 drm_sched_start_timeout(sched); 935 935 }

+1 -1

drivers/gpu/drm/tiny/simpledrm.c

reviewed

··· 745 745 746 746 ret = devm_aperture_acquire_from_firmware(dev, res->start, resource_size(res)); 747 747 if (ret) { 748 748 - drm_err(dev, "could not acquire memory range %pr: %d\n", &res, ret); 748 748 + drm_err(dev, "could not acquire memory range %pr: %d\n", res, ret); 749 749 return ERR_PTR(ret); 750 750 } 751 751

+4 -3

drivers/gpu/drm/vmwgfx/vmwgfx_bo.c

reviewed

··· 34 34 35 35 static void vmw_bo_release(struct vmw_bo *vbo) 36 36 { 37 37 + WARN_ON(vbo->tbo.base.funcs && 38 38 + kref_read(&vbo->tbo.base.refcount) != 0); 37 39 vmw_bo_unmap(vbo); 38 40 drm_gem_object_release(&vbo->tbo.base); 39 41 } ··· 499 497 if (!(flags & drm_vmw_synccpu_allow_cs)) { 500 498 atomic_dec(&vmw_bo->cpu_writers); 501 499 } 502 502 - vmw_user_bo_unref(vmw_bo); 500 500 + vmw_user_bo_unref(&vmw_bo); 503 501 } 504 502 505 503 return ret; ··· 541 539 return ret; 542 540 543 541 ret = vmw_user_bo_synccpu_grab(vbo, arg->flags); 544 544 - vmw_user_bo_unref(vbo); 542 542 + vmw_user_bo_unref(&vbo); 545 543 if (unlikely(ret != 0)) { 546 544 if (ret == -ERESTARTSYS || ret == -EBUSY) 547 545 return -EBUSY; ··· 614 612 } 615 613 616 614 *out = to_vmw_bo(gobj); 617 617 - ttm_bo_get(&(*out)->tbo); 618 615 619 616 return 0; 620 617 }

+12 -5

drivers/gpu/drm/vmwgfx/vmwgfx_bo.h

reviewed

··· 195 195 return buf; 196 196 } 197 197 198 198 - static inline void vmw_user_bo_unref(struct vmw_bo *vbo) 198 198 + static inline struct vmw_bo *vmw_user_bo_ref(struct vmw_bo *vbo) 199 199 { 200 200 - if (vbo) { 201 201 - ttm_bo_put(&vbo->tbo); 202 202 - drm_gem_object_put(&vbo->tbo.base); 203 203 - } 200 200 + drm_gem_object_get(&vbo->tbo.base); 201 201 + return vbo; 202 202 + } 203 203 + 204 204 + static inline void vmw_user_bo_unref(struct vmw_bo **buf) 205 205 + { 206 206 + struct vmw_bo *tmp_buf = *buf; 207 207 + 208 208 + *buf = NULL; 209 209 + if (tmp_buf) 210 210 + drm_gem_object_put(&tmp_buf->tbo.base); 204 211 } 205 212 206 213 static inline struct vmw_bo *to_vmw_bo(struct drm_gem_object *gobj)

+3 -3

drivers/gpu/drm/vmwgfx/vmwgfx_cotable.c

reviewed

··· 432 432 * for the new COTable. Initially pin the buffer object to make sure 433 433 * we can use tryreserve without failure. 434 434 */ 435 435 - ret = vmw_bo_create(dev_priv, &bo_params, &buf); 435 435 + ret = vmw_gem_object_create(dev_priv, &bo_params, &buf); 436 436 if (ret) { 437 437 DRM_ERROR("Failed initializing new cotable MOB.\n"); 438 438 goto out_done; ··· 502 502 503 503 vmw_resource_mob_attach(res); 504 504 /* Let go of the old mob. */ 505 505 - vmw_bo_unreference(&old_buf); 505 505 + vmw_user_bo_unref(&old_buf); 506 506 res->id = vcotbl->type; 507 507 508 508 ret = dma_resv_reserve_fences(bo->base.resv, 1); ··· 521 521 out_wait: 522 522 ttm_bo_unpin(bo); 523 523 ttm_bo_unreserve(bo); 524 524 - vmw_bo_unreference(&buf); 524 524 + vmw_user_bo_unref(&buf); 525 525 526 526 out_done: 527 527 MKS_STAT_TIME_POP(MKSSTAT_KERN_COTABLE_RESIZE);

+4

drivers/gpu/drm/vmwgfx/vmwgfx_drv.h

reviewed

··· 853 853 /** 854 854 * GEM related functionality - vmwgfx_gem.c 855 855 */ 856 856 + struct vmw_bo_params; 857 857 + int vmw_gem_object_create(struct vmw_private *vmw, 858 858 + struct vmw_bo_params *params, 859 859 + struct vmw_bo **p_vbo); 856 860 extern int vmw_gem_object_create_with_handle(struct vmw_private *dev_priv, 857 861 struct drm_file *filp, 858 862 uint32_t size,

+7 -5

drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c

reviewed

··· 1151 1151 SVGAMobId *id, 1152 1152 struct vmw_bo **vmw_bo_p) 1153 1153 { 1154 1154 - struct vmw_bo *vmw_bo; 1154 1154 + struct vmw_bo *vmw_bo, *tmp_bo; 1155 1155 uint32_t handle = *id; 1156 1156 struct vmw_relocation *reloc; 1157 1157 int ret; ··· 1164 1164 } 1165 1165 vmw_bo_placement_set(vmw_bo, VMW_BO_DOMAIN_MOB, VMW_BO_DOMAIN_MOB); 1166 1166 ret = vmw_validation_add_bo(sw_context->ctx, vmw_bo); 1167 1167 - vmw_user_bo_unref(vmw_bo); 1167 1167 + tmp_bo = vmw_bo; 1168 1168 + vmw_user_bo_unref(&tmp_bo); 1168 1169 if (unlikely(ret != 0)) 1169 1170 return ret; 1170 1171 ··· 1207 1206 SVGAGuestPtr *ptr, 1208 1207 struct vmw_bo **vmw_bo_p) 1209 1208 { 1210 1210 - struct vmw_bo *vmw_bo; 1209 1209 + struct vmw_bo *vmw_bo, *tmp_bo; 1211 1210 uint32_t handle = ptr->gmrId; 1212 1211 struct vmw_relocation *reloc; 1213 1212 int ret; ··· 1221 1220 vmw_bo_placement_set(vmw_bo, VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM, 1222 1221 VMW_BO_DOMAIN_GMR | VMW_BO_DOMAIN_VRAM); 1223 1222 ret = vmw_validation_add_bo(sw_context->ctx, vmw_bo); 1224 1224 - vmw_user_bo_unref(vmw_bo); 1223 1223 + tmp_bo = vmw_bo; 1224 1224 + vmw_user_bo_unref(&tmp_bo); 1225 1225 if (unlikely(ret != 0)) 1226 1226 return ret; 1227 1227 ··· 1621 1619 { 1622 1620 VMW_DECLARE_CMD_VAR(*cmd, SVGA3dCmdSetTextureState); 1623 1621 SVGA3dTextureState *last_state = (SVGA3dTextureState *) 1624 1624 - ((unsigned long) header + header->size + sizeof(header)); 1622 1622 + ((unsigned long) header + header->size + sizeof(*header)); 1625 1623 SVGA3dTextureState *cur_state = (SVGA3dTextureState *) 1626 1624 ((unsigned long) header + sizeof(*cmd)); 1627 1625 struct vmw_resource *ctx;

+15 -3

drivers/gpu/drm/vmwgfx/vmwgfx_gem.c

reviewed

··· 111 111 .vm_ops = &vmw_vm_ops, 112 112 }; 113 113 114 114 + int vmw_gem_object_create(struct vmw_private *vmw, 115 115 + struct vmw_bo_params *params, 116 116 + struct vmw_bo **p_vbo) 117 117 + { 118 118 + int ret = vmw_bo_create(vmw, params, p_vbo); 119 119 + 120 120 + if (ret != 0) 121 121 + goto out_no_bo; 122 122 + 123 123 + (*p_vbo)->tbo.base.funcs = &vmw_gem_object_funcs; 124 124 + out_no_bo: 125 125 + return ret; 126 126 + } 127 127 + 114 128 int vmw_gem_object_create_with_handle(struct vmw_private *dev_priv, 115 129 struct drm_file *filp, 116 130 uint32_t size, ··· 140 126 .pin = false 141 127 }; 142 128 143 143 - ret = vmw_bo_create(dev_priv, &params, p_vbo); 129 129 + ret = vmw_gem_object_create(dev_priv, &params, p_vbo); 144 130 if (ret != 0) 145 131 goto out_no_bo; 146 146 - 147 147 - (*p_vbo)->tbo.base.funcs = &vmw_gem_object_funcs; 148 132 149 133 ret = drm_gem_handle_create(filp, &(*p_vbo)->tbo.base, handle); 150 134 out_no_bo:

+3 -3

drivers/gpu/drm/vmwgfx/vmwgfx_kms.c

reviewed

··· 1471 1471 /* Reserve and switch the backing mob. */ 1472 1472 mutex_lock(&res->dev_priv->cmdbuf_mutex); 1473 1473 (void) vmw_resource_reserve(res, false, true); 1474 1474 - vmw_bo_unreference(&res->guest_memory_bo); 1475 1475 - res->guest_memory_bo = vmw_bo_reference(bo_mob); 1474 1474 + vmw_user_bo_unref(&res->guest_memory_bo); 1475 1475 + res->guest_memory_bo = vmw_user_bo_ref(bo_mob); 1476 1476 res->guest_memory_offset = 0; 1477 1477 vmw_resource_unreserve(res, false, false, false, NULL, 0); 1478 1478 mutex_unlock(&res->dev_priv->cmdbuf_mutex); ··· 1666 1666 err_out: 1667 1667 /* vmw_user_lookup_handle takes one ref so does new_fb */ 1668 1668 if (bo) 1669 1669 - vmw_user_bo_unref(bo); 1669 1669 + vmw_user_bo_unref(&bo); 1670 1670 if (surface) 1671 1671 vmw_surface_unreference(&surface); 1672 1672

+1 -1

drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c

reviewed

··· 451 451 452 452 ret = vmw_overlay_update_stream(dev_priv, buf, arg, true); 453 453 454 454 - vmw_user_bo_unref(buf); 454 454 + vmw_user_bo_unref(&buf); 455 455 456 456 out_unlock: 457 457 mutex_unlock(&overlay->mutex);

+6 -6

drivers/gpu/drm/vmwgfx/vmwgfx_resource.c

reviewed

··· 141 141 if (res->coherent) 142 142 vmw_bo_dirty_release(res->guest_memory_bo); 143 143 ttm_bo_unreserve(bo); 144 144 - vmw_bo_unreference(&res->guest_memory_bo); 144 144 + vmw_user_bo_unref(&res->guest_memory_bo); 145 145 } 146 146 147 147 if (likely(res->hw_destroy != NULL)) { ··· 338 338 return 0; 339 339 } 340 340 341 341 - ret = vmw_bo_create(res->dev_priv, &bo_params, &gbo); 341 341 + ret = vmw_gem_object_create(res->dev_priv, &bo_params, &gbo); 342 342 if (unlikely(ret != 0)) 343 343 goto out_no_bo; 344 344 ··· 457 457 vmw_resource_mob_detach(res); 458 458 if (res->coherent) 459 459 vmw_bo_dirty_release(res->guest_memory_bo); 460 460 - vmw_bo_unreference(&res->guest_memory_bo); 460 460 + vmw_user_bo_unref(&res->guest_memory_bo); 461 461 } 462 462 463 463 if (new_guest_memory_bo) { 464 464 - res->guest_memory_bo = vmw_bo_reference(new_guest_memory_bo); 464 464 + res->guest_memory_bo = vmw_user_bo_ref(new_guest_memory_bo); 465 465 466 466 /* 467 467 * The validation code should already have added a ··· 551 551 ttm_bo_put(val_buf->bo); 552 552 val_buf->bo = NULL; 553 553 if (guest_memory_dirty) 554 554 - vmw_bo_unreference(&res->guest_memory_bo); 554 554 + vmw_user_bo_unref(&res->guest_memory_bo); 555 555 556 556 return ret; 557 557 } ··· 727 727 goto out_no_validate; 728 728 else if (!res->func->needs_guest_memory && res->guest_memory_bo) { 729 729 WARN_ON_ONCE(vmw_resource_mob_attached(res)); 730 730 - vmw_bo_unreference(&res->guest_memory_bo); 730 730 + vmw_user_bo_unref(&res->guest_memory_bo); 731 731 } 732 732 733 733 return 0;

+2 -2

drivers/gpu/drm/vmwgfx/vmwgfx_shader.c

reviewed

··· 180 180 181 181 res->guest_memory_size = size; 182 182 if (byte_code) { 183 183 - res->guest_memory_bo = vmw_bo_reference(byte_code); 183 183 + res->guest_memory_bo = vmw_user_bo_ref(byte_code); 184 184 res->guest_memory_offset = offset; 185 185 } 186 186 shader->size = size; ··· 809 809 shader_type, num_input_sig, 810 810 num_output_sig, tfile, shader_handle); 811 811 out_bad_arg: 812 812 - vmw_user_bo_unref(buffer); 812 812 + vmw_user_bo_unref(&buffer); 813 813 return ret; 814 814 } 815 815

+11 -18

drivers/gpu/drm/vmwgfx/vmwgfx_surface.c

reviewed

··· 686 686 container_of(base, struct vmw_user_surface, prime.base); 687 687 struct vmw_resource *res = &user_srf->srf.res; 688 688 689 689 - if (res->guest_memory_bo) 690 690 - drm_gem_object_put(&res->guest_memory_bo->tbo.base); 691 691 - 692 689 *p_base = NULL; 693 690 vmw_resource_unreference(&res); 694 691 } ··· 852 855 * expect a backup buffer to be present. 853 856 */ 854 857 if (dev_priv->has_mob && req->shareable) { 855 855 - uint32_t backup_handle; 858 858 + struct vmw_bo_params params = { 859 859 + .domain = VMW_BO_DOMAIN_SYS, 860 860 + .busy_domain = VMW_BO_DOMAIN_SYS, 861 861 + .bo_type = ttm_bo_type_device, 862 862 + .size = res->guest_memory_size, 863 863 + .pin = false 864 864 + }; 856 865 857 857 - ret = vmw_gem_object_create_with_handle(dev_priv, 858 858 - file_priv, 859 859 - res->guest_memory_size, 860 860 - &backup_handle, 861 861 - &res->guest_memory_bo); 866 866 + ret = vmw_gem_object_create(dev_priv, 867 867 + &params, 868 868 + &res->guest_memory_bo); 862 869 if (unlikely(ret != 0)) { 863 870 vmw_resource_unreference(&res); 864 871 goto out_unlock; 865 872 } 866 866 - vmw_bo_reference(res->guest_memory_bo); 867 867 - /* 868 868 - * We don't expose the handle to the userspace and surface 869 869 - * already holds a gem reference 870 870 - */ 871 871 - drm_gem_handle_delete(file_priv, backup_handle); 872 873 } 873 874 874 875 tmp = vmw_resource_reference(&srf->res); ··· 1507 1512 if (ret == 0) { 1508 1513 if (res->guest_memory_bo->tbo.base.size < res->guest_memory_size) { 1509 1514 VMW_DEBUG_USER("Surface backup buffer too small.\n"); 1510 1510 - vmw_bo_unreference(&res->guest_memory_bo); 1515 1515 + vmw_user_bo_unref(&res->guest_memory_bo); 1511 1516 ret = -EINVAL; 1512 1517 goto out_unlock; 1513 1518 } else { ··· 1521 1526 res->guest_memory_size, 1522 1527 &backup_handle, 1523 1528 &res->guest_memory_bo); 1524 1524 - if (ret == 0) 1525 1525 - vmw_bo_reference(res->guest_memory_bo); 1526 1529 } 1527 1530 1528 1531 if (unlikely(ret != 0)) {

+19

include/linux/dma-fence.h

reviewed

··· 568 568 fence->error = error; 569 569 } 570 570 571 571 + /** 572 572 + * dma_fence_timestamp - helper to get the completion timestamp of a fence 573 573 + * @fence: fence to get the timestamp from. 574 574 + * 575 575 + * After a fence is signaled the timestamp is updated with the signaling time, 576 576 + * but setting the timestamp can race with tasks waiting for the signaling. This 577 577 + * helper busy waits for the correct timestamp to appear. 578 578 + */ 579 579 + static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) 580 580 + { 581 581 + if (WARN_ON(!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) 582 582 + return ktime_get(); 583 583 + 584 584 + while (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags)) 585 585 + cpu_relax(); 586 586 + 587 587 + return fence->timestamp; 588 588 + } 589 589 + 571 590 signed long dma_fence_wait_timeout(struct dma_fence *, 572 591 bool intr, signed long timeout); 573 592 signed long dma_fence_wait_any_timeout(struct dma_fence **fences,