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phy: phy-rockchip-samsung-hdptx: Enable runtime PM at PHY core level

When a new PHY is created via [devm_]phy_create(), the runtime PM for it
is not enabled unless the parent device (which creates the PHY) has its
own runtime PM already enabled.

Move the call to devm_pm_runtime_enable() before devm_phy_create() to
enable runtime PM at PHY core level.

With this change the ->power_on() and ->power_off() callbacks do not
require explicit runtime PM management anymore, since the PHY core
handles that via phy_pm_runtime_{get,put}_sync() when phy_power_on() and
phy_power_off() are invoked.

Hence drop the now unnecessary calls to pm_runtime_resume_and_get() and
pm_runtime_put() helpers.

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-2-6a2d2164e508@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Cristian Ciocaltea and committed by
Vinod Koul 10ba8479 1b369ff9

+6 -18
+6 -18
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
··· 860 860 static int rk_hdptx_phy_power_on(struct phy *phy) 861 861 { 862 862 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 863 - int ret, bus_width = phy_get_bus_width(hdptx->phy); 863 + int bus_width = phy_get_bus_width(hdptx->phy); 864 864 /* 865 865 * FIXME: Temporary workaround to pass pixel_clk_rate 866 866 * from the HDMI bridge driver until phy_configure_opts_hdmi ··· 871 871 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n", 872 872 __func__, bus_width, rate); 873 873 874 - ret = pm_runtime_resume_and_get(hdptx->dev); 875 - if (ret) { 876 - dev_err(hdptx->dev, "Failed to resume phy: %d\n", ret); 877 - return ret; 878 - } 879 - 880 - ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate); 881 - if (ret) 882 - pm_runtime_put(hdptx->dev); 883 - 884 - return ret; 874 + return rk_hdptx_ropll_tmds_mode_config(hdptx, rate); 885 875 } 886 876 887 877 static int rk_hdptx_phy_power_off(struct phy *phy) ··· 883 893 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &val); 884 894 if (ret == 0 && (val & HDPTX_O_PLL_LOCK_DONE)) 885 895 rk_hdptx_phy_disable(hdptx); 886 - 887 - pm_runtime_put(hdptx->dev); 888 896 889 897 return ret; 890 898 } ··· 965 977 return dev_err_probe(dev, PTR_ERR(hdptx->grf), 966 978 "Could not get GRF syscon\n"); 967 979 980 + ret = devm_pm_runtime_enable(dev); 981 + if (ret) 982 + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 983 + 968 984 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); 969 985 if (IS_ERR(hdptx->phy)) 970 986 return dev_err_probe(dev, PTR_ERR(hdptx->phy), ··· 977 985 platform_set_drvdata(pdev, hdptx); 978 986 phy_set_drvdata(hdptx->phy, hdptx); 979 987 phy_set_bus_width(hdptx->phy, 8); 980 - 981 - ret = devm_pm_runtime_enable(dev); 982 - if (ret) 983 - return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 984 988 985 989 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 986 990 if (IS_ERR(phy_provider))