tjh.dev / kernel
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coresight: Change syncfreq to be a u8

TRCSYNCPR.PERIOD is the only functional part of TRCSYNCPR and it only
has 5 valid bits so it can be stored in a u8.

Reviewed-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Tested-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-1-4d319764cc58@linaro.org

authored by

James Clark and committed by
Suzuki K Poulose 10d4dbdc 51cd1fb7

+1 -1
+1 -1
drivers/hwtracing/coresight/coresight-etm4x.h
··· 825 825 u32 eventctrl1; 826 826 u32 stall_ctrl; 827 827 u32 ts_ctrl; 828 - u32 syncfreq; 829 828 u32 ccctlr; 830 829 u32 bb_ctrl; 831 830 u32 vinst_ctrl; ··· 832 833 u32 vissctlr; 833 834 u32 vipcssctlr; 834 835 u8 seq_idx; 836 + u8 syncfreq; 835 837 u32 seq_ctrl[ETM_MAX_SEQ_STATES]; 836 838 u32 seq_rst; 837 839 u32 seq_state;