Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'iommu-fixes-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
Pull iommu fixes from Joerg Roedel:
- Per-domain device-list locking fixes for the AMD IOMMU driver
- Fix incorrect use of smp_processor_id() in the NVidia-specific part
of the ARM-SMMU-v3 driver
- Intel IOMMU driver fixes:
- Remove cache tags before disabling ATS
- Avoid draining PRQ in sva mm release path
- Fix qi_batch NULL pointer with nested parent domain
* tag 'iommu-fixes-v6.13-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux:
iommu/vt-d: Avoid draining PRQ in sva mm release path
iommu/vt-d: Fix qi_batch NULL pointer with nested parent domain
iommu/vt-d: Remove cache tags before disabling ATS
iommu/amd: Add lockdep asserts for domain->dev_list
iommu/amd: Put list_add/del(dev_data) back under the domain->lock
iommu/tegra241-cmdqv: do not use smp_processor_id in preemptible context
+42
-11
+9
-1
drivers/iommu/amd/iommu.c
+9
-1
drivers/iommu/amd/iommu.c
···
1415
1415
struct iommu_cmd cmd;
1416
1416
int ret = 0;
1417
1417
1418
+
lockdep_assert_held(&pdom->lock);
1418
1419
list_for_each_entry(dev_data, &pdom->dev_list, list) {
1419
1420
struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);
1420
1421
u16 domid = dev_data->gcr3_info.domid;
···
1464
1463
int ret = 0;
1465
1464
ioasid_t pasid = IOMMU_NO_PASID;
1466
1465
bool gn = false;
1466
+
1467
+
lockdep_assert_held(&domain->lock);
1467
1468
1468
1469
if (pdom_is_v2_pgtbl_mode(domain)) {
1469
1470
gn = true;
···
1587
1584
void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1588
1585
{
1589
1586
struct iommu_dev_data *dev_data;
1587
+
1588
+
lockdep_assert_held(&domain->lock);
1590
1589
1591
1590
list_for_each_entry(dev_data, &domain->dev_list, list) {
1592
1591
struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev);
···
2078
2073
struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2079
2074
struct amd_iommu *iommu = get_amd_iommu_from_dev_data(dev_data);
2080
2075
struct pci_dev *pdev;
2076
+
unsigned long flags;
2081
2077
int ret = 0;
2082
2078
2083
2079
mutex_lock(&dev_data->mutex);
···
2119
2113
2120
2114
/* Update data structures */
2121
2115
dev_data->domain = domain;
2116
+
spin_lock_irqsave(&domain->lock, flags);
2122
2117
list_add(&dev_data->list, &domain->dev_list);
2118
+
spin_unlock_irqrestore(&domain->lock, flags);
2123
2119
2124
2120
/* Update device table */
2125
2121
dev_update_dte(dev_data, true);
···
2168
2160
/* Flush IOTLB and wait for the flushes to finish */
2169
2161
spin_lock_irqsave(&domain->lock, flags);
2170
2162
amd_iommu_domain_flush_all(domain);
2163
+
list_del(&dev_data->list);
2171
2164
spin_unlock_irqrestore(&domain->lock, flags);
2172
2165
2173
2166
/* Clear GCR3 table */
···
2177
2168
2178
2169
/* Update data structures */
2179
2170
dev_data->domain = NULL;
2180
-
list_del(&dev_data->list);
2181
2171
2182
2172
/* decrease reference counters - needs to happen after the flushes */
2183
2173
pdom_detach_iommu(iommu, domain);
+1
-1
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
+1
-1
drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
···
339
339
* one CPU at a time can enter the process, while the others
340
340
* will be spinning at the same lock.
341
341
*/
342
-
lidx = smp_processor_id() % cmdqv->num_lvcmdqs_per_vintf;
342
+
lidx = raw_smp_processor_id() % cmdqv->num_lvcmdqs_per_vintf;
343
343
vcmdq = vintf->lvcmdqs[lidx];
344
344
if (!vcmdq || !READ_ONCE(vcmdq->enabled))
345
345
return NULL;
+27
-7
drivers/iommu/intel/cache.c
+27
-7
drivers/iommu/intel/cache.c
···
105
105
spin_unlock_irqrestore(&domain->cache_lock, flags);
106
106
}
107
107
108
+
/* domain->qi_batch will be freed in iommu_free_domain() path. */
109
+
static int domain_qi_batch_alloc(struct dmar_domain *domain)
110
+
{
111
+
unsigned long flags;
112
+
int ret = 0;
113
+
114
+
spin_lock_irqsave(&domain->cache_lock, flags);
115
+
if (domain->qi_batch)
116
+
goto out_unlock;
117
+
118
+
domain->qi_batch = kzalloc(sizeof(*domain->qi_batch), GFP_ATOMIC);
119
+
if (!domain->qi_batch)
120
+
ret = -ENOMEM;
121
+
out_unlock:
122
+
spin_unlock_irqrestore(&domain->cache_lock, flags);
123
+
124
+
return ret;
125
+
}
126
+
108
127
static int __cache_tag_assign_domain(struct dmar_domain *domain, u16 did,
109
128
struct device *dev, ioasid_t pasid)
110
129
{
111
130
struct device_domain_info *info = dev_iommu_priv_get(dev);
112
131
int ret;
132
+
133
+
ret = domain_qi_batch_alloc(domain);
134
+
if (ret)
135
+
return ret;
113
136
114
137
ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_IOTLB);
115
138
if (ret || !info->ats_enabled)
···
161
138
{
162
139
struct device_domain_info *info = dev_iommu_priv_get(dev);
163
140
int ret;
141
+
142
+
ret = domain_qi_batch_alloc(domain);
143
+
if (ret)
144
+
return ret;
164
145
165
146
ret = cache_tag_assign(domain, did, dev, pasid, CACHE_TAG_NESTING_IOTLB);
166
147
if (ret || !info->ats_enabled)
···
216
189
{
217
190
u16 did = domain_get_id_for_dev(domain, dev);
218
191
int ret;
219
-
220
-
/* domain->qi_bach will be freed in iommu_free_domain() path. */
221
-
if (!domain->qi_batch) {
222
-
domain->qi_batch = kzalloc(sizeof(*domain->qi_batch), GFP_KERNEL);
223
-
if (!domain->qi_batch)
224
-
return -ENOMEM;
225
-
}
226
192
227
193
ret = __cache_tag_assign_domain(domain, did, dev, pasid);
228
194
if (ret || domain->domain.type != IOMMU_DOMAIN_NESTED)
+3
-1
drivers/iommu/intel/iommu.c
+3
-1
drivers/iommu/intel/iommu.c
···
3220
3220
struct intel_iommu *iommu = info->iommu;
3221
3221
unsigned long flags;
3222
3222
3223
+
if (info->domain)
3224
+
cache_tag_unassign_domain(info->domain, dev, IOMMU_NO_PASID);
3225
+
3223
3226
iommu_disable_pci_caps(info);
3224
3227
if (!dev_is_real_dma_subdevice(dev)) {
3225
3228
if (sm_supported(iommu))
···
3239
3236
list_del(&info->link);
3240
3237
spin_unlock_irqrestore(&info->domain->lock, flags);
3241
3238
3242
-
cache_tag_unassign_domain(info->domain, dev, IOMMU_NO_PASID);
3243
3239
domain_detach_iommu(info->domain, iommu);
3244
3240
info->domain = NULL;
3245
3241
}
+2
-1
drivers/iommu/intel/pasid.c
+2
-1
drivers/iommu/intel/pasid.c