Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
arm64: dts: qcom: sm6115: Add GPU nodes
Introduce nodes for the A610 GPU and its GMU wrapper along with the
speedbin fuse entry in QFPROM.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230620-topic-gpu_tablet_disp-v2-1-0538ea1beb0b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Konrad Dybcio
and committed by
Bjorn Andersson
11750af2
8882ae07
+103
+103
arch/arm64/boot/dts/qcom/sm6115.dtsi
+103
arch/arm64/boot/dts/qcom/sm6115.dtsi
···
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reg = <0x25b 0x1>;
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bits = <1 4>;
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};
868
+
869
+
gpu_speed_bin: gpu-speed-bin@6006 {
870
+
reg = <0x6006 0x2>;
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+
bits = <5 8>;
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+
};
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};
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rng: rng@1b53000 {
···
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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};
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+
};
1318
+
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+
gpu: gpu@5900000 {
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+
compatible = "qcom,adreno-610.0", "qcom,adreno";
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+
reg = <0x0 0x05900000 0x0 0x40000>;
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+
reg-names = "kgsl_3d0_reg_memory";
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+
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+
/* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
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+
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
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+
<&gpucc GPU_CC_AHB_CLK>,
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+
<&gcc GCC_BIMC_GPU_AXI_CLK>,
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+
<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
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+
<&gpucc GPU_CC_CX_GMU_CLK>,
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+
<&gpucc GPU_CC_CXO_CLK>;
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+
clock-names = "core",
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+
"iface",
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+
"mem_iface",
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+
"alt_mem_iface",
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+
"gmu",
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+
"xo";
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+
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+
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
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+
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+
iommus = <&adreno_smmu 0 1>;
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+
operating-points-v2 = <&gpu_opp_table>;
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+
power-domains = <&rpmpd SM6115_VDDCX>;
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+
qcom,gmu = <&gmu_wrapper>;
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+
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+
nvmem-cells = <&gpu_speed_bin>;
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+
nvmem-cell-names = "speed_bin";
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+
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+
status = "disabled";
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+
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+
zap-shader {
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+
memory-region = <&pil_gpu_mem>;
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+
};
1353
+
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+
gpu_opp_table: opp-table {
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+
compatible = "operating-points-v2";
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+
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+
opp-320000000 {
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+
opp-hz = /bits/ 64 <320000000>;
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+
required-opps = <&rpmpd_opp_low_svs>;
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+
opp-supported-hw = <0x1f>;
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+
};
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+
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+
opp-465000000 {
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+
opp-hz = /bits/ 64 <465000000>;
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+
required-opps = <&rpmpd_opp_svs>;
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+
opp-supported-hw = <0x1f>;
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+
};
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+
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+
opp-600000000 {
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+
opp-hz = /bits/ 64 <600000000>;
1371
+
required-opps = <&rpmpd_opp_svs_plus>;
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+
opp-supported-hw = <0x1f>;
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+
};
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+
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+
opp-745000000 {
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+
opp-hz = /bits/ 64 <745000000>;
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+
required-opps = <&rpmpd_opp_nom>;
1378
+
opp-supported-hw = <0xf>;
1379
+
};
1380
+
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+
opp-820000000 {
1382
+
opp-hz = /bits/ 64 <820000000>;
1383
+
required-opps = <&rpmpd_opp_nom_plus>;
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+
opp-supported-hw = <0x7>;
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+
};
1386
+
1387
+
opp-900000000 {
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+
opp-hz = /bits/ 64 <900000000>;
1389
+
required-opps = <&rpmpd_opp_turbo>;
1390
+
opp-supported-hw = <0x7>;
1391
+
};
1392
+
1393
+
/* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
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+
opp-950000000 {
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+
opp-hz = /bits/ 64 <950000000>;
1396
+
required-opps = <&rpmpd_opp_turbo_plus>;
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+
opp-supported-hw = <0x4>;
1398
+
};
1399
+
1400
+
opp-980000000 {
1401
+
opp-hz = /bits/ 64 <980000000>;
1402
+
required-opps = <&rpmpd_opp_turbo_plus>;
1403
+
opp-supported-hw = <0x3>;
1404
+
};
1405
+
};
1406
+
};
1407
+
1408
+
gmu_wrapper: gmu@596a000 {
1409
+
compatible = "qcom,adreno-gmu-wrapper";
1410
+
reg = <0x0 0x0596a000 0x0 0x30000>;
1411
+
reg-names = "gmu";
1412
+
power-domains = <&gpucc GPU_CX_GDSC>,
1413
+
<&gpucc GPU_GX_GDSC>;
1414
+
power-domain-names = "cx", "gx";
1322
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};
1323
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1324
1417
gpucc: clock-controller@5990000 {