phy: qcom-qmp: qserdes-com-v4: add missing registers

+1 -1

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

··· 1085 1085 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1086 1086 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1087 1087 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1088 - QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03), 1088 + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1089 1089 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1090 1090 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1091 1091 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),

+46 -1

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v4.h

··· 7 7 #define QCOM_PHY_QMP_QSERDES_COM_V4_H_ 8 8 9 9 /* Only for QMP V4 PHY - QSERDES COM registers */ 10 + #define QSERDES_V4_COM_ATB_SEL1 0x000 11 + #define QSERDES_V4_COM_ATB_SEL2 0x004 12 + #define QSERDES_V4_COM_FREQ_UPDATE 0x008 10 13 #define QSERDES_V4_COM_BG_TIMER 0x00c 11 14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 12 15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 16 + #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018 13 17 #define QSERDES_V4_COM_SSC_PER1 0x01c 14 18 #define QSERDES_V4_COM_SSC_PER2 0x020 15 19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 16 20 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 21 + #define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0 0x02c 17 22 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 18 23 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 24 + #define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1 0x038 25 + #define QSERDES_V4_COM_POST_DIV 0x03c 26 + #define QSERDES_V4_COM_POST_DIV_MUX 0x040 19 27 #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 20 28 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 21 29 #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 22 30 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 31 + #define QSERDES_V4_COM_PLL_EN 0x054 23 32 #define QSERDES_V4_COM_PLL_IVCO 0x058 33 + #define QSERDES_V4_COM_CMN_IETRIM 0x05c 24 34 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 35 + #define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL 0x064 36 + #define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS 0x068 37 + #define QSERDES_V4_COM_CLK_EP_DIV_MODE0 0x06c 38 + #define QSERDES_V4_COM_CLK_EP_DIV_MODE1 0x070 25 39 #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 26 40 #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 27 41 #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 28 42 #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 29 43 #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 30 44 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 45 + #define QSERDES_V4_COM_PLL_CNTRL 0x08c 46 + #define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM 0x090 31 47 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 48 + #define QSERDES_V4_COM_CML_SYSCLK_SEL 0x098 32 49 #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 50 + #define QSERDES_V4_COM_RESETSM_CNTRL2 0x0a0 33 51 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 34 52 #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 35 53 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac ··· 55 37 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 56 38 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 57 39 #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 40 + #define QSERDES_V4_COM_DEC_START_MSB_MODE0 0x0c0 58 41 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 42 + #define QSERDES_V4_COM_DEC_START_MSB_MODE1 0x0c8 59 43 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 60 44 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 61 45 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 62 46 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 63 47 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 64 48 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 49 + #define QSERDES_V4_COM_INTEGLOOP_INITVAL 0x0e4 50 + #define QSERDES_V4_COM_INTEGLOOP_EN 0x0e8 65 51 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 66 52 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 67 53 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 68 54 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 55 + #define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc 56 + #define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1 0x100 57 + #define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL 0x104 69 58 #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 70 59 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 71 60 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 72 61 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 73 62 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 74 63 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 64 + #define QSERDES_V4_COM_VCO_TUNE_INITVAL1 0x120 75 65 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 66 + #define QSERDES_V4_COM_VCO_TUNE_MINVAL1 0x128 67 + #define QSERDES_V4_COM_VCO_TUNE_MINVAL2 0x12c 68 + #define QSERDES_V4_COM_VCO_TUNE_MAXVAL1 0x130 69 + #define QSERDES_V4_COM_VCO_TUNE_MAXVAL2 0x134 70 + #define QSERDES_V4_COM_VCO_TUNE_TIMER1 0x138 71 + #define QSERDES_V4_COM_VCO_TUNE_TIMER2 0x13c 76 72 #define QSERDES_V4_COM_CMN_STATUS 0x140 73 + #define QSERDES_V4_COM_RESET_SM_STATUS 0x144 74 + #define QSERDES_V4_COM_RESTRIM_CODE_STATUS 0x148 75 + #define QSERDES_V4_COM_PLLCAL_CODE1_STATUS 0x14c 76 + #define QSERDES_V4_COM_PLLCAL_CODE2_STATUS 0x150 77 77 #define QSERDES_V4_COM_CLK_SELECT 0x154 78 78 #define QSERDES_V4_COM_HSCLK_SEL 0x158 79 79 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 80 + #define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS 0x160 81 + #define QSERDES_V4_COM_PLL_ANALOG 0x164 80 82 #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 81 83 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 84 + #define QSERDES_V4_COM_SW_RESET 0x170 82 85 #define QSERDES_V4_COM_CORE_CLK_EN 0x174 83 86 #define QSERDES_V4_COM_C_READY_STATUS 0x178 84 87 #define QSERDES_V4_COM_CMN_CONFIG 0x17c 88 + #define QSERDES_V4_COM_CMN_RATE_OVERRIDE 0x180 85 89 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 90 + #define QSERDES_V4_COM_DEBUG_BUS0 0x188 91 + #define QSERDES_V4_COM_DEBUG_BUS1 0x18c 92 + #define QSERDES_V4_COM_DEBUG_BUS2 0x190 93 + #define QSERDES_V4_COM_DEBUG_BUS3 0x194 94 + #define QSERDES_V4_COM_DEBUG_BUS_SEL 0x198 86 95 #define QSERDES_V4_COM_CMN_MISC1 0x19c 87 - #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 96 + #define QSERDES_V4_COM_CMN_MISC2 0x1a0 88 97 #define QSERDES_V4_COM_CMN_MODE 0x1a4 89 98 #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 90 99 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac

+141

drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v4.h

··· 7 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_ 8 8 9 9 /* Only for QMP V4 PHY - TX registers */ 10 + #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000 11 + #define QSERDES_V4_TX_BIST_INVERT 0x004 10 12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008 11 13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c 14 + #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010 12 15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014 16 + #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018 13 17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c 14 18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020 15 19 #define QSERDES_V4_TX_TX_BAND 0x024 20 + #define QSERDES_V4_TX_SLEW_CNTL 0x028 16 21 #define QSERDES_V4_TX_INTERFACE_SELECT 0x02c 22 + #define QSERDES_V4_TX_LPB_EN 0x030 17 23 #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x034 18 24 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x038 19 25 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x03c 20 26 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x040 27 + #define QSERDES_V4_TX_PERL_LENGTH1 0x044 28 + #define QSERDES_V4_TX_PERL_LENGTH2 0x048 29 + #define QSERDES_V4_TX_SERDES_BYP_EN_OUT 0x04c 30 + #define QSERDES_V4_TX_DEBUG_BUS_SEL 0x050 21 31 #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x054 22 32 #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x058 23 33 #define QSERDES_V4_TX_TX_POL_INV 0x05c 24 34 #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 35 + #define QSERDES_V4_TX_BIST_PATTERN1 0x064 36 + #define QSERDES_V4_TX_BIST_PATTERN2 0x068 37 + #define QSERDES_V4_TX_BIST_PATTERN3 0x06c 38 + #define QSERDES_V4_TX_BIST_PATTERN4 0x070 39 + #define QSERDES_V4_TX_BIST_PATTERN5 0x074 40 + #define QSERDES_V4_TX_BIST_PATTERN6 0x078 41 + #define QSERDES_V4_TX_BIST_PATTERN7 0x07c 42 + #define QSERDES_V4_TX_BIST_PATTERN8 0x080 25 43 #define QSERDES_V4_TX_LANE_MODE_1 0x084 26 44 #define QSERDES_V4_TX_LANE_MODE_2 0x088 45 + #define QSERDES_V4_TX_LANE_MODE_3 0x08c 46 + #define QSERDES_V4_TX_ATB_SEL1 0x090 47 + #define QSERDES_V4_TX_ATB_SEL2 0x094 48 + #define QSERDES_V4_TX_RCV_DETECT_LVL 0x098 27 49 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x09c 50 + #define QSERDES_V4_TX_PRBS_SEED1 0x0a0 51 + #define QSERDES_V4_TX_PRBS_SEED2 0x0a4 52 + #define QSERDES_V4_TX_PRBS_SEED3 0x0a8 53 + #define QSERDES_V4_TX_PRBS_SEED4 0x0ac 54 + #define QSERDES_V4_TX_RESET_GEN 0x0b0 55 + #define QSERDES_V4_TX_RESET_GEN_MUXES 0x0b4 28 56 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0x0b8 29 57 #define QSERDES_V4_TX_TX_INTERFACE_MODE 0x0bc 58 + #define QSERDES_V4_TX_PWM_CTRL 0x0c0 59 + #define QSERDES_V4_TX_PWM_ENCODED_OR_DATA 0x0c4 60 + #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2 0x0c8 61 + #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2 0x0cc 62 + #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2 0x0d0 63 + #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2 0x0d4 30 64 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x0d8 31 65 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x0dc 32 66 #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x0e0 33 67 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x0e4 34 68 #define QSERDES_V4_TX_VMODE_CTRL1 0x0e8 69 + #define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1 0x0ec 70 + #define QSERDES_V4_TX_BIST_STATUS 0x0f0 71 + #define QSERDES_V4_TX_BIST_ERROR_COUNT1 0x0f4 72 + #define QSERDES_V4_TX_BIST_ERROR_COUNT2 0x0f8 73 + #define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1 0x0fc 74 + #define QSERDES_V4_TX_LANE_DIG_CONFIG 0x100 35 75 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 76 + #define QSERDES_V4_TX_PRE_EMPH 0x108 77 + #define QSERDES_V4_TX_SW_RESET 0x10c 78 + #define QSERDES_V4_TX_DCC_OFFSET 0x110 79 + #define QSERDES_V4_TX_DIG_BKUP_CTRL 0x114 80 + #define QSERDES_V4_TX_DEBUG_BUS0 0x118 81 + #define QSERDES_V4_TX_DEBUG_BUS1 0x11c 82 + #define QSERDES_V4_TX_DEBUG_BUS2 0x120 83 + #define QSERDES_V4_TX_DEBUG_BUS3 0x124 84 + #define QSERDES_V4_TX_READ_EQCODE 0x128 85 + #define QSERDES_V4_TX_READ_OFFSETCODE 0x12c 86 + #define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW 0x130 87 + #define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH 0x134 88 + #define QSERDES_V4_TX_VGA_READ_CODE 0x138 89 + #define QSERDES_V4_TX_VTH_READ_CODE 0x13c 90 + #define QSERDES_V4_TX_DFE_TAP1_READ_CODE 0x140 91 + #define QSERDES_V4_TX_DFE_TAP2_READ_CODE 0x144 92 + #define QSERDES_V4_TX_IDAC_STATUS_I 0x148 93 + #define QSERDES_V4_TX_IDAC_STATUS_IBAR 0x14c 94 + #define QSERDES_V4_TX_IDAC_STATUS_Q 0x150 95 + #define QSERDES_V4_TX_IDAC_STATUS_QBAR 0x154 96 + #define QSERDES_V4_TX_IDAC_STATUS_A 0x158 97 + #define QSERDES_V4_TX_IDAC_STATUS_ABAR 0x15c 98 + #define QSERDES_V4_TX_IDAC_STATUS_SM_ON 0x160 99 + #define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE 0x164 100 + #define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR 0x168 101 + #define QSERDES_V4_TX_DCC_CAL_STATUS 0x16c 36 102 37 103 /* Only for QMP V4 PHY - RX registers */ 104 + #define QSERDES_V4_RX_UCDR_FO_GAIN_HALF 0x000 105 + #define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER 0x004 38 106 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 107 + #define QSERDES_V4_RX_UCDR_SO_GAIN_HALF 0x00c 108 + #define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER 0x010 39 109 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 110 + #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF 0x018 111 + #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c 112 + #define QSERDES_V4_RX_UCDR_SVS_FO_GAIN 0x020 113 + #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF 0x024 114 + #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 115 + #define QSERDES_V4_RX_UCDR_SVS_SO_GAIN 0x02c 40 116 #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 41 117 #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 118 + #define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY 0x038 42 119 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 43 120 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 44 121 #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 ··· 124 47 #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 125 48 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 126 49 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 50 + #define QSERDES_V4_RX_AUX_CONTROL 0x05c 127 51 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 128 52 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 129 53 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 54 + #define QSERDES_V4_RX_AC_JTAG_INITP 0x06c 55 + #define QSERDES_V4_RX_AC_JTAG_INITN 0x070 56 + #define QSERDES_V4_RX_AC_JTAG_LVL 0x074 130 57 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 58 + #define QSERDES_V4_RX_AC_JTAG_RESET 0x07c 131 59 #define QSERDES_V4_RX_RX_TERM_BW 0x080 60 + #define QSERDES_V4_RX_RX_RCVR_IQ_EN 0x084 61 + #define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS 0x088 62 + #define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c 63 + #define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS 0x090 64 + #define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 65 + #define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS 0x098 66 + #define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c 67 + #define QSERDES_V4_RX_RX_IDAC_EN 0x0a0 68 + #define QSERDES_V4_RX_RX_IDAC_ENABLES 0x0a4 69 + #define QSERDES_V4_RX_RX_IDAC_SIGN 0x0a8 70 + #define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE 0x0ac 71 + #define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 72 + #define QSERDES_V4_RX_DFE_1 0x0b4 73 + #define QSERDES_V4_RX_DFE_2 0x0b8 74 + #define QSERDES_V4_RX_DFE_3 0x0bc 75 + #define QSERDES_V4_RX_DFE_4 0x0c0 76 + #define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1 0x0c4 77 + #define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2 0x0c8 78 + #define QSERDES_V4_RX_TX_ADAPT_POST_THRESH 0x0cc 79 + #define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH 0x0d0 132 80 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 133 81 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 134 82 #define QSERDES_V4_RX_GM_CAL 0x0dc 83 + #define QSERDES_V4_RX_RX_VGA_GAIN2_LSB 0x0e0 84 + #define QSERDES_V4_RX_RX_VGA_GAIN2_MSB 0x0e4 135 85 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 136 86 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 137 87 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 ··· 166 62 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 167 63 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 168 64 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 65 + #define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR 0x104 66 + #define QSERDES_V4_RX_RX_EQ_OFFSET_LSB 0x108 67 + #define QSERDES_V4_RX_RX_EQ_OFFSET_MSB 0x10c 169 68 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 170 69 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 171 70 #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 ··· 176 69 #define QSERDES_V4_RX_SIGDET_LVL 0x120 177 70 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 178 71 #define QSERDES_V4_RX_RX_BAND 0x128 72 + #define QSERDES_V4_RX_CDR_FREEZE_UP_DN 0x12c 73 + #define QSERDES_V4_RX_CDR_RESET_OVERRIDE 0x130 74 + #define QSERDES_V4_RX_RX_INTERFACE_MODE 0x134 75 + #define QSERDES_V4_RX_JITTER_GEN_MODE 0x138 76 + #define QSERDES_V4_RX_SJ_AMP1 0x13c 77 + #define QSERDES_V4_RX_SJ_AMP2 0x140 78 + #define QSERDES_V4_RX_SJ_PER1 0x144 79 + #define QSERDES_V4_RX_SJ_PER2 0x148 80 + #define QSERDES_V4_RX_PPM_OFFSET1 0x14c 81 + #define QSERDES_V4_RX_PPM_OFFSET2 0x150 82 + #define QSERDES_V4_RX_SIGN_PPM_PERIOD1 0x154 83 + #define QSERDES_V4_RX_SIGN_PPM_PERIOD2 0x158 84 + #define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA 0x15c 85 + #define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x160 86 + #define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x164 87 + #define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x168 88 + #define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x16c 179 89 #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 180 90 #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 181 91 #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 ··· 208 84 #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 209 85 #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 210 86 #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 87 + #define QSERDES_V4_RX_PHPRE_CTRL 0x1ac 88 + #define QSERDES_V4_RX_PHPRE_INITVAL 0x1b0 211 89 #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 212 90 #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 213 91 #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 92 + #define QSERDES_V4_RX_DCC_CTRL2 0x1c0 214 93 #define QSERDES_V4_RX_VTH_CODE 0x1c4 94 + #define QSERDES_V4_RX_VTH_MIN_THRESH 0x1c8 95 + #define QSERDES_V4_RX_VTH_MAX_THRESH 0x1cc 96 + #define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1 0x1d0 97 + #define QSERDES_V4_RX_PI_CTRL1 0x1d4 98 + #define QSERDES_V4_RX_PI_CTRL2 0x1d8 99 + #define QSERDES_V4_RX_PI_QUAD 0x1dc 100 + #define QSERDES_V4_RX_IDATA1 0x1e0 101 + #define QSERDES_V4_RX_IDATA2 0x1e4 102 + #define QSERDES_V4_RX_AUX_DATA1 0x1e8 103 + #define QSERDES_V4_RX_AUX_DATA2 0x1ec 104 + #define QSERDES_V4_RX_AC_JTAG_OUTP 0x1f0 105 + #define QSERDES_V4_RX_AC_JTAG_OUTN 0x1f4 106 + #define QSERDES_V4_RX_RX_SIGDET 0x1f8 107 + #define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1 0x1fc 215 108 216 109 #endif

Configure Feed

Configure Feed