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drm/xe/xe3: Generate and store the L3 bank mask

On Xe3, the register used to indicate which L3 banks are enabled on
the system is a new one called MIRROR_L3BANK_ENABLE. Each bit
represents one bank enabled in each node.
Extend the existing topology code for Xe3 to read this register and
generate the correct L3 bank mask, which can be read by user space
throug the topology query.

Bspec: 72573, 73439
Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250114203853.35055-1-matthew.s.atwood@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

authored by

Francois Dugast and committed by
Matt Roper 11a64adc 50554bf3

+16 -3
+3
drivers/gpu/drm/xe/regs/xe_gt_regs.h
··· 221 221 222 222 #define MIRROR_FUSE1 XE_REG(0x911c) 223 223 224 + #define MIRROR_L3BANK_ENABLE XE_REG(0x9130) 225 + #define XE3_L3BANK_ENABLE REG_GENMASK(31, 0) 226 + 224 227 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 225 228 #define XELP_EU_MASK REG_GENMASK(7, 0) 226 229 #define XELP_GT_SLICE_ENABLE XE_REG(0x9138)
+13 -3
drivers/gpu/drm/xe/xe_gt_topology.c
··· 129 129 load_l3_bank_mask(struct xe_gt *gt, xe_l3_bank_mask_t l3_bank_mask) 130 130 { 131 131 struct xe_device *xe = gt_to_xe(gt); 132 - u32 fuse3 = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); 132 + struct xe_mmio *mmio = &gt->mmio; 133 + u32 fuse3 = xe_mmio_read32(mmio, MIRROR_FUSE3); 133 134 134 135 /* 135 136 * PTL platforms with media version 30.00 do not provide proper values ··· 144 143 if (XE_WA(gt, no_media_l3)) 145 144 return; 146 145 147 - if (GRAPHICS_VER(xe) >= 20) { 146 + if (GRAPHICS_VER(xe) >= 30) { 147 + xe_l3_bank_mask_t per_node = {}; 148 + u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); 149 + u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE); 150 + u32 bank_val = REG_FIELD_GET(XE3_L3BANK_ENABLE, mirror_l3bank_enable); 151 + 152 + bitmap_from_arr32(per_node, &bank_val, 32); 153 + gen_l3_mask_from_pattern(xe, l3_bank_mask, per_node, 32, 154 + meml3_en); 155 + } else if (GRAPHICS_VER(xe) >= 20) { 148 156 xe_l3_bank_mask_t per_node = {}; 149 157 u32 meml3_en = REG_FIELD_GET(XE2_NODE_ENABLE_MASK, fuse3); 150 158 u32 bank_val = REG_FIELD_GET(XE2_GT_L3_MODE_MASK, fuse3); ··· 165 155 xe_l3_bank_mask_t per_node = {}; 166 156 xe_l3_bank_mask_t per_mask_bit = {}; 167 157 u32 meml3_en = REG_FIELD_GET(MEML3_EN_MASK, fuse3); 168 - u32 fuse4 = xe_mmio_read32(&gt->mmio, XEHP_FUSE4); 158 + u32 fuse4 = xe_mmio_read32(mmio, XEHP_FUSE4); 169 159 u32 bank_val = REG_FIELD_GET(GT_L3_EXC_MASK, fuse4); 170 160 171 161 bitmap_set_value8(per_mask_bit, 0x3, 0);