Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull kvm fixes from Paolo Bonzini:
"ARM:
- Correctly handle 'invariant' system registers for protected VMs
- Improved handling of VNCR data aborts, including external aborts
- Fixes for handling of FEAT_RAS for NV guests, providing a sane
fault context during SEA injection and preventing the use of
RASv1p1 fault injection hardware
- Ensure that page table destruction when a VM is destroyed gives an
opportunity to reschedule
- Large fix to KVM's infrastructure for managing guest context loaded
on the CPU, addressing issues where the output of AT emulation
doesn't get reflected to the guest
- Fix AT S12 emulation to actually perform stage-2 translation when
necessary
- Avoid attempting vLPI irqbypass when GICv4 has been explicitly
disabled for a VM
- Minor KVM + selftest fixes
RISC-V:
- Fix pte settings within kvm_riscv_gstage_ioremap()
- Fix comments in kvm_riscv_check_vcpu_requests()
- Fix stack overrun when setting vlenb via ONE_REG
x86:
- Use array_index_nospec() to sanitize the target vCPU ID when
handling PV IPIs and yields as the ID is guest-controlled.
- Drop a superfluous cpumask_empty() check when reclaiming SEV
memory, as the common case, by far, is that at least one CPU will
have entered the VM, and wbnoinvd_on_cpus_mask() will naturally
handle the rare case where the set of have_run_cpus is empty.
Selftests (not KVM):
- Rename the is_signed_type() macro in kselftest_harness.h to
is_signed_var() to fix a collision with linux/overflow.h. The
collision generates compiler warnings due to the two macros having
different meaning"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (29 commits)
KVM: arm64: nv: Fix ATS12 handling of single-stage translation
KVM: arm64: Remove __vcpu_{read,write}_sys_reg_{from,to}_cpu()
KVM: arm64: Fix vcpu_{read,write}_sys_reg() accessors
KVM: arm64: Simplify sysreg access on exception delivery
KVM: arm64: Check for SYSREGS_ON_CPU before accessing the 32bit state
RISC-V: KVM: fix stack overrun when loading vlenb
RISC-V: KVM: Correct kvm_riscv_check_vcpu_requests() comment
RISC-V: KVM: Fix pte settings within kvm_riscv_gstage_ioremap()
KVM: arm64: selftests: Sync ID_AA64MMFR3_EL1 in set_id_regs
KVM: arm64: Get rid of ARM64_FEATURE_MASK()
KVM: arm64: Make ID_AA64PFR1_EL1.RAS_frac writable
KVM: arm64: Make ID_AA64PFR0_EL1.RAS writable
KVM: arm64: Ignore HCR_EL2.FIEN set by L1 guest's EL2
KVM: arm64: Handle RASv1p1 registers
arm64: Add capability denoting FEAT_RASv1p1
KVM: arm64: Reschedule as needed when destroying the stage-2 page-tables
KVM: arm64: Split kvm_pgtable_stage2_destroy()
selftests: harness: Rename is_signed_type() to avoid collision with overflow.h
KVM: SEV: don't check have_run_cpus in sev_writeback_caches()
KVM: arm64: Correctly populate FAR_EL2 on nested SEA injection
...
+585
-368
+2
-109
arch/arm64/include/asm/kvm_host.h
+2
-109
arch/arm64/include/asm/kvm_host.h
···
1160
1160
__v; \
1161
1161
})
1162
1162
1163
-
u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
1164
-
void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
1165
-
1166
-
static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
1167
-
{
1168
-
/*
1169
-
* *** VHE ONLY ***
1170
-
*
1171
-
* System registers listed in the switch are not saved on every
1172
-
* exit from the guest but are only saved on vcpu_put.
1173
-
*
1174
-
* SYSREGS_ON_CPU *MUST* be checked before using this helper.
1175
-
*
1176
-
* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1177
-
* should never be listed below, because the guest cannot modify its
1178
-
* own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1179
-
* thread when emulating cross-VCPU communication.
1180
-
*/
1181
-
if (!has_vhe())
1182
-
return false;
1183
-
1184
-
switch (reg) {
1185
-
case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break;
1186
-
case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break;
1187
-
case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break;
1188
-
case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break;
1189
-
case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break;
1190
-
case TCR2_EL1: *val = read_sysreg_s(SYS_TCR2_EL12); break;
1191
-
case PIR_EL1: *val = read_sysreg_s(SYS_PIR_EL12); break;
1192
-
case PIRE0_EL1: *val = read_sysreg_s(SYS_PIRE0_EL12); break;
1193
-
case POR_EL1: *val = read_sysreg_s(SYS_POR_EL12); break;
1194
-
case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break;
1195
-
case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break;
1196
-
case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break;
1197
-
case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break;
1198
-
case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break;
1199
-
case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break;
1200
-
case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
1201
-
case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break;
1202
-
case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
1203
-
case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break;
1204
-
case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break;
1205
-
case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
1206
-
case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break;
1207
-
case SPSR_EL1: *val = read_sysreg_s(SYS_SPSR_EL12); break;
1208
-
case PAR_EL1: *val = read_sysreg_par(); break;
1209
-
case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break;
1210
-
case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break;
1211
-
case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
1212
-
case ZCR_EL1: *val = read_sysreg_s(SYS_ZCR_EL12); break;
1213
-
case SCTLR2_EL1: *val = read_sysreg_s(SYS_SCTLR2_EL12); break;
1214
-
default: return false;
1215
-
}
1216
-
1217
-
return true;
1218
-
}
1219
-
1220
-
static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
1221
-
{
1222
-
/*
1223
-
* *** VHE ONLY ***
1224
-
*
1225
-
* System registers listed in the switch are not restored on every
1226
-
* entry to the guest but are only restored on vcpu_load.
1227
-
*
1228
-
* SYSREGS_ON_CPU *MUST* be checked before using this helper.
1229
-
*
1230
-
* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1231
-
* should never be listed below, because the MPIDR should only be set
1232
-
* once, before running the VCPU, and never changed later.
1233
-
*/
1234
-
if (!has_vhe())
1235
-
return false;
1236
-
1237
-
switch (reg) {
1238
-
case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
1239
-
case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
1240
-
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
1241
-
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
1242
-
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
1243
-
case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
1244
-
case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
1245
-
case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
1246
-
case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
1247
-
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
1248
-
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
1249
-
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
1250
-
case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
1251
-
case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
1252
-
case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
1253
-
case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
1254
-
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
1255
-
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
1256
-
case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
1257
-
case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
1258
-
case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
1259
-
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
1260
-
case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
1261
-
case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
1262
-
case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
1263
-
case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
1264
-
case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
1265
-
case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
1266
-
case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
1267
-
default: return false;
1268
-
}
1269
-
1270
-
return true;
1271
-
}
1163
+
u64 vcpu_read_sys_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
1164
+
void vcpu_write_sys_reg(struct kvm_vcpu *, u64, enum vcpu_sysreg);
1272
1165
1273
1166
struct kvm_vm_stat {
1274
1167
struct kvm_vm_stat_generic generic;
+1
arch/arm64/include/asm/kvm_mmu.h
+1
arch/arm64/include/asm/kvm_mmu.h
···
180
180
int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
181
181
phys_addr_t pa, unsigned long size, bool writable);
182
182
183
+
int kvm_handle_guest_sea(struct kvm_vcpu *vcpu);
183
184
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu);
184
185
185
186
phys_addr_t kvm_mmu_get_httbr(void);
+30
arch/arm64/include/asm/kvm_pgtable.h
+30
arch/arm64/include/asm/kvm_pgtable.h
···
355
355
return pteref;
356
356
}
357
357
358
+
static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref)
359
+
{
360
+
return pteref;
361
+
}
362
+
358
363
static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker)
359
364
{
360
365
/*
···
387
382
kvm_pteref_t pteref)
388
383
{
389
384
return rcu_dereference_check(pteref, !(walker->flags & KVM_PGTABLE_WALK_SHARED));
385
+
}
386
+
387
+
static inline kvm_pte_t *kvm_dereference_pteref_raw(kvm_pteref_t pteref)
388
+
{
389
+
return rcu_dereference_raw(pteref);
390
390
}
391
391
392
392
static inline int kvm_pgtable_walk_begin(struct kvm_pgtable_walker *walker)
···
560
550
* to freeing and therefore no TLB invalidation is performed.
561
551
*/
562
552
void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);
553
+
554
+
/**
555
+
* kvm_pgtable_stage2_destroy_range() - Destroy the unlinked range of addresses.
556
+
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
557
+
* @addr: Intermediate physical address at which to place the mapping.
558
+
* @size: Size of the mapping.
559
+
*
560
+
* The page-table is assumed to be unreachable by any hardware walkers prior
561
+
* to freeing and therefore no TLB invalidation is performed.
562
+
*/
563
+
void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,
564
+
u64 addr, u64 size);
565
+
566
+
/**
567
+
* kvm_pgtable_stage2_destroy_pgd() - Destroy the PGD of guest stage-2 page-table.
568
+
* @pgt: Page-table structure initialised by kvm_pgtable_stage2_init*().
569
+
*
570
+
* It is assumed that the rest of the page-table is freed before this operation.
571
+
*/
572
+
void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt);
563
573
564
574
/**
565
575
* kvm_pgtable_stage2_free_unlinked() - Free an unlinked stage-2 paging structure.
+3
-1
arch/arm64/include/asm/kvm_pkvm.h
+3
-1
arch/arm64/include/asm/kvm_pkvm.h
···
179
179
180
180
int pkvm_pgtable_stage2_init(struct kvm_pgtable *pgt, struct kvm_s2_mmu *mmu,
181
181
struct kvm_pgtable_mm_ops *mm_ops);
182
-
void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt);
182
+
void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,
183
+
u64 addr, u64 size);
184
+
void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt);
183
185
int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size, u64 phys,
184
186
enum kvm_pgtable_prot prot, void *mc,
185
187
enum kvm_pgtable_walk_flags flags);
-25
arch/arm64/include/asm/kvm_ras.h
-25
arch/arm64/include/asm/kvm_ras.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 */
2
-
/* Copyright (C) 2018 - Arm Ltd */
3
-
4
-
#ifndef __ARM64_KVM_RAS_H__
5
-
#define __ARM64_KVM_RAS_H__
6
-
7
-
#include <linux/acpi.h>
8
-
#include <linux/errno.h>
9
-
#include <linux/types.h>
10
-
11
-
#include <asm/acpi.h>
12
-
13
-
/*
14
-
* Was this synchronous external abort a RAS notification?
15
-
* Returns '0' for errors handled by some RAS subsystem, or -ENOENT.
16
-
*/
17
-
static inline int kvm_handle_guest_sea(void)
18
-
{
19
-
/* apei_claim_sea(NULL) expects to mask interrupts itself */
20
-
lockdep_assert_irqs_enabled();
21
-
22
-
return apei_claim_sea(NULL);
23
-
}
24
-
25
-
#endif /* __ARM64_KVM_RAS_H__ */
-3
arch/arm64/include/asm/sysreg.h
-3
arch/arm64/include/asm/sysreg.h
+24
arch/arm64/kernel/cpufeature.c
+24
arch/arm64/kernel/cpufeature.c
···
2269
2269
/* Firmware may have left a deferred SError in this register. */
2270
2270
write_sysreg_s(0, SYS_DISR_EL1);
2271
2271
}
2272
+
static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope)
2273
+
{
2274
+
const struct arm64_cpu_capabilities rasv1p1_caps[] = {
2275
+
{
2276
+
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1)
2277
+
},
2278
+
{
2279
+
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2280
+
},
2281
+
{
2282
+
ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1)
2283
+
},
2284
+
};
2285
+
2286
+
return (has_cpuid_feature(&rasv1p1_caps[0], scope) ||
2287
+
(has_cpuid_feature(&rasv1p1_caps[1], scope) &&
2288
+
has_cpuid_feature(&rasv1p1_caps[2], scope)));
2289
+
}
2272
2290
#endif /* CONFIG_ARM64_RAS_EXTN */
2273
2291
2274
2292
#ifdef CONFIG_ARM64_PTR_AUTH
···
2704
2686
.matches = has_cpuid_feature,
2705
2687
.cpu_enable = cpu_clear_disr,
2706
2688
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP)
2689
+
},
2690
+
{
2691
+
.desc = "RASv1p1 Extension Support",
2692
+
.capability = ARM64_HAS_RASV1P1_EXTN,
2693
+
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
2694
+
.matches = has_rasv1p1,
2707
2695
},
2708
2696
#endif /* CONFIG_ARM64_RAS_EXTN */
2709
2697
#ifdef CONFIG_ARM64_AMU_EXTN
+4
-4
arch/arm64/kvm/arm.c
+4
-4
arch/arm64/kvm/arm.c
···
2408
2408
*/
2409
2409
u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2410
2410
2411
-
val &= ~(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2) |
2412
-
ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3));
2411
+
val &= ~(ID_AA64PFR0_EL1_CSV2 |
2412
+
ID_AA64PFR0_EL1_CSV3);
2413
2413
2414
-
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV2),
2414
+
val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV2,
2415
2415
arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED);
2416
-
val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_CSV3),
2416
+
val |= FIELD_PREP(ID_AA64PFR0_EL1_CSV3,
2417
2417
arm64_get_meltdown_state() == SPECTRE_UNAFFECTED);
2418
2418
2419
2419
return val;
+3
-3
arch/arm64/kvm/at.c
+3
-3
arch/arm64/kvm/at.c
···
1420
1420
return;
1421
1421
1422
1422
/*
1423
-
* If we only have a single stage of translation (E2H=0 or
1424
-
* TGE=1), exit early. Same thing if {VM,DC}=={0,0}.
1423
+
* If we only have a single stage of translation (EL2&0), exit
1424
+
* early. Same thing if {VM,DC}=={0,0}.
1425
1425
*/
1426
-
if (!vcpu_el2_e2h_is_set(vcpu) || vcpu_el2_tge_is_set(vcpu) ||
1426
+
if (compute_translation_regime(vcpu, op) == TR_EL20 ||
1427
1427
!(vcpu_read_sys_reg(vcpu, HCR_EL2) & (HCR_VM | HCR_DC)))
1428
1428
return;
1429
1429
+1
-1
arch/arm64/kvm/emulate-nested.c
+1
-1
arch/arm64/kvm/emulate-nested.c
···
2833
2833
iabt ? ESR_ELx_EC_IABT_LOW : ESR_ELx_EC_DABT_LOW);
2834
2834
esr |= ESR_ELx_FSC_EXTABT | ESR_ELx_IL;
2835
2835
2836
-
vcpu_write_sys_reg(vcpu, FAR_EL2, addr);
2836
+
vcpu_write_sys_reg(vcpu, addr, FAR_EL2);
2837
2837
2838
2838
if (__vcpu_sys_reg(vcpu, SCTLR2_EL2) & SCTLR2_EL1_EASE)
2839
2839
return kvm_inject_nested(vcpu, esr, except_type_serror);
+6
-14
arch/arm64/kvm/hyp/exception.c
+6
-14
arch/arm64/kvm/hyp/exception.c
···
22
22
23
23
static inline u64 __vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
24
24
{
25
-
u64 val;
26
-
27
-
if (unlikely(vcpu_has_nv(vcpu)))
25
+
if (has_vhe())
28
26
return vcpu_read_sys_reg(vcpu, reg);
29
-
else if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
30
-
__vcpu_read_sys_reg_from_cpu(reg, &val))
31
-
return val;
32
27
33
28
return __vcpu_sys_reg(vcpu, reg);
34
29
}
35
30
36
31
static inline void __vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
37
32
{
38
-
if (unlikely(vcpu_has_nv(vcpu)))
33
+
if (has_vhe())
39
34
vcpu_write_sys_reg(vcpu, val, reg);
40
-
else if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU) ||
41
-
!__vcpu_write_sys_reg_to_cpu(val, reg))
35
+
else
42
36
__vcpu_assign_sys_reg(vcpu, reg, val);
43
37
}
44
38
45
39
static void __vcpu_write_spsr(struct kvm_vcpu *vcpu, unsigned long target_mode,
46
40
u64 val)
47
41
{
48
-
if (unlikely(vcpu_has_nv(vcpu))) {
42
+
if (has_vhe()) {
49
43
if (target_mode == PSR_MODE_EL1h)
50
44
vcpu_write_sys_reg(vcpu, val, SPSR_EL1);
51
45
else
52
46
vcpu_write_sys_reg(vcpu, val, SPSR_EL2);
53
-
} else if (has_vhe()) {
54
-
write_sysreg_el1(val, SYS_SPSR);
55
47
} else {
56
48
__vcpu_assign_sys_reg(vcpu, SPSR_EL1, val);
57
49
}
···
51
59
52
60
static void __vcpu_write_spsr_abt(struct kvm_vcpu *vcpu, u64 val)
53
61
{
54
-
if (has_vhe())
62
+
if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
55
63
write_sysreg(val, spsr_abt);
56
64
else
57
65
vcpu->arch.ctxt.spsr_abt = val;
···
59
67
60
68
static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu, u64 val)
61
69
{
62
-
if (has_vhe())
70
+
if (has_vhe() && vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
63
71
write_sysreg(val, spsr_und);
64
72
else
65
73
vcpu->arch.ctxt.spsr_und = val;
+1
-1
arch/arm64/kvm/hyp/nvhe/list_debug.c
+1
-1
arch/arm64/kvm/hyp/nvhe/list_debug.c
+5
arch/arm64/kvm/hyp/nvhe/sys_regs.c
+5
arch/arm64/kvm/hyp/nvhe/sys_regs.c
···
253
253
254
254
*vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
255
255
*vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR);
256
+
__vcpu_assign_sys_reg(vcpu, read_sysreg_el1(SYS_VBAR), VBAR_EL1);
256
257
257
258
kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
258
259
···
373
372
374
373
/* Debug and Trace Registers are restricted. */
375
374
375
+
/* Group 1 ID registers */
376
+
HOST_HANDLED(SYS_REVIDR_EL1),
377
+
376
378
/* AArch64 mappings of the AArch32 ID registers */
377
379
/* CRm=1 */
378
380
AARCH32(SYS_ID_PFR0_EL1),
···
464
460
465
461
HOST_HANDLED(SYS_CCSIDR_EL1),
466
462
HOST_HANDLED(SYS_CLIDR_EL1),
463
+
HOST_HANDLED(SYS_AIDR_EL1),
467
464
HOST_HANDLED(SYS_CSSELR_EL1),
468
465
HOST_HANDLED(SYS_CTR_EL0),
469
466
+21
-4
arch/arm64/kvm/hyp/pgtable.c
+21
-4
arch/arm64/kvm/hyp/pgtable.c
···
1551
1551
return 0;
1552
1552
}
1553
1553
1554
-
void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt)
1554
+
void kvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,
1555
+
u64 addr, u64 size)
1555
1556
{
1556
-
size_t pgd_sz;
1557
1557
struct kvm_pgtable_walker walker = {
1558
1558
.cb = stage2_free_walker,
1559
1559
.flags = KVM_PGTABLE_WALK_LEAF |
1560
1560
KVM_PGTABLE_WALK_TABLE_POST,
1561
1561
};
1562
1562
1563
-
WARN_ON(kvm_pgtable_walk(pgt, 0, BIT(pgt->ia_bits), &walker));
1563
+
WARN_ON(kvm_pgtable_walk(pgt, addr, size, &walker));
1564
+
}
1565
+
1566
+
void kvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt)
1567
+
{
1568
+
size_t pgd_sz;
1569
+
1564
1570
pgd_sz = kvm_pgd_pages(pgt->ia_bits, pgt->start_level) * PAGE_SIZE;
1565
-
pgt->mm_ops->free_pages_exact(kvm_dereference_pteref(&walker, pgt->pgd), pgd_sz);
1571
+
1572
+
/*
1573
+
* Since the pgtable is unlinked at this point, and not shared with
1574
+
* other walkers, safely deference pgd with kvm_dereference_pteref_raw()
1575
+
*/
1576
+
pgt->mm_ops->free_pages_exact(kvm_dereference_pteref_raw(pgt->pgd), pgd_sz);
1566
1577
pgt->pgd = NULL;
1578
+
}
1579
+
1580
+
void kvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt)
1581
+
{
1582
+
kvm_pgtable_stage2_destroy_range(pgt, 0, BIT(pgt->ia_bits));
1583
+
kvm_pgtable_stage2_destroy_pgd(pgt);
1567
1584
}
1568
1585
1569
1586
void kvm_pgtable_stage2_free_unlinked(struct kvm_pgtable_mm_ops *mm_ops, void *pgtable, s8 level)
+1
-1
arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
+1
-1
arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c
+4
-1
arch/arm64/kvm/hyp/vhe/switch.c
+4
-1
arch/arm64/kvm/hyp/vhe/switch.c
···
43
43
*
44
44
* - API/APK: they are already accounted for by vcpu_load(), and can
45
45
* only take effect across a load/put cycle (such as ERET)
46
+
*
47
+
* - FIEN: no way we let a guest have access to the RAS "Common Fault
48
+
* Injection" thing, whatever that does
46
49
*/
47
-
#define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK)
50
+
#define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK | HCR_FIEN)
48
51
49
52
static u64 __compute_hcr(struct kvm_vcpu *vcpu)
50
53
{
+51
-14
arch/arm64/kvm/mmu.c
+51
-14
arch/arm64/kvm/mmu.c
···
4
4
* Author: Christoffer Dall <c.dall@virtualopensystems.com>
5
5
*/
6
6
7
+
#include <linux/acpi.h>
7
8
#include <linux/mman.h>
8
9
#include <linux/kvm_host.h>
9
10
#include <linux/io.h>
10
11
#include <linux/hugetlb.h>
11
12
#include <linux/sched/signal.h>
12
13
#include <trace/events/kvm.h>
14
+
#include <asm/acpi.h>
13
15
#include <asm/pgalloc.h>
14
16
#include <asm/cacheflush.h>
15
17
#include <asm/kvm_arm.h>
16
18
#include <asm/kvm_mmu.h>
17
19
#include <asm/kvm_pgtable.h>
18
20
#include <asm/kvm_pkvm.h>
19
-
#include <asm/kvm_ras.h>
20
21
#include <asm/kvm_asm.h>
21
22
#include <asm/kvm_emulate.h>
22
23
#include <asm/virt.h>
···
904
903
return 0;
905
904
}
906
905
906
+
/*
907
+
* Assume that @pgt is valid and unlinked from the KVM MMU to free the
908
+
* page-table without taking the kvm_mmu_lock and without performing any
909
+
* TLB invalidations.
910
+
*
911
+
* Also, the range of addresses can be large enough to cause need_resched
912
+
* warnings, for instance on CONFIG_PREEMPT_NONE kernels. Hence, invoke
913
+
* cond_resched() periodically to prevent hogging the CPU for a long time
914
+
* and schedule something else, if required.
915
+
*/
916
+
static void stage2_destroy_range(struct kvm_pgtable *pgt, phys_addr_t addr,
917
+
phys_addr_t end)
918
+
{
919
+
u64 next;
920
+
921
+
do {
922
+
next = stage2_range_addr_end(addr, end);
923
+
KVM_PGT_FN(kvm_pgtable_stage2_destroy_range)(pgt, addr,
924
+
next - addr);
925
+
if (next != end)
926
+
cond_resched();
927
+
} while (addr = next, addr != end);
928
+
}
929
+
930
+
static void kvm_stage2_destroy(struct kvm_pgtable *pgt)
931
+
{
932
+
unsigned int ia_bits = VTCR_EL2_IPA(pgt->mmu->vtcr);
933
+
934
+
stage2_destroy_range(pgt, 0, BIT(ia_bits));
935
+
KVM_PGT_FN(kvm_pgtable_stage2_destroy_pgd)(pgt);
936
+
}
937
+
907
938
/**
908
939
* kvm_init_stage2_mmu - Initialise a S2 MMU structure
909
940
* @kvm: The pointer to the KVM structure
···
1012
979
return 0;
1013
980
1014
981
out_destroy_pgtable:
1015
-
KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt);
982
+
kvm_stage2_destroy(pgt);
1016
983
out_free_pgtable:
1017
984
kfree(pgt);
1018
985
return err;
···
1109
1076
write_unlock(&kvm->mmu_lock);
1110
1077
1111
1078
if (pgt) {
1112
-
KVM_PGT_FN(kvm_pgtable_stage2_destroy)(pgt);
1079
+
kvm_stage2_destroy(pgt);
1113
1080
kfree(pgt);
1114
1081
}
1115
1082
}
···
1844
1811
read_unlock(&vcpu->kvm->mmu_lock);
1845
1812
}
1846
1813
1814
+
int kvm_handle_guest_sea(struct kvm_vcpu *vcpu)
1815
+
{
1816
+
/*
1817
+
* Give APEI the opportunity to claim the abort before handling it
1818
+
* within KVM. apei_claim_sea() expects to be called with IRQs enabled.
1819
+
*/
1820
+
lockdep_assert_irqs_enabled();
1821
+
if (apei_claim_sea(NULL) == 0)
1822
+
return 1;
1823
+
1824
+
return kvm_inject_serror(vcpu);
1825
+
}
1826
+
1847
1827
/**
1848
1828
* kvm_handle_guest_abort - handles all 2nd stage aborts
1849
1829
* @vcpu: the VCPU pointer
···
1880
1834
gfn_t gfn;
1881
1835
int ret, idx;
1882
1836
1883
-
/* Synchronous External Abort? */
1884
-
if (kvm_vcpu_abt_issea(vcpu)) {
1885
-
/*
1886
-
* For RAS the host kernel may handle this abort.
1887
-
* There is no need to pass the error into the guest.
1888
-
*/
1889
-
if (kvm_handle_guest_sea())
1890
-
return kvm_inject_serror(vcpu);
1891
-
1892
-
return 1;
1893
-
}
1837
+
if (kvm_vcpu_abt_issea(vcpu))
1838
+
return kvm_handle_guest_sea(vcpu);
1894
1839
1895
1840
esr = kvm_vcpu_get_esr(vcpu);
1896
1841
+4
-1
arch/arm64/kvm/nested.c
+4
-1
arch/arm64/kvm/nested.c
···
1287
1287
struct vncr_tlb *vt = vcpu->arch.vncr_tlb;
1288
1288
u64 esr = kvm_vcpu_get_esr(vcpu);
1289
1289
1290
-
BUG_ON(!(esr & ESR_ELx_VNCR_SHIFT));
1290
+
WARN_ON_ONCE(!(esr & ESR_ELx_VNCR));
1291
+
1292
+
if (kvm_vcpu_abt_issea(vcpu))
1293
+
return kvm_handle_guest_sea(vcpu);
1291
1294
1292
1295
if (esr_fsc_is_permission_fault(esr)) {
1293
1296
inject_vncr_perm(vcpu);
+9
-2
arch/arm64/kvm/pkvm.c
+9
-2
arch/arm64/kvm/pkvm.c
···
316
316
return 0;
317
317
}
318
318
319
-
void pkvm_pgtable_stage2_destroy(struct kvm_pgtable *pgt)
319
+
void pkvm_pgtable_stage2_destroy_range(struct kvm_pgtable *pgt,
320
+
u64 addr, u64 size)
320
321
{
321
-
__pkvm_pgtable_stage2_unmap(pgt, 0, ~(0ULL));
322
+
__pkvm_pgtable_stage2_unmap(pgt, addr, addr + size);
323
+
}
324
+
325
+
void pkvm_pgtable_stage2_destroy_pgd(struct kvm_pgtable *pgt)
326
+
{
327
+
/* Expected to be called after all pKVM mappings have been released. */
328
+
WARN_ON_ONCE(!RB_EMPTY_ROOT(&pgt->pkvm_mappings.rb_root));
322
329
}
323
330
324
331
int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
+293
-138
arch/arm64/kvm/sys_regs.c
+293
-138
arch/arm64/kvm/sys_regs.c
···
82
82
"sys_reg write to read-only register");
83
83
}
84
84
85
-
#define PURE_EL2_SYSREG(el2) \
86
-
case el2: { \
87
-
*el1r = el2; \
88
-
return true; \
89
-
}
85
+
enum sr_loc_attr {
86
+
SR_LOC_MEMORY = 0, /* Register definitely in memory */
87
+
SR_LOC_LOADED = BIT(0), /* Register on CPU, unless it cannot */
88
+
SR_LOC_MAPPED = BIT(1), /* Register in a different CPU register */
89
+
SR_LOC_XLATED = BIT(2), /* Register translated to fit another reg */
90
+
SR_LOC_SPECIAL = BIT(3), /* Demanding register, implies loaded */
91
+
};
90
92
91
-
#define MAPPED_EL2_SYSREG(el2, el1, fn) \
92
-
case el2: { \
93
-
*xlate = fn; \
94
-
*el1r = el1; \
95
-
return true; \
96
-
}
93
+
struct sr_loc {
94
+
enum sr_loc_attr loc;
95
+
enum vcpu_sysreg map_reg;
96
+
u64 (*xlate)(u64);
97
+
};
97
98
98
-
static bool get_el2_to_el1_mapping(unsigned int reg,
99
-
unsigned int *el1r, u64 (**xlate)(u64))
99
+
static enum sr_loc_attr locate_direct_register(const struct kvm_vcpu *vcpu,
100
+
enum vcpu_sysreg reg)
100
101
{
101
102
switch (reg) {
102
-
PURE_EL2_SYSREG( VPIDR_EL2 );
103
-
PURE_EL2_SYSREG( VMPIDR_EL2 );
104
-
PURE_EL2_SYSREG( ACTLR_EL2 );
105
-
PURE_EL2_SYSREG( HCR_EL2 );
106
-
PURE_EL2_SYSREG( MDCR_EL2 );
107
-
PURE_EL2_SYSREG( HSTR_EL2 );
108
-
PURE_EL2_SYSREG( HACR_EL2 );
109
-
PURE_EL2_SYSREG( VTTBR_EL2 );
110
-
PURE_EL2_SYSREG( VTCR_EL2 );
111
-
PURE_EL2_SYSREG( TPIDR_EL2 );
112
-
PURE_EL2_SYSREG( HPFAR_EL2 );
113
-
PURE_EL2_SYSREG( HCRX_EL2 );
114
-
PURE_EL2_SYSREG( HFGRTR_EL2 );
115
-
PURE_EL2_SYSREG( HFGWTR_EL2 );
116
-
PURE_EL2_SYSREG( HFGITR_EL2 );
117
-
PURE_EL2_SYSREG( HDFGRTR_EL2 );
118
-
PURE_EL2_SYSREG( HDFGWTR_EL2 );
119
-
PURE_EL2_SYSREG( HAFGRTR_EL2 );
120
-
PURE_EL2_SYSREG( CNTVOFF_EL2 );
121
-
PURE_EL2_SYSREG( CNTHCTL_EL2 );
103
+
case SCTLR_EL1:
104
+
case CPACR_EL1:
105
+
case TTBR0_EL1:
106
+
case TTBR1_EL1:
107
+
case TCR_EL1:
108
+
case TCR2_EL1:
109
+
case PIR_EL1:
110
+
case PIRE0_EL1:
111
+
case POR_EL1:
112
+
case ESR_EL1:
113
+
case AFSR0_EL1:
114
+
case AFSR1_EL1:
115
+
case FAR_EL1:
116
+
case MAIR_EL1:
117
+
case VBAR_EL1:
118
+
case CONTEXTIDR_EL1:
119
+
case AMAIR_EL1:
120
+
case CNTKCTL_EL1:
121
+
case ELR_EL1:
122
+
case SPSR_EL1:
123
+
case ZCR_EL1:
124
+
case SCTLR2_EL1:
125
+
/*
126
+
* EL1 registers which have an ELx2 mapping are loaded if
127
+
* we're not in hypervisor context.
128
+
*/
129
+
return is_hyp_ctxt(vcpu) ? SR_LOC_MEMORY : SR_LOC_LOADED;
130
+
131
+
case TPIDR_EL0:
132
+
case TPIDRRO_EL0:
133
+
case TPIDR_EL1:
134
+
case PAR_EL1:
135
+
case DACR32_EL2:
136
+
case IFSR32_EL2:
137
+
case DBGVCR32_EL2:
138
+
/* These registers are always loaded, no matter what */
139
+
return SR_LOC_LOADED;
140
+
141
+
default:
142
+
/* Non-mapped EL2 registers are by definition in memory. */
143
+
return SR_LOC_MEMORY;
144
+
}
145
+
}
146
+
147
+
static void locate_mapped_el2_register(const struct kvm_vcpu *vcpu,
148
+
enum vcpu_sysreg reg,
149
+
enum vcpu_sysreg map_reg,
150
+
u64 (*xlate)(u64),
151
+
struct sr_loc *loc)
152
+
{
153
+
if (!is_hyp_ctxt(vcpu)) {
154
+
loc->loc = SR_LOC_MEMORY;
155
+
return;
156
+
}
157
+
158
+
loc->loc = SR_LOC_LOADED | SR_LOC_MAPPED;
159
+
loc->map_reg = map_reg;
160
+
161
+
WARN_ON(locate_direct_register(vcpu, map_reg) != SR_LOC_MEMORY);
162
+
163
+
if (xlate != NULL && !vcpu_el2_e2h_is_set(vcpu)) {
164
+
loc->loc |= SR_LOC_XLATED;
165
+
loc->xlate = xlate;
166
+
}
167
+
}
168
+
169
+
#define MAPPED_EL2_SYSREG(r, m, t) \
170
+
case r: { \
171
+
locate_mapped_el2_register(vcpu, r, m, t, loc); \
172
+
break; \
173
+
}
174
+
175
+
static void locate_register(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg,
176
+
struct sr_loc *loc)
177
+
{
178
+
if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU)) {
179
+
loc->loc = SR_LOC_MEMORY;
180
+
return;
181
+
}
182
+
183
+
switch (reg) {
122
184
MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1,
123
185
translate_sctlr_el2_to_sctlr_el1 );
124
186
MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1,
···
206
144
MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL );
207
145
MAPPED_EL2_SYSREG(CONTEXTIDR_EL2, CONTEXTIDR_EL1, NULL );
208
146
MAPPED_EL2_SYSREG(SCTLR2_EL2, SCTLR2_EL1, NULL );
147
+
case CNTHCTL_EL2:
148
+
/* CNTHCTL_EL2 is super special, until we support NV2.1 */
149
+
loc->loc = ((is_hyp_ctxt(vcpu) && vcpu_el2_e2h_is_set(vcpu)) ?
150
+
SR_LOC_SPECIAL : SR_LOC_MEMORY);
151
+
break;
209
152
default:
210
-
return false;
153
+
loc->loc = locate_direct_register(vcpu, reg);
211
154
}
212
155
}
213
156
214
-
u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
157
+
static u64 read_sr_from_cpu(enum vcpu_sysreg reg)
215
158
{
216
159
u64 val = 0x8badf00d8badf00d;
217
-
u64 (*xlate)(u64) = NULL;
218
-
unsigned int el1r;
219
160
220
-
if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
221
-
goto memory_read;
161
+
switch (reg) {
162
+
case SCTLR_EL1: val = read_sysreg_s(SYS_SCTLR_EL12); break;
163
+
case CPACR_EL1: val = read_sysreg_s(SYS_CPACR_EL12); break;
164
+
case TTBR0_EL1: val = read_sysreg_s(SYS_TTBR0_EL12); break;
165
+
case TTBR1_EL1: val = read_sysreg_s(SYS_TTBR1_EL12); break;
166
+
case TCR_EL1: val = read_sysreg_s(SYS_TCR_EL12); break;
167
+
case TCR2_EL1: val = read_sysreg_s(SYS_TCR2_EL12); break;
168
+
case PIR_EL1: val = read_sysreg_s(SYS_PIR_EL12); break;
169
+
case PIRE0_EL1: val = read_sysreg_s(SYS_PIRE0_EL12); break;
170
+
case POR_EL1: val = read_sysreg_s(SYS_POR_EL12); break;
171
+
case ESR_EL1: val = read_sysreg_s(SYS_ESR_EL12); break;
172
+
case AFSR0_EL1: val = read_sysreg_s(SYS_AFSR0_EL12); break;
173
+
case AFSR1_EL1: val = read_sysreg_s(SYS_AFSR1_EL12); break;
174
+
case FAR_EL1: val = read_sysreg_s(SYS_FAR_EL12); break;
175
+
case MAIR_EL1: val = read_sysreg_s(SYS_MAIR_EL12); break;
176
+
case VBAR_EL1: val = read_sysreg_s(SYS_VBAR_EL12); break;
177
+
case CONTEXTIDR_EL1: val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
178
+
case AMAIR_EL1: val = read_sysreg_s(SYS_AMAIR_EL12); break;
179
+
case CNTKCTL_EL1: val = read_sysreg_s(SYS_CNTKCTL_EL12); break;
180
+
case ELR_EL1: val = read_sysreg_s(SYS_ELR_EL12); break;
181
+
case SPSR_EL1: val = read_sysreg_s(SYS_SPSR_EL12); break;
182
+
case ZCR_EL1: val = read_sysreg_s(SYS_ZCR_EL12); break;
183
+
case SCTLR2_EL1: val = read_sysreg_s(SYS_SCTLR2_EL12); break;
184
+
case TPIDR_EL0: val = read_sysreg_s(SYS_TPIDR_EL0); break;
185
+
case TPIDRRO_EL0: val = read_sysreg_s(SYS_TPIDRRO_EL0); break;
186
+
case TPIDR_EL1: val = read_sysreg_s(SYS_TPIDR_EL1); break;
187
+
case PAR_EL1: val = read_sysreg_par(); break;
188
+
case DACR32_EL2: val = read_sysreg_s(SYS_DACR32_EL2); break;
189
+
case IFSR32_EL2: val = read_sysreg_s(SYS_IFSR32_EL2); break;
190
+
case DBGVCR32_EL2: val = read_sysreg_s(SYS_DBGVCR32_EL2); break;
191
+
default: WARN_ON_ONCE(1);
192
+
}
222
193
223
-
if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
224
-
if (!is_hyp_ctxt(vcpu))
225
-
goto memory_read;
194
+
return val;
195
+
}
196
+
197
+
static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 val)
198
+
{
199
+
switch (reg) {
200
+
case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break;
201
+
case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break;
202
+
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break;
203
+
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break;
204
+
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break;
205
+
case TCR2_EL1: write_sysreg_s(val, SYS_TCR2_EL12); break;
206
+
case PIR_EL1: write_sysreg_s(val, SYS_PIR_EL12); break;
207
+
case PIRE0_EL1: write_sysreg_s(val, SYS_PIRE0_EL12); break;
208
+
case POR_EL1: write_sysreg_s(val, SYS_POR_EL12); break;
209
+
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break;
210
+
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break;
211
+
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break;
212
+
case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break;
213
+
case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break;
214
+
case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break;
215
+
case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
216
+
case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break;
217
+
case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break;
218
+
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break;
219
+
case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break;
220
+
case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break;
221
+
case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break;
222
+
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break;
223
+
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break;
224
+
case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break;
225
+
case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break;
226
+
case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break;
227
+
case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break;
228
+
case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break;
229
+
default: WARN_ON_ONCE(1);
230
+
}
231
+
}
232
+
233
+
u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
234
+
{
235
+
struct sr_loc loc = {};
236
+
237
+
locate_register(vcpu, reg, &loc);
238
+
239
+
WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY);
240
+
241
+
if (loc.loc & SR_LOC_SPECIAL) {
242
+
u64 val;
243
+
244
+
WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL);
226
245
227
246
/*
228
-
* CNTHCTL_EL2 requires some special treatment to
229
-
* account for the bits that can be set via CNTKCTL_EL1.
247
+
* CNTHCTL_EL2 requires some special treatment to account
248
+
* for the bits that can be set via CNTKCTL_EL1 when E2H==1.
230
249
*/
231
250
switch (reg) {
232
251
case CNTHCTL_EL2:
233
-
if (vcpu_el2_e2h_is_set(vcpu)) {
234
-
val = read_sysreg_el1(SYS_CNTKCTL);
235
-
val &= CNTKCTL_VALID_BITS;
236
-
val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
237
-
return val;
238
-
}
239
-
break;
252
+
val = read_sysreg_el1(SYS_CNTKCTL);
253
+
val &= CNTKCTL_VALID_BITS;
254
+
val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
255
+
return val;
256
+
default:
257
+
WARN_ON_ONCE(1);
240
258
}
241
-
242
-
/*
243
-
* If this register does not have an EL1 counterpart,
244
-
* then read the stored EL2 version.
245
-
*/
246
-
if (reg == el1r)
247
-
goto memory_read;
248
-
249
-
/*
250
-
* If we have a non-VHE guest and that the sysreg
251
-
* requires translation to be used at EL1, use the
252
-
* in-memory copy instead.
253
-
*/
254
-
if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
255
-
goto memory_read;
256
-
257
-
/* Get the current version of the EL1 counterpart. */
258
-
WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
259
-
if (reg >= __SANITISED_REG_START__)
260
-
val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
261
-
262
-
return val;
263
259
}
264
260
265
-
/* EL1 register can't be on the CPU if the guest is in vEL2. */
266
-
if (unlikely(is_hyp_ctxt(vcpu)))
267
-
goto memory_read;
261
+
if (loc.loc & SR_LOC_LOADED) {
262
+
enum vcpu_sysreg map_reg = reg;
268
263
269
-
if (__vcpu_read_sys_reg_from_cpu(reg, &val))
270
-
return val;
264
+
if (loc.loc & SR_LOC_MAPPED)
265
+
map_reg = loc.map_reg;
271
266
272
-
memory_read:
267
+
if (!(loc.loc & SR_LOC_XLATED)) {
268
+
u64 val = read_sr_from_cpu(map_reg);
269
+
270
+
if (reg >= __SANITISED_REG_START__)
271
+
val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
272
+
273
+
return val;
274
+
}
275
+
}
276
+
273
277
return __vcpu_sys_reg(vcpu, reg);
274
278
}
275
279
276
-
void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
280
+
void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, enum vcpu_sysreg reg)
277
281
{
278
-
u64 (*xlate)(u64) = NULL;
279
-
unsigned int el1r;
282
+
struct sr_loc loc = {};
280
283
281
-
if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
282
-
goto memory_write;
284
+
locate_register(vcpu, reg, &loc);
283
285
284
-
if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
285
-
if (!is_hyp_ctxt(vcpu))
286
-
goto memory_write;
286
+
WARN_ON_ONCE(!has_vhe() && loc.loc != SR_LOC_MEMORY);
287
287
288
-
/*
289
-
* Always store a copy of the write to memory to avoid having
290
-
* to reverse-translate virtual EL2 system registers for a
291
-
* non-VHE guest hypervisor.
292
-
*/
293
-
__vcpu_assign_sys_reg(vcpu, reg, val);
288
+
if (loc.loc & SR_LOC_SPECIAL) {
289
+
290
+
WARN_ON_ONCE(loc.loc & ~SR_LOC_SPECIAL);
294
291
295
292
switch (reg) {
296
293
case CNTHCTL_EL2:
297
294
/*
298
-
* If E2H=0, CNHTCTL_EL2 is a pure shadow register.
299
-
* Otherwise, some of the bits are backed by
295
+
* If E2H=1, some of the bits are backed by
300
296
* CNTKCTL_EL1, while the rest is kept in memory.
301
297
* Yes, this is fun stuff.
302
298
*/
303
-
if (vcpu_el2_e2h_is_set(vcpu))
304
-
write_sysreg_el1(val, SYS_CNTKCTL);
305
-
return;
299
+
write_sysreg_el1(val, SYS_CNTKCTL);
300
+
break;
301
+
default:
302
+
WARN_ON_ONCE(1);
306
303
}
307
-
308
-
/* No EL1 counterpart? We're done here.? */
309
-
if (reg == el1r)
310
-
return;
311
-
312
-
if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
313
-
val = xlate(val);
314
-
315
-
/* Redirect this to the EL1 version of the register. */
316
-
WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
317
-
return;
318
304
}
319
305
320
-
/* EL1 register can't be on the CPU if the guest is in vEL2. */
321
-
if (unlikely(is_hyp_ctxt(vcpu)))
322
-
goto memory_write;
306
+
if (loc.loc & SR_LOC_LOADED) {
307
+
enum vcpu_sysreg map_reg = reg;
308
+
u64 xlated_val;
323
309
324
-
if (__vcpu_write_sys_reg_to_cpu(val, reg))
325
-
return;
310
+
if (reg >= __SANITISED_REG_START__)
311
+
val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
326
312
327
-
memory_write:
313
+
if (loc.loc & SR_LOC_MAPPED)
314
+
map_reg = loc.map_reg;
315
+
316
+
if (loc.loc & SR_LOC_XLATED)
317
+
xlated_val = loc.xlate(val);
318
+
else
319
+
xlated_val = val;
320
+
321
+
write_sr_to_cpu(map_reg, xlated_val);
322
+
323
+
/*
324
+
* Fall through to write the backing store anyway, which
325
+
* allows translated registers to be directly read without a
326
+
* reverse translation.
327
+
*/
328
+
}
329
+
328
330
__vcpu_assign_sys_reg(vcpu, reg, val);
329
331
}
330
332
···
1710
1584
}
1711
1585
1712
1586
static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1587
+
static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val);
1713
1588
static u64 sanitise_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val);
1714
1589
1715
1590
/* Read a sanitised cpufeature ID register by sys_reg_desc */
···
1733
1606
val = sanitise_id_aa64pfr0_el1(vcpu, val);
1734
1607
break;
1735
1608
case SYS_ID_AA64PFR1_EL1:
1736
-
if (!kvm_has_mte(vcpu->kvm)) {
1737
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1738
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
1739
-
}
1740
-
1741
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1742
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
1743
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
1744
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
1745
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
1746
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
1747
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
1748
-
val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MPAM_frac);
1609
+
val = sanitise_id_aa64pfr1_el1(vcpu, val);
1749
1610
break;
1750
1611
case SYS_ID_AA64PFR2_EL1:
1751
1612
val &= ID_AA64PFR2_EL1_FPMR |
···
1743
1628
break;
1744
1629
case SYS_ID_AA64ISAR1_EL1:
1745
1630
if (!vcpu_has_ptrauth(vcpu))
1746
-
val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1747
-
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1748
-
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1749
-
ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1631
+
val &= ~(ID_AA64ISAR1_EL1_APA |
1632
+
ID_AA64ISAR1_EL1_API |
1633
+
ID_AA64ISAR1_EL1_GPA |
1634
+
ID_AA64ISAR1_EL1_GPI);
1750
1635
break;
1751
1636
case SYS_ID_AA64ISAR2_EL1:
1752
1637
if (!vcpu_has_ptrauth(vcpu))
1753
-
val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1754
-
ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1638
+
val &= ~(ID_AA64ISAR2_EL1_APA3 |
1639
+
ID_AA64ISAR2_EL1_GPA3);
1755
1640
if (!cpus_have_final_cap(ARM64_HAS_WFXT) ||
1756
1641
has_broken_cntvoff())
1757
-
val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1642
+
val &= ~ID_AA64ISAR2_EL1_WFxT;
1758
1643
break;
1759
1644
case SYS_ID_AA64ISAR3_EL1:
1760
1645
val &= ID_AA64ISAR3_EL1_FPRCVT | ID_AA64ISAR3_EL1_FAMINMAX;
···
1770
1655
ID_AA64MMFR3_EL1_S1PIE;
1771
1656
break;
1772
1657
case SYS_ID_MMFR4_EL1:
1773
-
val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1658
+
val &= ~ID_MMFR4_EL1_CCIDX;
1774
1659
break;
1775
1660
}
1776
1661
···
1947
1832
* older kernels let the guest see the ID bit.
1948
1833
*/
1949
1834
val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
1835
+
1836
+
return val;
1837
+
}
1838
+
1839
+
static u64 sanitise_id_aa64pfr1_el1(const struct kvm_vcpu *vcpu, u64 val)
1840
+
{
1841
+
u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1842
+
1843
+
if (!kvm_has_mte(vcpu->kvm)) {
1844
+
val &= ~ID_AA64PFR1_EL1_MTE;
1845
+
val &= ~ID_AA64PFR1_EL1_MTE_frac;
1846
+
}
1847
+
1848
+
if (!(cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN) &&
1849
+
SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) == ID_AA64PFR0_EL1_RAS_IMP))
1850
+
val &= ~ID_AA64PFR1_EL1_RAS_frac;
1851
+
1852
+
val &= ~ID_AA64PFR1_EL1_SME;
1853
+
val &= ~ID_AA64PFR1_EL1_RNDR_trap;
1854
+
val &= ~ID_AA64PFR1_EL1_NMI;
1855
+
val &= ~ID_AA64PFR1_EL1_GCS;
1856
+
val &= ~ID_AA64PFR1_EL1_THE;
1857
+
val &= ~ID_AA64PFR1_EL1_MTEX;
1858
+
val &= ~ID_AA64PFR1_EL1_PFAR;
1859
+
val &= ~ID_AA64PFR1_EL1_MPAM_frac;
1950
1860
1951
1861
return val;
1952
1862
}
···
2837
2697
struct kvm *kvm = vcpu->kvm;
2838
2698
2839
2699
switch(reg_to_encoding(r)) {
2700
+
case SYS_ERXPFGCDN_EL1:
2701
+
case SYS_ERXPFGCTL_EL1:
2702
+
case SYS_ERXPFGF_EL1:
2703
+
case SYS_ERXMISC2_EL1:
2704
+
case SYS_ERXMISC3_EL1:
2705
+
if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ||
2706
+
(kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) &&
2707
+
kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) {
2708
+
kvm_inject_undefined(vcpu);
2709
+
return false;
2710
+
}
2711
+
break;
2840
2712
default:
2841
2713
if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) {
2842
2714
kvm_inject_undefined(vcpu);
···
3081
2929
~(ID_AA64PFR0_EL1_AMU |
3082
2930
ID_AA64PFR0_EL1_MPAM |
3083
2931
ID_AA64PFR0_EL1_SVE |
3084
-
ID_AA64PFR0_EL1_RAS |
3085
2932
ID_AA64PFR0_EL1_AdvSIMD |
3086
2933
ID_AA64PFR0_EL1_FP)),
3087
2934
ID_FILTERED(ID_AA64PFR1_EL1, id_aa64pfr1_el1,
···
3094
2943
ID_AA64PFR1_EL1_SME |
3095
2944
ID_AA64PFR1_EL1_RES0 |
3096
2945
ID_AA64PFR1_EL1_MPAM_frac |
3097
-
ID_AA64PFR1_EL1_RAS_frac |
3098
2946
ID_AA64PFR1_EL1_MTE)),
3099
2947
ID_WRITABLE(ID_AA64PFR2_EL1,
3100
2948
ID_AA64PFR2_EL1_FPMR |
···
3213
3063
{ SYS_DESC(SYS_ERXCTLR_EL1), access_ras },
3214
3064
{ SYS_DESC(SYS_ERXSTATUS_EL1), access_ras },
3215
3065
{ SYS_DESC(SYS_ERXADDR_EL1), access_ras },
3066
+
{ SYS_DESC(SYS_ERXPFGF_EL1), access_ras },
3067
+
{ SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras },
3068
+
{ SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras },
3216
3069
{ SYS_DESC(SYS_ERXMISC0_EL1), access_ras },
3217
3070
{ SYS_DESC(SYS_ERXMISC1_EL1), access_ras },
3071
+
{ SYS_DESC(SYS_ERXMISC2_EL1), access_ras },
3072
+
{ SYS_DESC(SYS_ERXMISC3_EL1), access_ras },
3218
3073
3219
3074
MTE_REG(TFSR_EL1),
3220
3075
MTE_REG(TFSRE0_EL1),
+8
arch/arm64/kvm/vgic/vgic-mmio-v3.c
+8
arch/arm64/kvm/vgic/vgic-mmio-v3.c
···
50
50
51
51
bool vgic_supports_direct_msis(struct kvm *kvm)
52
52
{
53
+
/*
54
+
* Deliberately conflate vLPI and vSGI support on GICv4.1 hardware,
55
+
* indirectly allowing userspace to control whether or not vPEs are
56
+
* allocated for the VM.
57
+
*/
58
+
if (system_supports_direct_sgis() && !vgic_supports_direct_sgis(kvm))
59
+
return false;
60
+
53
61
return kvm_vgic_global_state.has_gicv4 && vgic_has_its(kvm);
54
62
}
55
63
+1
-1
arch/arm64/kvm/vgic/vgic-mmio.c
+1
-1
arch/arm64/kvm/vgic/vgic-mmio.c
+1
-9
arch/arm64/kvm/vgic/vgic.h
+1
-9
arch/arm64/kvm/vgic/vgic.h
···
396
396
397
397
static inline bool vgic_supports_direct_irqs(struct kvm *kvm)
398
398
{
399
-
/*
400
-
* Deliberately conflate vLPI and vSGI support on GICv4.1 hardware,
401
-
* indirectly allowing userspace to control whether or not vPEs are
402
-
* allocated for the VM.
403
-
*/
404
-
if (system_supports_direct_sgis())
405
-
return vgic_supports_direct_sgis(kvm);
406
-
407
-
return vgic_supports_direct_msis(kvm);
399
+
return vgic_supports_direct_msis(kvm) || vgic_supports_direct_sgis(kvm);
408
400
}
409
401
410
402
int vgic_v4_init(struct kvm *kvm);
+1
arch/arm64/tools/cpucaps
+1
arch/arm64/tools/cpucaps
+4
-1
arch/riscv/kvm/mmu.c
+4
-1
arch/riscv/kvm/mmu.c
···
39
39
unsigned long size, bool writable, bool in_atomic)
40
40
{
41
41
int ret = 0;
42
+
pgprot_t prot;
42
43
unsigned long pfn;
43
44
phys_addr_t addr, end;
44
45
struct kvm_mmu_memory_cache pcache = {
···
56
55
57
56
end = (gpa + size + PAGE_SIZE - 1) & PAGE_MASK;
58
57
pfn = __phys_to_pfn(hpa);
58
+
prot = pgprot_noncached(PAGE_WRITE);
59
59
60
60
for (addr = gpa; addr < end; addr += PAGE_SIZE) {
61
61
map.addr = addr;
62
-
map.pte = pfn_pte(pfn, PAGE_KERNEL_IO);
62
+
map.pte = pfn_pte(pfn, prot);
63
+
map.pte = pte_mkdirty(map.pte);
63
64
map.level = 0;
64
65
65
66
if (!writable)
+1
-1
arch/riscv/kvm/vcpu.c
+1
-1
arch/riscv/kvm/vcpu.c
+2
arch/riscv/kvm/vcpu_vector.c
+2
arch/riscv/kvm/vcpu_vector.c
+2
arch/x86/kvm/lapic.c
+2
arch/x86/kvm/lapic.c
+3
-7
arch/x86/kvm/svm/sev.c
+3
-7
arch/x86/kvm/svm/sev.c
···
719
719
static void sev_writeback_caches(struct kvm *kvm)
720
720
{
721
721
/*
722
-
* Note, the caller is responsible for ensuring correctness if the mask
723
-
* can be modified, e.g. if a CPU could be doing VMRUN.
724
-
*/
725
-
if (cpumask_empty(to_kvm_sev_info(kvm)->have_run_cpus))
726
-
return;
727
-
728
-
/*
729
722
* Ensure that all dirty guest tagged cache entries are written back
730
723
* before releasing the pages back to the system for use. CLFLUSH will
731
724
* not do this without SME_COHERENT, and flushing many cache lines
···
732
739
* serializing multiple calls and having responding CPUs (to the IPI)
733
740
* mark themselves as still running if they are running (or about to
734
741
* run) a vCPU for the VM.
742
+
*
743
+
* Note, the caller is responsible for ensuring correctness if the mask
744
+
* can be modified, e.g. if a CPU could be doing VMRUN.
735
745
*/
736
746
wbnoinvd_on_cpus_mask(to_kvm_sev_info(kvm)->have_run_cpus);
737
747
}
+5
-2
arch/x86/kvm/x86.c
+5
-2
arch/x86/kvm/x86.c
···
9908
9908
rcu_read_lock();
9909
9909
map = rcu_dereference(vcpu->kvm->arch.apic_map);
9910
9910
9911
-
if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9912
-
target = map->phys_map[dest_id]->vcpu;
9911
+
if (likely(map) && dest_id <= map->max_apic_id) {
9912
+
dest_id = array_index_nospec(dest_id, map->max_apic_id + 1);
9913
+
if (map->phys_map[dest_id])
9914
+
target = map->phys_map[dest_id]->vcpu;
9915
+
}
9913
9916
9914
9917
rcu_read_unlock();
9915
9918
-3
tools/arch/arm64/include/asm/sysreg.h
-3
tools/arch/arm64/include/asm/sysreg.h
+2
-2
tools/testing/selftests/kselftest_harness.h
+2
-2
tools/testing/selftests/kselftest_harness.h
···
751
751
for (; _metadata->trigger; _metadata->trigger = \
752
752
__bail(_assert, _metadata))
753
753
754
-
#define is_signed_type(var) (!!(((__typeof__(var))(-1)) < (__typeof__(var))1))
754
+
#define is_signed_var(var) (!!(((__typeof__(var))(-1)) < (__typeof__(var))1))
755
755
756
756
#define __EXPECT(_expected, _expected_str, _seen, _seen_str, _t, _assert) do { \
757
757
/* Avoid multiple evaluation of the cases */ \
···
759
759
__typeof__(_seen) __seen = (_seen); \
760
760
if (!(__exp _t __seen)) { \
761
761
/* Report with actual signedness to avoid weird output. */ \
762
-
switch (is_signed_type(__exp) * 2 + is_signed_type(__seen)) { \
762
+
switch (is_signed_var(__exp) * 2 + is_signed_var(__seen)) { \
763
763
case 0: { \
764
764
uintmax_t __exp_print = (uintmax_t)__exp; \
765
765
uintmax_t __seen_print = (uintmax_t)__seen; \
+1
tools/testing/selftests/kvm/Makefile.kvm
+1
tools/testing/selftests/kvm/Makefile.kvm
···
169
169
TEST_GEN_PROGS_arm64 += arm64/vgic_lpi_stress
170
170
TEST_GEN_PROGS_arm64 += arm64/vpmu_counter_access
171
171
TEST_GEN_PROGS_arm64 += arm64/no-vgic-v3
172
+
TEST_GEN_PROGS_arm64 += arm64/kvm-uuid
172
173
TEST_GEN_PROGS_arm64 += access_tracking_perf_test
173
174
TEST_GEN_PROGS_arm64 += arch_timer
174
175
TEST_GEN_PROGS_arm64 += coalesced_io_test
+1
-1
tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
+1
-1
tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
+6
-6
tools/testing/selftests/kvm/arm64/debug-exceptions.c
+6
-6
tools/testing/selftests/kvm/arm64/debug-exceptions.c
···
116
116
117
117
/* Reset all bcr/bvr/wcr/wvr registers */
118
118
dfr0 = read_sysreg(id_aa64dfr0_el1);
119
-
brps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), dfr0);
119
+
brps = FIELD_GET(ID_AA64DFR0_EL1_BRPs, dfr0);
120
120
for (i = 0; i <= brps; i++) {
121
121
write_dbgbcr(i, 0);
122
122
write_dbgbvr(i, 0);
123
123
}
124
-
wrps = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), dfr0);
124
+
wrps = FIELD_GET(ID_AA64DFR0_EL1_WRPs, dfr0);
125
125
for (i = 0; i <= wrps; i++) {
126
126
write_dbgwcr(i, 0);
127
127
write_dbgwvr(i, 0);
···
418
418
419
419
static int debug_version(uint64_t id_aa64dfr0)
420
420
{
421
-
return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DebugVer), id_aa64dfr0);
421
+
return FIELD_GET(ID_AA64DFR0_EL1_DebugVer, id_aa64dfr0);
422
422
}
423
423
424
424
static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)
···
539
539
int b, w, c;
540
540
541
541
/* Number of breakpoints */
542
-
brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_BRPs), aa64dfr0) + 1;
542
+
brp_num = FIELD_GET(ID_AA64DFR0_EL1_BRPs, aa64dfr0) + 1;
543
543
__TEST_REQUIRE(brp_num >= 2, "At least two breakpoints are required");
544
544
545
545
/* Number of watchpoints */
546
-
wrp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_WRPs), aa64dfr0) + 1;
546
+
wrp_num = FIELD_GET(ID_AA64DFR0_EL1_WRPs, aa64dfr0) + 1;
547
547
548
548
/* Number of context aware breakpoints */
549
-
ctx_brp_num = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_CTX_CMPs), aa64dfr0) + 1;
549
+
ctx_brp_num = FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, aa64dfr0) + 1;
550
550
551
551
pr_debug("%s brp_num:%d, wrp_num:%d, ctx_brp_num:%d\n", __func__,
552
552
brp_num, wrp_num, ctx_brp_num);
+70
tools/testing/selftests/kvm/arm64/kvm-uuid.c
+70
tools/testing/selftests/kvm/arm64/kvm-uuid.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
3
+
// Check that nobody has tampered with KVM's UID
4
+
5
+
#include <errno.h>
6
+
#include <linux/arm-smccc.h>
7
+
#include <asm/kvm.h>
8
+
#include <kvm_util.h>
9
+
10
+
#include "processor.h"
11
+
12
+
/*
13
+
* Do NOT redefine these constants, or try to replace them with some
14
+
* "common" version. They are hardcoded here to detect any potential
15
+
* breakage happening in the rest of the kernel.
16
+
*
17
+
* KVM UID value: 28b46fb6-2ec5-11e9-a9ca-4b564d003a74
18
+
*/
19
+
#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 0xb66fb428U
20
+
#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 0xe911c52eU
21
+
#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 0x564bcaa9U
22
+
#define ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3 0x743a004dU
23
+
24
+
static void guest_code(void)
25
+
{
26
+
struct arm_smccc_res res = {};
27
+
28
+
smccc_hvc(ARM_SMCCC_VENDOR_HYP_CALL_UID_FUNC_ID, 0, 0, 0, 0, 0, 0, 0, &res);
29
+
30
+
__GUEST_ASSERT(res.a0 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_0 &&
31
+
res.a1 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_1 &&
32
+
res.a2 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_2 &&
33
+
res.a3 == ARM_SMCCC_VENDOR_HYP_UID_KVM_REG_3,
34
+
"Unexpected KVM-specific UID %lx %lx %lx %lx\n", res.a0, res.a1, res.a2, res.a3);
35
+
GUEST_DONE();
36
+
}
37
+
38
+
int main (int argc, char *argv[])
39
+
{
40
+
struct kvm_vcpu *vcpu;
41
+
struct kvm_vm *vm;
42
+
struct ucall uc;
43
+
bool guest_done = false;
44
+
45
+
vm = vm_create_with_one_vcpu(&vcpu, guest_code);
46
+
47
+
while (!guest_done) {
48
+
vcpu_run(vcpu);
49
+
50
+
switch (get_ucall(vcpu, &uc)) {
51
+
case UCALL_SYNC:
52
+
break;
53
+
case UCALL_DONE:
54
+
guest_done = true;
55
+
break;
56
+
case UCALL_ABORT:
57
+
REPORT_GUEST_ASSERT(uc);
58
+
break;
59
+
case UCALL_PRINTF:
60
+
printf("%s", uc.buffer);
61
+
break;
62
+
default:
63
+
TEST_FAIL("Unexpected guest exit");
64
+
}
65
+
}
66
+
67
+
kvm_vm_free(vm);
68
+
69
+
return 0;
70
+
}
+2
-2
tools/testing/selftests/kvm/arm64/no-vgic-v3.c
+2
-2
tools/testing/selftests/kvm/arm64/no-vgic-v3.c
···
54
54
* Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having
55
55
* hidden the feature at runtime without any other userspace action.
56
56
*/
57
-
__GUEST_ASSERT(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC),
57
+
__GUEST_ASSERT(FIELD_GET(ID_AA64PFR0_EL1_GIC,
58
58
read_sysreg(id_aa64pfr0_el1)) == 0,
59
59
"GICv3 wrongly advertised");
60
60
···
165
165
166
166
vm = vm_create_with_one_vcpu(&vcpu, NULL);
167
167
pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
168
-
__TEST_REQUIRE(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), pfr0),
168
+
__TEST_REQUIRE(FIELD_GET(ID_AA64PFR0_EL1_GIC, pfr0),
169
169
"GICv3 not supported.");
170
170
kvm_vm_free(vm);
171
171
+3
-3
tools/testing/selftests/kvm/arm64/page_fault_test.c
+3
-3
tools/testing/selftests/kvm/arm64/page_fault_test.c
···
95
95
uint64_t isar0 = read_sysreg(id_aa64isar0_el1);
96
96
uint64_t atomic;
97
97
98
-
atomic = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMIC), isar0);
98
+
atomic = FIELD_GET(ID_AA64ISAR0_EL1_ATOMIC, isar0);
99
99
return atomic >= 2;
100
100
}
101
101
102
102
static bool guest_check_dc_zva(void)
103
103
{
104
104
uint64_t dczid = read_sysreg(dczid_el0);
105
-
uint64_t dzp = FIELD_GET(ARM64_FEATURE_MASK(DCZID_EL0_DZP), dczid);
105
+
uint64_t dzp = FIELD_GET(DCZID_EL0_DZP, dczid);
106
106
107
107
return dzp == 0;
108
108
}
···
195
195
uint64_t hadbs, tcr;
196
196
197
197
/* Skip if HA is not supported. */
198
-
hadbs = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS), mmfr1);
198
+
hadbs = FIELD_GET(ID_AA64MMFR1_EL1_HAFDBS, mmfr1);
199
199
if (hadbs == 0)
200
200
return false;
201
201
+5
-4
tools/testing/selftests/kvm/arm64/set_id_regs.c
+5
-4
tools/testing/selftests/kvm/arm64/set_id_regs.c
···
243
243
GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
244
244
GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
245
245
GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
246
+
GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1);
246
247
GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
247
248
GUEST_REG_SYNC(SYS_CTR_EL0);
248
249
GUEST_REG_SYNC(SYS_MIDR_EL1);
···
595
594
*/
596
595
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
597
596
598
-
mte = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE), val);
599
-
mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
597
+
mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val);
598
+
mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
600
599
if (mte != ID_AA64PFR1_EL1_MTE_MTE2 ||
601
600
mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) {
602
601
ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n");
···
613
612
}
614
613
615
614
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
616
-
mte_frac = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac), val);
615
+
mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
617
616
if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI)
618
617
ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n");
619
618
else
···
775
774
776
775
/* Check for AARCH64 only system */
777
776
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
778
-
el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
777
+
el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val);
779
778
aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
780
779
781
780
ksft_print_header();
+1
-1
tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
+1
-1
tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
···
441
441
442
442
/* Make sure that PMUv3 support is indicated in the ID register */
443
443
dfr0 = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
444
-
pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), dfr0);
444
+
pmuver = FIELD_GET(ID_AA64DFR0_EL1_PMUVer, dfr0);
445
445
TEST_ASSERT(pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF &&
446
446
pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP,
447
447
"Unexpected PMUVER (0x%x) on the vCPU with PMUv3", pmuver);
+3
-3
tools/testing/selftests/kvm/lib/arm64/processor.c
+3
-3
tools/testing/selftests/kvm/lib/arm64/processor.c
···
573
573
err = ioctl(vcpu_fd, KVM_GET_ONE_REG, ®);
574
574
TEST_ASSERT(err == 0, KVM_IOCTL_ERROR(KVM_GET_ONE_REG, vcpu_fd));
575
575
576
-
gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN4), val);
576
+
gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN4, val);
577
577
*ipa4k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN4_NI,
578
578
ID_AA64MMFR0_EL1_TGRAN4_52_BIT);
579
579
580
-
gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN64), val);
580
+
gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN64, val);
581
581
*ipa64k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN64_NI,
582
582
ID_AA64MMFR0_EL1_TGRAN64_IMP);
583
583
584
-
gran = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_TGRAN16), val);
584
+
gran = FIELD_GET(ID_AA64MMFR0_EL1_TGRAN16, val);
585
585
*ipa16k = max_ipa_for_page_size(ipa, gran, ID_AA64MMFR0_EL1_TGRAN16_NI,
586
586
ID_AA64MMFR0_EL1_TGRAN16_52_BIT);
587
587