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arm64: dts: qcom: sa8775p-ride: enable ethernet0

Enable the first 1Gb ethernet port on sa8775p-ride development board.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Bartosz Golaszewski and committed by
Bjorn Andersson
120ab6c0 48c99529

+88
+88
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
··· 261 261 }; 262 262 }; 263 263 264 + &ethernet0 { 265 + phy-mode = "sgmii"; 266 + phy-handle = <&sgmii_phy>; 267 + 268 + pinctrl-0 = <&ethernet0_default>; 269 + pinctrl-names = "default"; 270 + 271 + snps,mtl-rx-config = <&mtl_rx_setup>; 272 + snps,mtl-tx-config = <&mtl_tx_setup>; 273 + snps,ps-speed = <1000>; 274 + 275 + status = "okay"; 276 + 277 + mdio { 278 + compatible = "snps,dwmac-mdio"; 279 + #address-cells = <1>; 280 + #size-cells = <0>; 281 + 282 + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; 283 + reset-delay-us = <11000>; 284 + reset-post-delay-us = <70000>; 285 + 286 + sgmii_phy: phy@8 { 287 + reg = <0x8>; 288 + device_type = "ethernet-phy"; 289 + }; 290 + }; 291 + 292 + mtl_rx_setup: rx-queues-config { 293 + snps,rx-queues-to-use = <4>; 294 + snps,rx-sched-sp; 295 + 296 + queue0 { 297 + snps,dcb-algorithm; 298 + snps,map-to-dma-channel = <0x0>; 299 + snps,route-up; 300 + snps,priority = <0x1>; 301 + }; 302 + 303 + queue1 { 304 + snps,dcb-algorithm; 305 + snps,map-to-dma-channel = <0x1>; 306 + snps,route-ptp; 307 + }; 308 + 309 + queue2 { 310 + snps,avb-algorithm; 311 + snps,map-to-dma-channel = <0x2>; 312 + snps,route-avcp; 313 + }; 314 + 315 + queue3 { 316 + snps,avb-algorithm; 317 + snps,map-to-dma-channel = <0x3>; 318 + snps,priority = <0xc>; 319 + }; 320 + }; 321 + 322 + mtl_tx_setup: tx-queues-config { 323 + snps,tx-queues-to-use = <4>; 324 + snps,tx-sched-sp; 325 + 326 + queue0 { 327 + snps,dcb-algorithm; 328 + }; 329 + 330 + queue1 { 331 + snps,dcb-algorithm; 332 + }; 333 + 334 + queue2 { 335 + snps,avb-algorithm; 336 + snps,send_slope = <0x1000>; 337 + snps,idle_slope = <0x1000>; 338 + snps,high_credit = <0x3e800>; 339 + snps,low_credit = <0xffc18000>; 340 + }; 341 + 342 + queue3 { 343 + snps,avb-algorithm; 344 + snps,send_slope = <0x1000>; 345 + snps,idle_slope = <0x1000>; 346 + snps,high_credit = <0x3e800>; 347 + snps,low_credit = <0xffc18000>; 348 + }; 349 + }; 350 + }; 351 + 264 352 &i2c11 { 265 353 clock-frequency = <400000>; 266 354 pinctrl-0 = <&qup_i2c11_default>;