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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:

- support for nr_cpus= command line argument (maxcpus was previously
changed to allow secondary CPUs to be hot-plugged)

- ARM PMU interrupt handling fix

- fix potential TLB conflict in the hibernate code

- improved handling of EL1 instruction aborts (better error reporting)

- removal of useless jprobes code for stack saving/restoring

- defconfig updates

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: defconfig: enable CONFIG_LOCALVERSION_AUTO
arm64: defconfig: add options for virtualization and containers
arm64: hibernate: handle allocation failures
arm64: hibernate: avoid potential TLB conflict
arm64: Handle el1 synchronous instruction aborts cleanly
arm64: Remove stack duplicating code from jprobes
drivers/perf: arm-pmu: Fix handling of SPI lacking "interrupt-affinity" property
drivers/perf: arm-pmu: convert arm_pmu_mutex to spinlock
arm64: Support hard limit of cpu count by nr_cpus

+137 -87
+46 -7
arch/arm64/configs/defconfig
··· 1 - # CONFIG_LOCALVERSION_AUTO is not set 2 1 CONFIG_SYSVIPC=y 3 2 CONFIG_POSIX_MQUEUE=y 4 3 CONFIG_AUDIT=y ··· 14 15 CONFIG_LOG_BUF_SHIFT=14 15 16 CONFIG_MEMCG=y 16 17 CONFIG_MEMCG_SWAP=y 18 + CONFIG_BLK_CGROUP=y 19 + CONFIG_CGROUP_PIDS=y 17 20 CONFIG_CGROUP_HUGETLB=y 18 - # CONFIG_UTS_NS is not set 19 - # CONFIG_IPC_NS is not set 20 - # CONFIG_NET_NS is not set 21 + CONFIG_CPUSETS=y 22 + CONFIG_CGROUP_DEVICE=y 23 + CONFIG_CGROUP_CPUACCT=y 24 + CONFIG_CGROUP_PERF=y 25 + CONFIG_USER_NS=y 21 26 CONFIG_SCHED_AUTOGROUP=y 22 27 CONFIG_BLK_DEV_INITRD=y 23 28 CONFIG_KALLSYMS_ALL=y ··· 74 71 CONFIG_KSM=y 75 72 CONFIG_TRANSPARENT_HUGEPAGE=y 76 73 CONFIG_CMA=y 74 + CONFIG_SECCOMP=y 77 75 CONFIG_XEN=y 78 76 CONFIG_KEXEC=y 79 77 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ··· 88 84 CONFIG_PACKET=y 89 85 CONFIG_UNIX=y 90 86 CONFIG_INET=y 87 + CONFIG_IP_MULTICAST=y 91 88 CONFIG_IP_PNP=y 92 89 CONFIG_IP_PNP_DHCP=y 93 90 CONFIG_IP_PNP_BOOTP=y 94 - # CONFIG_IPV6 is not set 91 + CONFIG_IPV6=m 92 + CONFIG_NETFILTER=y 93 + CONFIG_NF_CONNTRACK=m 94 + CONFIG_NF_CONNTRACK_EVENTS=y 95 + CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m 96 + CONFIG_NETFILTER_XT_TARGET_LOG=m 97 + CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m 98 + CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m 99 + CONFIG_NF_CONNTRACK_IPV4=m 100 + CONFIG_IP_NF_IPTABLES=m 101 + CONFIG_IP_NF_FILTER=m 102 + CONFIG_IP_NF_TARGET_REJECT=m 103 + CONFIG_IP_NF_NAT=m 104 + CONFIG_IP_NF_TARGET_MASQUERADE=m 105 + CONFIG_IP_NF_MANGLE=m 106 + CONFIG_NF_CONNTRACK_IPV6=m 107 + CONFIG_IP6_NF_IPTABLES=m 108 + CONFIG_IP6_NF_FILTER=m 109 + CONFIG_IP6_NF_TARGET_REJECT=m 110 + CONFIG_IP6_NF_MANGLE=m 111 + CONFIG_IP6_NF_NAT=m 112 + CONFIG_IP6_NF_TARGET_MASQUERADE=m 113 + CONFIG_BRIDGE=m 114 + CONFIG_BRIDGE_VLAN_FILTERING=y 115 + CONFIG_VLAN_8021Q=m 116 + CONFIG_VLAN_8021Q_GVRP=y 117 + CONFIG_VLAN_8021Q_MVRP=y 95 118 CONFIG_BPF_JIT=y 96 119 CONFIG_CFG80211=m 97 120 CONFIG_MAC80211=m ··· 134 103 CONFIG_MTD_M25P80=y 135 104 CONFIG_MTD_SPI_NOR=y 136 105 CONFIG_BLK_DEV_LOOP=y 106 + CONFIG_BLK_DEV_NBD=m 137 107 CONFIG_VIRTIO_BLK=y 138 108 CONFIG_SRAM=y 139 109 # CONFIG_SCSI_PROC_FS is not set ··· 152 120 CONFIG_PATA_PLATFORM=y 153 121 CONFIG_PATA_OF_PLATFORM=y 154 122 CONFIG_NETDEVICES=y 123 + CONFIG_MACVLAN=m 124 + CONFIG_MACVTAP=m 155 125 CONFIG_TUN=y 126 + CONFIG_VETH=m 156 127 CONFIG_VIRTIO_NET=y 157 128 CONFIG_AMD_XGBE=y 158 129 CONFIG_NET_XGENE=y ··· 385 350 CONFIG_PWM_SAMSUNG=y 386 351 CONFIG_EXT2_FS=y 387 352 CONFIG_EXT3_FS=y 353 + CONFIG_EXT4_FS_POSIX_ACL=y 354 + CONFIG_BTRFS_FS=m 355 + CONFIG_BTRFS_FS_POSIX_ACL=y 388 356 CONFIG_FANOTIFY=y 389 357 CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y 390 358 CONFIG_QUOTA=y 391 359 CONFIG_AUTOFS4_FS=y 392 - CONFIG_FUSE_FS=y 393 - CONFIG_CUSE=y 360 + CONFIG_FUSE_FS=m 361 + CONFIG_CUSE=m 362 + CONFIG_OVERLAY_FS=m 394 363 CONFIG_VFAT_FS=y 395 364 CONFIG_TMPFS=y 396 365 CONFIG_HUGETLBFS=y
-2
arch/arm64/include/asm/kprobes.h
··· 22 22 23 23 #define __ARCH_WANT_KPROBES_INSN_SLOT 24 24 #define MAX_INSN_SIZE 1 25 - #define MAX_STACK_SIZE 128 26 25 27 26 #define flush_insn_slot(p) do { } while (0) 28 27 #define kretprobe_blacklist_size 0 ··· 46 47 struct prev_kprobe prev_kprobe; 47 48 struct kprobe_step_ctx ss_ctx; 48 49 struct pt_regs jprobe_saved_regs; 49 - char jprobes_stack[MAX_STACK_SIZE]; 50 50 }; 51 51 52 52 void arch_remove_kprobe(struct kprobe *);
+7
arch/arm64/kernel/entry.S
··· 353 353 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class 354 354 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1 355 355 b.eq el1_da 356 + cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1 357 + b.eq el1_ia 356 358 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap 357 359 b.eq el1_undef 358 360 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception ··· 366 364 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1 367 365 b.ge el1_dbg 368 366 b el1_inv 367 + 368 + el1_ia: 369 + /* 370 + * Fall through to the Data abort case 371 + */ 369 372 el1_da: 370 373 /* 371 374 * Data abort handling
+49 -33
arch/arm64/kernel/hibernate.c
··· 35 35 #include <asm/sections.h> 36 36 #include <asm/smp.h> 37 37 #include <asm/suspend.h> 38 + #include <asm/sysreg.h> 38 39 #include <asm/virt.h> 39 40 40 41 /* ··· 218 217 set_pte(pte, __pte(virt_to_phys((void *)dst) | 219 218 pgprot_val(PAGE_KERNEL_EXEC))); 220 219 221 - /* Load our new page tables */ 222 - asm volatile("msr ttbr0_el1, %0;" 223 - "isb;" 224 - "tlbi vmalle1is;" 225 - "dsb ish;" 226 - "isb" : : "r"(virt_to_phys(pgd))); 220 + /* 221 + * Load our new page tables. A strict BBM approach requires that we 222 + * ensure that TLBs are free of any entries that may overlap with the 223 + * global mappings we are about to install. 224 + * 225 + * For a real hibernate/resume cycle TTBR0 currently points to a zero 226 + * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI 227 + * runtime services), while for a userspace-driven test_resume cycle it 228 + * points to userspace page tables (and we must point it at a zero page 229 + * ourselves). Elsewhere we only (un)install the idmap with preemption 230 + * disabled, so T0SZ should be as required regardless. 231 + */ 232 + cpu_set_reserved_ttbr0(); 233 + local_flush_tlb_all(); 234 + write_sysreg(virt_to_phys(pgd), ttbr0_el1); 235 + isb(); 227 236 228 237 *phys_dst_addr = virt_to_phys((void *)dst); 229 238 ··· 405 394 void *, phys_addr_t, phys_addr_t); 406 395 407 396 /* 397 + * Restoring the memory image will overwrite the ttbr1 page tables. 398 + * Create a second copy of just the linear map, and use this when 399 + * restoring. 400 + */ 401 + tmp_pg_dir = (pgd_t *)get_safe_page(GFP_ATOMIC); 402 + if (!tmp_pg_dir) { 403 + pr_err("Failed to allocate memory for temporary page tables."); 404 + rc = -ENOMEM; 405 + goto out; 406 + } 407 + rc = copy_page_tables(tmp_pg_dir, PAGE_OFFSET, 0); 408 + if (rc) 409 + goto out; 410 + 411 + /* 412 + * Since we only copied the linear map, we need to find restore_pblist's 413 + * linear map address. 414 + */ 415 + lm_restore_pblist = LMADDR(restore_pblist); 416 + 417 + /* 418 + * We need a zero page that is zero before & after resume in order to 419 + * to break before make on the ttbr1 page tables. 420 + */ 421 + zero_page = (void *)get_safe_page(GFP_ATOMIC); 422 + if (!zero_page) { 423 + pr_err("Failed to allocate zero page."); 424 + rc = -ENOMEM; 425 + goto out; 426 + } 427 + 428 + /* 408 429 * Locate the exit code in the bottom-but-one page, so that *NULL 409 430 * still has disastrous affects. 410 431 */ ··· 462 419 __flush_dcache_area(hibernate_exit, exit_size); 463 420 464 421 /* 465 - * Restoring the memory image will overwrite the ttbr1 page tables. 466 - * Create a second copy of just the linear map, and use this when 467 - * restoring. 468 - */ 469 - tmp_pg_dir = (pgd_t *)get_safe_page(GFP_ATOMIC); 470 - if (!tmp_pg_dir) { 471 - pr_err("Failed to allocate memory for temporary page tables."); 472 - rc = -ENOMEM; 473 - goto out; 474 - } 475 - rc = copy_page_tables(tmp_pg_dir, PAGE_OFFSET, 0); 476 - if (rc) 477 - goto out; 478 - 479 - /* 480 - * Since we only copied the linear map, we need to find restore_pblist's 481 - * linear map address. 482 - */ 483 - lm_restore_pblist = LMADDR(restore_pblist); 484 - 485 - /* 486 422 * KASLR will cause the el2 vectors to be in a different location in 487 423 * the resumed kernel. Load hibernate's temporary copy into el2. 488 424 * ··· 474 452 475 453 __hyp_set_vectors(el2_vectors); 476 454 } 477 - 478 - /* 479 - * We need a zero page that is zero before & after resume in order to 480 - * to break before make on the ttbr1 page tables. 481 - */ 482 - zero_page = (void *)get_safe_page(GFP_ATOMIC); 483 455 484 456 hibernate_exit(virt_to_phys(tmp_pg_dir), resume_hdr.ttbr1_el1, 485 457 resume_hdr.reenter_kernel, lm_restore_pblist,
+5 -26
arch/arm64/kernel/probes/kprobes.c
··· 41 41 static void __kprobes 42 42 post_kprobe_handler(struct kprobe_ctlblk *, struct pt_regs *); 43 43 44 - static inline unsigned long min_stack_size(unsigned long addr) 45 - { 46 - unsigned long size; 47 - 48 - if (on_irq_stack(addr, raw_smp_processor_id())) 49 - size = IRQ_STACK_PTR(raw_smp_processor_id()) - addr; 50 - else 51 - size = (unsigned long)current_thread_info() + THREAD_START_SP - addr; 52 - 53 - return min(size, FIELD_SIZEOF(struct kprobe_ctlblk, jprobes_stack)); 54 - } 55 - 56 44 static void __kprobes arch_prepare_ss_slot(struct kprobe *p) 57 45 { 58 46 /* prepare insn slot */ ··· 477 489 { 478 490 struct jprobe *jp = container_of(p, struct jprobe, kp); 479 491 struct kprobe_ctlblk *kcb = get_kprobe_ctlblk(); 480 - long stack_ptr = kernel_stack_pointer(regs); 481 492 482 493 kcb->jprobe_saved_regs = *regs; 483 494 /* 484 - * As Linus pointed out, gcc assumes that the callee 485 - * owns the argument space and could overwrite it, e.g. 486 - * tailcall optimization. So, to be absolutely safe 487 - * we also save and restore enough stack bytes to cover 488 - * the argument area. 495 + * Since we can't be sure where in the stack frame "stacked" 496 + * pass-by-value arguments are stored we just don't try to 497 + * duplicate any of the stack. Do not use jprobes on functions that 498 + * use more than 64 bytes (after padding each to an 8 byte boundary) 499 + * of arguments, or pass individual arguments larger than 16 bytes. 489 500 */ 490 - kasan_disable_current(); 491 - memcpy(kcb->jprobes_stack, (void *)stack_ptr, 492 - min_stack_size(stack_ptr)); 493 - kasan_enable_current(); 494 501 495 502 instruction_pointer_set(regs, (unsigned long) jp->entry); 496 503 preempt_disable(); ··· 537 554 } 538 555 unpause_graph_tracing(); 539 556 *regs = kcb->jprobe_saved_regs; 540 - kasan_disable_current(); 541 - memcpy((void *)stack_addr, kcb->jprobes_stack, 542 - min_stack_size(stack_addr)); 543 - kasan_enable_current(); 544 557 preempt_enable_no_resched(); 545 558 return 1; 546 559 }
+4 -4
arch/arm64/kernel/smp.c
··· 661 661 acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 662 662 acpi_parse_gic_cpu_interface, 0); 663 663 664 - if (cpu_count > NR_CPUS) 665 - pr_warn("no. of cores (%d) greater than configured maximum of %d - clipping\n", 666 - cpu_count, NR_CPUS); 664 + if (cpu_count > nr_cpu_ids) 665 + pr_warn("Number of cores (%d) exceeds configured maximum of %d - clipping\n", 666 + cpu_count, nr_cpu_ids); 667 667 668 668 if (!bootcpu_valid) { 669 669 pr_err("missing boot CPU MPIDR, not enabling secondaries\n"); ··· 677 677 * with entries in cpu_logical_map while initializing the cpus. 678 678 * If the cpu set-up fails, invalidate the cpu_logical_map entry. 679 679 */ 680 - for (i = 1; i < NR_CPUS; i++) { 680 + for (i = 1; i < nr_cpu_ids; i++) { 681 681 if (cpu_logical_map(i) != INVALID_HWID) { 682 682 if (smp_cpu_setup(i)) 683 683 cpu_logical_map(i) = INVALID_HWID;
+12 -2
arch/arm64/mm/fault.c
··· 153 153 } 154 154 #endif 155 155 156 + static bool is_el1_instruction_abort(unsigned int esr) 157 + { 158 + return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_CUR; 159 + } 160 + 156 161 /* 157 162 * The kernel tried to access some page that wasn't present. 158 163 */ ··· 166 161 { 167 162 /* 168 163 * Are we prepared to handle this kernel fault? 164 + * We are almost certainly not prepared to handle instruction faults. 169 165 */ 170 - if (fixup_exception(regs)) 166 + if (!is_el1_instruction_abort(esr) && fixup_exception(regs)) 171 167 return; 172 168 173 169 /* ··· 273 267 unsigned int ec = ESR_ELx_EC(esr); 274 268 unsigned int fsc_type = esr & ESR_ELx_FSC_TYPE; 275 269 276 - return (ec == ESR_ELx_EC_DABT_CUR && fsc_type == ESR_ELx_FSC_PERM); 270 + return (ec == ESR_ELx_EC_DABT_CUR && fsc_type == ESR_ELx_FSC_PERM) || 271 + (ec == ESR_ELx_EC_IABT_CUR && fsc_type == ESR_ELx_FSC_PERM); 277 272 } 278 273 279 274 static bool is_el0_instruction_abort(unsigned int esr) ··· 318 311 /* regs->orig_addr_limit may be 0 if we entered from EL0 */ 319 312 if (regs->orig_addr_limit == KERNEL_DS) 320 313 die("Accessing user space memory with fs=KERNEL_DS", regs, esr); 314 + 315 + if (is_el1_instruction_abort(esr)) 316 + die("Attempting to execute userspace memory", regs, esr); 321 317 322 318 if (!search_exception_tables(regs->pc)) 323 319 die("Accessing user space memory outside uaccess.h routines", regs, esr);
+14 -13
drivers/perf/arm_pmu.c
··· 688 688 return 0; 689 689 } 690 690 691 - static DEFINE_MUTEX(arm_pmu_mutex); 691 + static DEFINE_SPINLOCK(arm_pmu_lock); 692 692 static LIST_HEAD(arm_pmu_list); 693 693 694 694 /* ··· 701 701 { 702 702 struct arm_pmu *pmu; 703 703 704 - mutex_lock(&arm_pmu_mutex); 704 + spin_lock(&arm_pmu_lock); 705 705 list_for_each_entry(pmu, &arm_pmu_list, entry) { 706 706 707 707 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus)) ··· 709 709 if (pmu->reset) 710 710 pmu->reset(pmu); 711 711 } 712 - mutex_unlock(&arm_pmu_mutex); 712 + spin_unlock(&arm_pmu_lock); 713 713 return 0; 714 714 } 715 715 ··· 821 821 if (!cpu_hw_events) 822 822 return -ENOMEM; 823 823 824 - mutex_lock(&arm_pmu_mutex); 824 + spin_lock(&arm_pmu_lock); 825 825 list_add_tail(&cpu_pmu->entry, &arm_pmu_list); 826 - mutex_unlock(&arm_pmu_mutex); 826 + spin_unlock(&arm_pmu_lock); 827 827 828 828 err = cpu_pm_pmu_register(cpu_pmu); 829 829 if (err) ··· 859 859 return 0; 860 860 861 861 out_unregister: 862 - mutex_lock(&arm_pmu_mutex); 862 + spin_lock(&arm_pmu_lock); 863 863 list_del(&cpu_pmu->entry); 864 - mutex_unlock(&arm_pmu_mutex); 864 + spin_unlock(&arm_pmu_lock); 865 865 free_percpu(cpu_hw_events); 866 866 return err; 867 867 } ··· 869 869 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu) 870 870 { 871 871 cpu_pm_pmu_unregister(cpu_pmu); 872 - mutex_lock(&arm_pmu_mutex); 872 + spin_lock(&arm_pmu_lock); 873 873 list_del(&cpu_pmu->entry); 874 - mutex_unlock(&arm_pmu_mutex); 874 + spin_unlock(&arm_pmu_lock); 875 875 free_percpu(cpu_pmu->hw_events); 876 876 } 877 877 ··· 967 967 968 968 /* If we didn't manage to parse anything, try the interrupt affinity */ 969 969 if (cpumask_weight(&pmu->supported_cpus) == 0) { 970 - if (!using_spi) { 971 - /* If using PPIs, check the affinity of the partition */ 972 - int ret, irq; 970 + int irq = platform_get_irq(pdev, 0); 973 971 974 - irq = platform_get_irq(pdev, 0); 972 + if (irq_is_percpu(irq)) { 973 + /* If using PPIs, check the affinity of the partition */ 974 + int ret; 975 + 975 976 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); 976 977 if (ret) { 977 978 kfree(irqs);