Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'linux-watchdog-6.7-rc1' of git://www.linux-watchdog.org/linux-watchdog
Pull watchdog updates from Wim Van Sebroeck:
- add support for Amlogic C3 and S4 SoCs
- add IT8613 ID
- add MSM8226 and MSM8974 compatibles
- other small fixes and improvements
* tag 'linux-watchdog-6.7-rc1' of git://www.linux-watchdog.org/linux-watchdog: (24 commits)
dt-bindings: watchdog: Add support for Amlogic C3 and S4 SoCs
watchdog: mlx-wdt: Parameter desctiption warning fix
watchdog: aspeed: Add support for aspeed,reset-mask DT property
dt-bindings: watchdog: aspeed-wdt: Add aspeed,reset-mask property
watchdog: apple: Deactivate on suspend
dt-bindings: watchdog: qcom-wdt: Add MSM8226 and MSM8974 compatibles
dt-bindings: watchdog: fsl-imx7ulp-wdt: Add 'fsl,ext-reset-output'
wdog: imx7ulp: Enable wdog int_en bit for watchdog any reset
drivers: watchdog: marvell_gti: Program the max_hw_heartbeat_ms
drivers: watchdog: marvell_gti: fix zero pretimeout handling
watchdog: marvell_gti: Replace of_platform.h with explicit includes
watchdog: imx_sc_wdt: continue if the wdog already enabled
watchdog: st_lpc: Use device_get_match_data()
watchdog: wdat_wdt: Add timeout value as a param in ping method
watchdog: gpio_wdt: Make use of device properties
sbsa_gwdt: Calculate timeout with 64-bit math
watchdog: ixp4xx: Make sure restart always works
watchdog: it87_wdt: add IT8613 ID
watchdog: marvell_gti_wdt: Fix error code in probe()
Watchdog: marvell_gti_wdt: Remove redundant dev_err_probe() for platform_get_irq()
...
+248
-83
+9
-3
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
+9
-3
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
···
15
15
16
16
properties:
17
17
compatible:
18
-
enum:
19
-
- amlogic,meson-gxbb-wdt
20
-
- amlogic,t7-wdt
18
+
oneOf:
19
+
- enum:
20
+
- amlogic,meson-gxbb-wdt
21
+
- amlogic,t7-wdt
22
+
- items:
23
+
- enum:
24
+
- amlogic,c3-wdt
25
+
- amlogic,s4-wdt
26
+
- const: amlogic,t7-wdt
21
27
22
28
reg:
23
29
maxItems: 1
+17
-1
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
+17
-1
Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
···
47
47
is configured as push-pull, then set the pulse
48
48
polarity to active-high. The default is active-low.
49
49
50
-
Example:
50
+
Optional properties for AST2500- and AST2600-compatible watchdogs:
51
+
- aspeed,reset-mask: A bitmask indicating which peripherals will be reset if
52
+
the watchdog timer expires. On AST2500 this should be a
53
+
single word defined using the AST2500_WDT_RESET_* macros;
54
+
on AST2600 this should be a two-word array with the first
55
+
word defined using the AST2600_WDT_RESET1_* macros and the
56
+
second word defined using the AST2600_WDT_RESET2_* macros.
57
+
58
+
Examples:
51
59
52
60
wdt1: watchdog@1e785000 {
53
61
compatible = "aspeed,ast2400-wdt";
54
62
reg = <0x1e785000 0x1c>;
55
63
aspeed,reset-type = "system";
56
64
aspeed,external-signal;
65
+
};
66
+
67
+
#include <dt-bindings/watchdog/aspeed-wdt.h>
68
+
wdt2: watchdog@1e785040 {
69
+
compatible = "aspeed,ast2600-wdt";
70
+
reg = <0x1e785040 0x40>;
71
+
aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT
72
+
(AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>;
57
73
};
+5
Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
+5
Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml
+2
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+2
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+25
drivers/watchdog/apple_wdt.c
+25
drivers/watchdog/apple_wdt.c
···
173
173
if (!wdt->clk_rate)
174
174
return -EINVAL;
175
175
176
+
platform_set_drvdata(pdev, wdt);
177
+
176
178
wdt->wdd.ops = &apple_wdt_ops;
177
179
wdt->wdd.info = &apple_wdt_info;
178
180
wdt->wdd.max_timeout = U32_MAX / wdt->clk_rate;
···
192
190
return devm_watchdog_register_device(dev, &wdt->wdd);
193
191
}
194
192
193
+
static int apple_wdt_resume(struct device *dev)
194
+
{
195
+
struct apple_wdt *wdt = dev_get_drvdata(dev);
196
+
197
+
if (watchdog_active(&wdt->wdd) || watchdog_hw_running(&wdt->wdd))
198
+
apple_wdt_start(&wdt->wdd);
199
+
200
+
return 0;
201
+
}
202
+
203
+
static int apple_wdt_suspend(struct device *dev)
204
+
{
205
+
struct apple_wdt *wdt = dev_get_drvdata(dev);
206
+
207
+
if (watchdog_active(&wdt->wdd) || watchdog_hw_running(&wdt->wdd))
208
+
apple_wdt_stop(&wdt->wdd);
209
+
210
+
return 0;
211
+
}
212
+
213
+
static DEFINE_SIMPLE_DEV_PM_OPS(apple_wdt_pm_ops, apple_wdt_suspend, apple_wdt_resume);
214
+
195
215
static const struct of_device_id apple_wdt_of_match[] = {
196
216
{ .compatible = "apple,wdt" },
197
217
{},
···
224
200
.driver = {
225
201
.name = "apple-watchdog",
226
202
.of_match_table = apple_wdt_of_match,
203
+
.pm = pm_sleep_ptr(&apple_wdt_pm_ops),
227
204
},
228
205
.probe = apple_wdt_probe,
229
206
};
+11
drivers/watchdog/aspeed_wdt.c
+11
drivers/watchdog/aspeed_wdt.c
···
79
79
#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
80
80
#define WDT_CLEAR_TIMEOUT_STATUS 0x14
81
81
#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
82
+
#define WDT_RESET_MASK1 0x1c
83
+
#define WDT_RESET_MASK2 0x20
82
84
83
85
/*
84
86
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
···
404
402
405
403
if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
406
404
(of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
405
+
u32 reset_mask[2];
406
+
size_t nrstmask = of_device_is_compatible(np, "aspeed,ast2600-wdt") ? 2 : 1;
407
407
u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
408
408
409
409
reg &= wdt->cfg->ext_pulse_width_mask;
···
423
419
reg |= WDT_OPEN_DRAIN_MAGIC;
424
420
425
421
writel(reg, wdt->base + WDT_RESET_WIDTH);
422
+
423
+
ret = of_property_read_u32_array(np, "aspeed,reset-mask", reset_mask, nrstmask);
424
+
if (!ret) {
425
+
writel(reset_mask[0], wdt->base + WDT_RESET_MASK1);
426
+
if (nrstmask > 1)
427
+
writel(reset_mask[1], wdt->base + WDT_RESET_MASK2);
428
+
}
426
429
}
427
430
428
431
if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
+5
-15
drivers/watchdog/at91sam9_wdt.c
+5
-15
drivers/watchdog/at91sam9_wdt.c
···
348
348
if (IS_ERR(wdt->base))
349
349
return PTR_ERR(wdt->base);
350
350
351
-
wdt->sclk = devm_clk_get(&pdev->dev, NULL);
352
-
if (IS_ERR(wdt->sclk))
353
-
return PTR_ERR(wdt->sclk);
354
-
355
-
err = clk_prepare_enable(wdt->sclk);
356
-
if (err) {
351
+
wdt->sclk = devm_clk_get_enabled(&pdev->dev, NULL);
352
+
if (IS_ERR(wdt->sclk)) {
357
353
dev_err(&pdev->dev, "Could not enable slow clock\n");
358
-
return err;
354
+
return PTR_ERR(wdt->sclk);
359
355
}
360
356
361
357
if (pdev->dev.of_node) {
362
358
err = of_at91wdt_init(pdev->dev.of_node, wdt);
363
359
if (err)
364
-
goto err_clk;
360
+
return err;
365
361
}
366
362
367
363
err = at91_wdt_init(pdev, wdt);
368
364
if (err)
369
-
goto err_clk;
365
+
return err;
370
366
371
367
platform_set_drvdata(pdev, wdt);
372
368
···
370
374
wdt->wdd.timeout, wdt->nowayout);
371
375
372
376
return 0;
373
-
374
-
err_clk:
375
-
clk_disable_unprepare(wdt->sclk);
376
-
377
-
return err;
378
377
}
379
378
380
379
static int __exit at91wdt_remove(struct platform_device *pdev)
···
379
388
380
389
pr_warn("I quit now, hardware will probably reboot!\n");
381
390
del_timer(&wdt->timer);
382
-
clk_disable_unprepare(wdt->sclk);
383
391
384
392
return 0;
385
393
}
+4
-15
drivers/watchdog/ath79_wdt.c
+4
-15
drivers/watchdog/ath79_wdt.c
···
257
257
if (IS_ERR(wdt_base))
258
258
return PTR_ERR(wdt_base);
259
259
260
-
wdt_clk = devm_clk_get(&pdev->dev, "wdt");
260
+
wdt_clk = devm_clk_get_enabled(&pdev->dev, "wdt");
261
261
if (IS_ERR(wdt_clk))
262
262
return PTR_ERR(wdt_clk);
263
263
264
-
err = clk_prepare_enable(wdt_clk);
265
-
if (err)
266
-
return err;
267
-
268
264
wdt_freq = clk_get_rate(wdt_clk);
269
-
if (!wdt_freq) {
270
-
err = -EINVAL;
271
-
goto err_clk_disable;
272
-
}
265
+
if (!wdt_freq)
266
+
return -EINVAL;
273
267
274
268
max_timeout = (0xfffffffful / wdt_freq);
275
269
if (timeout < 1 || timeout > max_timeout) {
···
280
286
if (err) {
281
287
dev_err(&pdev->dev,
282
288
"unable to register misc device, err=%d\n", err);
283
-
goto err_clk_disable;
289
+
return err;
284
290
}
285
291
286
292
return 0;
287
-
288
-
err_clk_disable:
289
-
clk_disable_unprepare(wdt_clk);
290
-
return err;
291
293
}
292
294
293
295
static void ath79_wdt_remove(struct platform_device *pdev)
294
296
{
295
297
misc_deregister(&ath79_wdt_miscdev);
296
-
clk_disable_unprepare(wdt_clk);
297
298
}
298
299
299
300
static void ath79_wdt_shutdown(struct platform_device *pdev)
+7
-9
drivers/watchdog/gpio_wdt.c
+7
-9
drivers/watchdog/gpio_wdt.c
···
5
5
* Author: 2013, Alexander Shiyan <shc_work@mail.ru>
6
6
*/
7
7
8
-
#include <linux/err.h>
9
8
#include <linux/delay.h>
10
-
#include <linux/module.h>
9
+
#include <linux/err.h>
11
10
#include <linux/gpio/consumer.h>
12
-
#include <linux/of.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
13
13
#include <linux/platform_device.h>
14
+
#include <linux/property.h>
14
15
#include <linux/watchdog.h>
15
16
16
17
static bool nowayout = WATCHDOG_NOWAYOUT;
···
107
106
static int gpio_wdt_probe(struct platform_device *pdev)
108
107
{
109
108
struct device *dev = &pdev->dev;
110
-
struct device_node *np = dev->of_node;
111
109
struct gpio_wdt_priv *priv;
112
110
enum gpiod_flags gflags;
113
111
unsigned int hw_margin;
···
119
119
120
120
platform_set_drvdata(pdev, priv);
121
121
122
-
ret = of_property_read_string(np, "hw_algo", &algo);
122
+
ret = device_property_read_string(dev, "hw_algo", &algo);
123
123
if (ret)
124
124
return ret;
125
125
if (!strcmp(algo, "toggle")) {
···
136
136
if (IS_ERR(priv->gpiod))
137
137
return PTR_ERR(priv->gpiod);
138
138
139
-
ret = of_property_read_u32(np,
140
-
"hw_margin_ms", &hw_margin);
139
+
ret = device_property_read_u32(dev, "hw_margin_ms", &hw_margin);
141
140
if (ret)
142
141
return ret;
143
142
/* Disallow values lower than 2 and higher than 65535 ms */
144
143
if (hw_margin < 2 || hw_margin > 65535)
145
144
return -EINVAL;
146
145
147
-
priv->always_running = of_property_read_bool(np,
148
-
"always-running");
146
+
priv->always_running = device_property_read_bool(dev, "always-running");
149
147
150
148
watchdog_set_drvdata(&priv->wdd, priv);
151
149
+8
drivers/watchdog/imx7ulp_wdt.c
+8
drivers/watchdog/imx7ulp_wdt.c
···
23
23
#define LPO_CLK_SHIFT 8
24
24
#define WDOG_CS_CLK (LPO_CLK << LPO_CLK_SHIFT)
25
25
#define WDOG_CS_EN BIT(7)
26
+
#define WDOG_CS_INT_EN BIT(6)
26
27
#define WDOG_CS_UPDATE BIT(5)
27
28
#define WDOG_CS_WAIT BIT(1)
28
29
#define WDOG_CS_STOP BIT(0)
···
63
62
void __iomem *base;
64
63
struct clk *clk;
65
64
bool post_rcs_wait;
65
+
bool ext_reset;
66
66
const struct imx_wdt_hw_feature *hw;
67
67
};
68
68
···
287
285
if (wdt->hw->prescaler_enable)
288
286
val |= WDOG_CS_PRES;
289
287
288
+
if (wdt->ext_reset)
289
+
val |= WDOG_CS_INT_EN;
290
+
290
291
do {
291
292
ret = _imx7ulp_wdt_init(wdt, timeout, val);
292
293
toval = readl(wdt->base + WDOG_TOVAL);
···
325
320
dev_err(dev, "Failed to get watchdog clock\n");
326
321
return PTR_ERR(imx7ulp_wdt->clk);
327
322
}
323
+
324
+
/* The WDOG may need to do external reset through dedicated pin */
325
+
imx7ulp_wdt->ext_reset = of_property_read_bool(dev->of_node, "fsl,ext-reset-output");
328
326
329
327
imx7ulp_wdt->post_rcs_wait = true;
330
328
if (of_device_is_compatible(dev->of_node,
+4
-1
drivers/watchdog/imx_sc_wdt.c
+4
-1
drivers/watchdog/imx_sc_wdt.c
···
34
34
35
35
#define SC_IRQ_WDOG 1
36
36
#define SC_IRQ_GROUP_WDOG 1
37
+
#define SC_TIMER_ERR_BUSY 10
37
38
38
39
static bool nowayout = WATCHDOG_NOWAYOUT;
39
40
module_param(nowayout, bool, 0000);
···
62
61
63
62
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_START_WDOG,
64
63
0, 0, 0, 0, 0, 0, &res);
65
-
if (res.a0)
64
+
65
+
/* Ignore if already enabled(SC_TIMER_ERR_BUSY) */
66
+
if (res.a0 && res.a0 != SC_TIMER_ERR_BUSY)
66
67
return -EACCES;
67
68
68
69
arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_SET_WDOG_ACT,
+5
-3
drivers/watchdog/it87_wdt.c
+5
-3
drivers/watchdog/it87_wdt.c
···
13
13
* http://www.ite.com.tw/
14
14
*
15
15
* Support of the watchdog timers, which are available on
16
-
* IT8607, IT8620, IT8622, IT8625, IT8628, IT8655, IT8665, IT8686,
17
-
* IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726, IT8728,
18
-
* IT8772, IT8783 and IT8784.
16
+
* IT8607, IT8613, IT8620, IT8622, IT8625, IT8628, IT8655, IT8665,
17
+
* IT8686, IT8702, IT8712, IT8716, IT8718, IT8720, IT8721, IT8726,
18
+
* IT8728, IT8772, IT8783 and IT8784.
19
19
*/
20
20
21
21
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
···
50
50
/* Chip Id numbers */
51
51
#define NO_DEV_ID 0xffff
52
52
#define IT8607_ID 0x8607
53
+
#define IT8613_ID 0x8613
53
54
#define IT8620_ID 0x8620
54
55
#define IT8622_ID 0x8622
55
56
#define IT8625_ID 0x8625
···
278
277
max_units = 65535;
279
278
break;
280
279
case IT8607_ID:
280
+
case IT8613_ID:
281
281
case IT8620_ID:
282
282
case IT8622_ID:
283
283
case IT8625_ID:
+25
-3
drivers/watchdog/ixp4xx_wdt.c
+25
-3
drivers/watchdog/ixp4xx_wdt.c
···
105
105
.owner = THIS_MODULE,
106
106
};
107
107
108
+
/*
109
+
* The A0 version of the IXP422 had a bug in the watchdog making
110
+
* is useless, but we still need to use it to restart the system
111
+
* as it is the only way, so in this special case we register a
112
+
* "dummy" watchdog that doesn't really work, but will support
113
+
* the restart operation.
114
+
*/
115
+
static int ixp4xx_wdt_dummy(struct watchdog_device *wdd)
116
+
{
117
+
return 0;
118
+
}
119
+
120
+
static const struct watchdog_ops ixp4xx_wdt_restart_only_ops = {
121
+
.start = ixp4xx_wdt_dummy,
122
+
.stop = ixp4xx_wdt_dummy,
123
+
.restart = ixp4xx_wdt_restart,
124
+
.owner = THIS_MODULE,
125
+
};
126
+
108
127
static const struct watchdog_info ixp4xx_wdt_info = {
109
128
.options = WDIOF_KEEPALIVEPING
110
129
| WDIOF_MAGICCLOSE
···
133
114
134
115
static int ixp4xx_wdt_probe(struct platform_device *pdev)
135
116
{
117
+
static const struct watchdog_ops *iwdt_ops;
136
118
struct device *dev = &pdev->dev;
137
119
struct ixp4xx_wdt *iwdt;
138
120
struct clk *clk;
139
121
int ret;
140
122
141
123
if (!(read_cpuid_id() & 0xf) && !cpu_is_ixp46x()) {
142
-
dev_err(dev, "Rev. A0 IXP42x CPU detected - watchdog disabled\n");
143
-
return -ENODEV;
124
+
dev_info(dev, "Rev. A0 IXP42x CPU detected - only restart supported\n");
125
+
iwdt_ops = &ixp4xx_wdt_restart_only_ops;
126
+
} else {
127
+
iwdt_ops = &ixp4xx_wdt_ops;
144
128
}
145
129
146
130
iwdt = devm_kzalloc(dev, sizeof(*iwdt), GFP_KERNEL);
···
163
141
iwdt->rate = IXP4XX_TIMER_FREQ;
164
142
165
143
iwdt->wdd.info = &ixp4xx_wdt_info;
166
-
iwdt->wdd.ops = &ixp4xx_wdt_ops;
144
+
iwdt->wdd.ops = iwdt_ops;
167
145
iwdt->wdd.min_timeout = 1;
168
146
iwdt->wdd.max_timeout = U32_MAX / iwdt->rate;
169
147
iwdt->wdd.parent = dev;
+11
-3
drivers/watchdog/marvell_gti_wdt.c
+11
-3
drivers/watchdog/marvell_gti_wdt.c
···
8
8
#include <linux/interrupt.h>
9
9
#include <linux/io.h>
10
10
#include <linux/module.h>
11
-
#include <linux/of_platform.h>
12
11
#include <linux/platform_device.h>
12
+
#include <linux/of.h>
13
13
#include <linux/watchdog.h>
14
14
15
15
/*
···
190
190
struct gti_wdt_priv *priv = watchdog_get_drvdata(wdev);
191
191
struct watchdog_device *wdog_dev = &priv->wdev;
192
192
193
+
if (!timeout) {
194
+
/* Disable Interrupt */
195
+
writeq(GTI_CWD_INT_ENA_CLR_VAL(priv->wdt_timer_idx),
196
+
priv->base + GTI_CWD_INT_ENA_CLR);
197
+
return 0;
198
+
}
199
+
193
200
/* pretimeout should 1/3 of max_timeout */
194
201
if (timeout * 3 <= wdog_dev->max_timeout)
195
202
return gti_wdt_settimeout(wdev, timeout * 3);
···
278
271
&wdt_idx);
279
272
if (!err) {
280
273
if (wdt_idx >= priv->data->gti_num_timers)
281
-
return dev_err_probe(&pdev->dev, err,
274
+
return dev_err_probe(&pdev->dev, -EINVAL,
282
275
"GTI wdog timer index not valid");
283
276
284
277
priv->wdt_timer_idx = wdt_idx;
···
299
292
300
293
/* Maximum timeout is 3 times the pretimeout */
301
294
wdog_dev->max_timeout = max_pretimeout * 3;
295
+
wdog_dev->max_hw_heartbeat_ms = max_pretimeout * 1000;
302
296
/* Minimum first timeout (pretimeout) is 1, so min_timeout as 3 */
303
297
wdog_dev->min_timeout = 3;
304
298
wdog_dev->timeout = wdog_dev->pretimeout;
···
316
308
317
309
irq = platform_get_irq(pdev, 0);
318
310
if (irq < 0)
319
-
return dev_err_probe(&pdev->dev, irq, "IRQ resource not found\n");
311
+
return irq;
320
312
321
313
err = devm_request_irq(dev, irq, gti_wdt_interrupt, 0,
322
314
pdev->name, &priv->wdev);
+1
drivers/watchdog/mlx_wdt.c
+1
drivers/watchdog/mlx_wdt.c
···
39
39
* @tleft_idx: index for direct access to time left register;
40
40
* @ping_idx: index for direct access to ping register;
41
41
* @reset_idx: index for direct access to reset cause register;
42
+
* @regmap_val_sz: size of value in register map;
42
43
* @wd_type: watchdog HW type;
43
44
*/
44
45
struct mlxreg_wdt {
+10
-3
drivers/watchdog/of_xilinx_wdt.c
+10
-3
drivers/watchdog/of_xilinx_wdt.c
···
187
187
188
188
watchdog_set_nowayout(xilinx_wdt_wdd, enable_once);
189
189
190
-
xdev->clk = devm_clk_get_enabled(dev, NULL);
190
+
xdev->clk = devm_clk_get_prepared(dev, NULL);
191
191
if (IS_ERR(xdev->clk)) {
192
192
if (PTR_ERR(xdev->clk) != -ENOENT)
193
193
return PTR_ERR(xdev->clk);
···
218
218
spin_lock_init(&xdev->spinlock);
219
219
watchdog_set_drvdata(xilinx_wdt_wdd, xdev);
220
220
221
+
rc = clk_enable(xdev->clk);
222
+
if (rc) {
223
+
dev_err(dev, "unable to enable clock\n");
224
+
return rc;
225
+
}
226
+
221
227
rc = xwdt_selftest(xdev);
222
228
if (rc == XWT_TIMER_FAILED) {
223
229
dev_err(dev, "SelfTest routine error\n");
230
+
clk_disable(xdev->clk);
224
231
return rc;
225
232
}
233
+
234
+
clk_disable(xdev->clk);
226
235
227
236
rc = devm_watchdog_register_device(dev, xilinx_wdt_wdd);
228
237
if (rc)
229
238
return rc;
230
-
231
-
clk_disable(xdev->clk);
232
239
233
240
dev_info(dev, "Xilinx Watchdog Timer with timeout %ds\n",
234
241
xilinx_wdt_wdd->timeout);
+2
-2
drivers/watchdog/sbsa_gwdt.c
+2
-2
drivers/watchdog/sbsa_gwdt.c
···
152
152
timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000);
153
153
154
154
if (action)
155
-
sbsa_gwdt_reg_write(gwdt->clk * timeout, gwdt);
155
+
sbsa_gwdt_reg_write((u64)gwdt->clk * timeout, gwdt);
156
156
else
157
157
/*
158
158
* In the single stage mode, The first signal (WS0) is ignored,
159
159
* the timeout is (WOR * 2), so the WOR should be configured
160
160
* to half value of timeout.
161
161
*/
162
-
sbsa_gwdt_reg_write(gwdt->clk / 2 * timeout, gwdt);
162
+
sbsa_gwdt_reg_write(((u64)gwdt->clk / 2) * timeout, gwdt);
163
163
164
164
return 0;
165
165
}
+2
-9
drivers/watchdog/st_lpc_wdt.c
+2
-9
drivers/watchdog/st_lpc_wdt.c
···
15
15
#include <linux/mfd/syscon.h>
16
16
#include <linux/module.h>
17
17
#include <linux/of.h>
18
-
#include <linux/of_platform.h>
19
18
#include <linux/platform_device.h>
20
19
#include <linux/regmap.h>
21
20
#include <linux/watchdog.h>
···
41
42
void __iomem *base;
42
43
struct device *dev;
43
44
struct regmap *regmap;
44
-
struct st_wdog_syscfg *syscfg;
45
+
const struct st_wdog_syscfg *syscfg;
45
46
struct clk *clk;
46
47
unsigned long clkrate;
47
48
bool warm_reset;
···
149
150
static int st_wdog_probe(struct platform_device *pdev)
150
151
{
151
152
struct device *dev = &pdev->dev;
152
-
const struct of_device_id *match;
153
153
struct device_node *np = dev->of_node;
154
154
struct st_wdog *st_wdog;
155
155
struct regmap *regmap;
···
171
173
if (!st_wdog)
172
174
return -ENOMEM;
173
175
174
-
match = of_match_device(st_wdog_match, dev);
175
-
if (!match) {
176
-
dev_err(dev, "Couldn't match device\n");
177
-
return -ENODEV;
178
-
}
179
-
st_wdog->syscfg = (struct st_wdog_syscfg *)match->data;
176
+
st_wdog->syscfg = (struct st_wdog_syscfg *)device_get_match_data(dev);
180
177
181
178
base = devm_platform_ioremap_resource(pdev, 0);
182
179
if (IS_ERR(base))
+2
-15
drivers/watchdog/sunplus_wdt.c
+2
-15
drivers/watchdog/sunplus_wdt.c
···
136
136
.restart = sp_wdt_restart,
137
137
};
138
138
139
-
static void sp_clk_disable_unprepare(void *data)
140
-
{
141
-
clk_disable_unprepare(data);
142
-
}
143
-
144
139
static void sp_reset_control_assert(void *data)
145
140
{
146
141
reset_control_assert(data);
···
151
156
if (!priv)
152
157
return -ENOMEM;
153
158
154
-
priv->clk = devm_clk_get(dev, NULL);
159
+
priv->clk = devm_clk_get_enabled(dev, NULL);
155
160
if (IS_ERR(priv->clk))
156
-
return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get clock\n");
157
-
158
-
ret = clk_prepare_enable(priv->clk);
159
-
if (ret)
160
-
return dev_err_probe(dev, ret, "Failed to enable clock\n");
161
-
162
-
ret = devm_add_action_or_reset(dev, sp_clk_disable_unprepare, priv->clk);
163
-
if (ret)
164
-
return ret;
161
+
return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to enable clock\n");
165
162
166
163
/* The timer and watchdog shared the STC reset */
167
164
priv->rstc = devm_reset_control_get_shared(dev, NULL);
+1
-1
drivers/watchdog/wdat_wdt.c
+1
-1
drivers/watchdog/wdat_wdt.c
···
269
269
270
270
static int wdat_wdt_ping(struct watchdog_device *wdd)
271
271
{
272
-
return wdat_wdt_run_action(to_wdat_wdt(wdd), ACPI_WDAT_RESET, 0, NULL);
272
+
return wdat_wdt_run_action(to_wdat_wdt(wdd), ACPI_WDAT_RESET, wdd->timeout, NULL);
273
273
}
274
274
275
275
static int wdat_wdt_set_timeout(struct watchdog_device *wdd,
+92
include/dt-bindings/watchdog/aspeed-wdt.h
+92
include/dt-bindings/watchdog/aspeed-wdt.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
3
+
#ifndef DT_BINDINGS_ASPEED_WDT_H
4
+
#define DT_BINDINGS_ASPEED_WDT_H
5
+
6
+
#define AST2500_WDT_RESET_CPU (1 << 0)
7
+
#define AST2500_WDT_RESET_COPROC (1 << 1)
8
+
#define AST2500_WDT_RESET_SDRAM (1 << 2)
9
+
#define AST2500_WDT_RESET_AHB (1 << 3)
10
+
#define AST2500_WDT_RESET_I2C (1 << 4)
11
+
#define AST2500_WDT_RESET_MAC0 (1 << 5)
12
+
#define AST2500_WDT_RESET_MAC1 (1 << 6)
13
+
#define AST2500_WDT_RESET_GRAPHICS (1 << 7)
14
+
#define AST2500_WDT_RESET_USB2_HOST_HUB (1 << 8)
15
+
#define AST2500_WDT_RESET_USB_HOST (1 << 9)
16
+
#define AST2500_WDT_RESET_HID_EHCI (1 << 10)
17
+
#define AST2500_WDT_RESET_VIDEO (1 << 11)
18
+
#define AST2500_WDT_RESET_HAC (1 << 12)
19
+
#define AST2500_WDT_RESET_LPC (1 << 13)
20
+
#define AST2500_WDT_RESET_SDIO (1 << 14)
21
+
#define AST2500_WDT_RESET_MIC (1 << 15)
22
+
#define AST2500_WDT_RESET_CRT (1 << 16)
23
+
#define AST2500_WDT_RESET_PWM (1 << 17)
24
+
#define AST2500_WDT_RESET_PECI (1 << 18)
25
+
#define AST2500_WDT_RESET_JTAG (1 << 19)
26
+
#define AST2500_WDT_RESET_ADC (1 << 20)
27
+
#define AST2500_WDT_RESET_GPIO (1 << 21)
28
+
#define AST2500_WDT_RESET_MCTP (1 << 22)
29
+
#define AST2500_WDT_RESET_XDMA (1 << 23)
30
+
#define AST2500_WDT_RESET_SPI (1 << 24)
31
+
#define AST2500_WDT_RESET_SOC_MISC (1 << 25)
32
+
33
+
#define AST2500_WDT_RESET_DEFAULT 0x023ffff3
34
+
35
+
#define AST2600_WDT_RESET1_CPU (1 << 0)
36
+
#define AST2600_WDT_RESET1_SDRAM (1 << 1)
37
+
#define AST2600_WDT_RESET1_AHB (1 << 2)
38
+
#define AST2600_WDT_RESET1_SLI (1 << 3)
39
+
#define AST2600_WDT_RESET1_SOC_MISC0 (1 << 4)
40
+
#define AST2600_WDT_RESET1_COPROC (1 << 5)
41
+
#define AST2600_WDT_RESET1_USB_A (1 << 6)
42
+
#define AST2600_WDT_RESET1_USB_B (1 << 7)
43
+
#define AST2600_WDT_RESET1_UHCI (1 << 8)
44
+
#define AST2600_WDT_RESET1_GRAPHICS (1 << 9)
45
+
#define AST2600_WDT_RESET1_CRT (1 << 10)
46
+
#define AST2600_WDT_RESET1_VIDEO (1 << 11)
47
+
#define AST2600_WDT_RESET1_HAC (1 << 12)
48
+
#define AST2600_WDT_RESET1_DP (1 << 13)
49
+
#define AST2600_WDT_RESET1_DP_MCU (1 << 14)
50
+
#define AST2600_WDT_RESET1_GP_MCU (1 << 15)
51
+
#define AST2600_WDT_RESET1_MAC0 (1 << 16)
52
+
#define AST2600_WDT_RESET1_MAC1 (1 << 17)
53
+
#define AST2600_WDT_RESET1_SDIO0 (1 << 18)
54
+
#define AST2600_WDT_RESET1_JTAG0 (1 << 19)
55
+
#define AST2600_WDT_RESET1_MCTP0 (1 << 20)
56
+
#define AST2600_WDT_RESET1_MCTP1 (1 << 21)
57
+
#define AST2600_WDT_RESET1_XDMA0 (1 << 22)
58
+
#define AST2600_WDT_RESET1_XDMA1 (1 << 23)
59
+
#define AST2600_WDT_RESET1_GPIO0 (1 << 24)
60
+
#define AST2600_WDT_RESET1_RVAS (1 << 25)
61
+
62
+
#define AST2600_WDT_RESET1_DEFAULT 0x030f1ff1
63
+
64
+
#define AST2600_WDT_RESET2_CPU (1 << 0)
65
+
#define AST2600_WDT_RESET2_SPI (1 << 1)
66
+
#define AST2600_WDT_RESET2_AHB2 (1 << 2)
67
+
#define AST2600_WDT_RESET2_SLI2 (1 << 3)
68
+
#define AST2600_WDT_RESET2_SOC_MISC1 (1 << 4)
69
+
#define AST2600_WDT_RESET2_MAC2 (1 << 5)
70
+
#define AST2600_WDT_RESET2_MAC3 (1 << 6)
71
+
#define AST2600_WDT_RESET2_SDIO1 (1 << 7)
72
+
#define AST2600_WDT_RESET2_JTAG1 (1 << 8)
73
+
#define AST2600_WDT_RESET2_GPIO1 (1 << 9)
74
+
#define AST2600_WDT_RESET2_MDIO (1 << 10)
75
+
#define AST2600_WDT_RESET2_LPC (1 << 11)
76
+
#define AST2600_WDT_RESET2_PECI (1 << 12)
77
+
#define AST2600_WDT_RESET2_PWM (1 << 13)
78
+
#define AST2600_WDT_RESET2_ADC (1 << 14)
79
+
#define AST2600_WDT_RESET2_FSI (1 << 15)
80
+
#define AST2600_WDT_RESET2_I2C (1 << 16)
81
+
#define AST2600_WDT_RESET2_I3C_GLOBAL (1 << 17)
82
+
#define AST2600_WDT_RESET2_I3C0 (1 << 18)
83
+
#define AST2600_WDT_RESET2_I3C1 (1 << 19)
84
+
#define AST2600_WDT_RESET2_I3C2 (1 << 20)
85
+
#define AST2600_WDT_RESET2_I3C3 (1 << 21)
86
+
#define AST2600_WDT_RESET2_I3C4 (1 << 22)
87
+
#define AST2600_WDT_RESET2_I3C5 (1 << 23)
88
+
#define AST2600_WDT_RESET2_ESPI (1 << 26)
89
+
90
+
#define AST2600_WDT_RESET2_DEFAULT 0x03fffff1
91
+
92
+
#endif