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bus: mhi: host: pci_generic: Reset QDU100 while the MHI driver is removed

So, When the MHI driver is removed from the host side, it is essential to
ensure a clean and stable recovery of the device. This commit introduces
the following steps to achieve that:

1. Disable SR-IOV for any SR-IOV-enabled devices on the Physical Function.
2. Perform a SOC_RESET on the PF to fully reset the device.

Disabling SR-IOV ensures all Virtual Functions (VFs) are properly shutdown,
preventing issues during the reset process. The SOC_RESET guarantees that
the PF is restored to a known good state.

If soc_reset is not performed device at driver remove, device will be
stuck in mission mode state and subsequent driver insert/power_up will not
proceed further.

Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
[mani: reworded subject]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20250912-uevent_vdev_next-20250911-v4-4-fa2f6ccd301b@quicinc.com

authored by

Vivek Pernamitta and committed by
Manivannan Sadhasivam 12543f44 fd6e0509

+12
+12
drivers/bus/mhi/host/pci_generic.c
··· 45 45 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 46 46 * of inband wake support (such as sdx24) 47 47 * @no_m3: M3 not supported 48 + * @reset_on_remove: Set true for devices that require SoC during driver removal 48 49 */ 49 50 struct mhi_pci_dev_info { 50 51 const struct mhi_controller_config *config; ··· 59 58 unsigned int mru_default; 60 59 bool sideband_wake; 61 60 bool no_m3; 61 + bool reset_on_remove; 62 62 }; 63 63 64 64 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ ··· 302 300 .dma_data_width = 32, 303 301 .sideband_wake = false, 304 302 .no_m3 = true, 303 + .reset_on_remove = true, 305 304 }; 306 305 307 306 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { ··· 1030 1027 struct work_struct recovery_work; 1031 1028 struct timer_list health_check_timer; 1032 1029 unsigned long status; 1030 + bool reset_on_remove; 1033 1031 }; 1034 1032 1035 1033 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, ··· 1336 1332 mhi_cntrl->mru = info->mru_default; 1337 1333 mhi_cntrl->name = info->name; 1338 1334 1335 + if (pdev->is_physfn) 1336 + mhi_pdev->reset_on_remove = info->reset_on_remove; 1337 + 1339 1338 if (info->edl_trigger) 1340 1339 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1341 1340 ··· 1411 1404 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1412 1405 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1413 1406 1407 + pci_disable_sriov(pdev); 1408 + 1414 1409 if (pdev->is_physfn) 1415 1410 timer_delete_sync(&mhi_pdev->health_check_timer); 1416 1411 cancel_work_sync(&mhi_pdev->recovery_work); ··· 1425 1416 /* balancing probe put_noidle */ 1426 1417 if (pci_pme_capable(pdev, PCI_D3hot)) 1427 1418 pm_runtime_get_noresume(&pdev->dev); 1419 + 1420 + if (mhi_pdev->reset_on_remove) 1421 + mhi_soc_reset(mhi_cntrl); 1428 1422 1429 1423 mhi_unregister_controller(mhi_cntrl); 1430 1424 }