tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into clk-for-7.1

Merge the IPQ5210 Global clock controller binding through a topic
branch, to allow the constants to also be merged into the DeviceTree
branch.

Bjorn Andersson 12792987 04088a68

+315
+62
Documentation/devicetree/bindings/clock/qcom,ipq5210-gcc.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller on IPQ5210 8 + 9 + maintainers: 10 + - Bjorn Andersson <andersson@kernel.org> 11 + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> 12 + 13 + description: | 14 + Qualcomm global clock control module provides the clocks, resets and power 15 + domains on IPQ5210 16 + 17 + See also: 18 + include/dt-bindings/clock/qcom,ipq5210-gcc.h 19 + include/dt-bindings/reset/qcom,ipq5210-gcc.h 20 + 21 + properties: 22 + compatible: 23 + const: qcom,ipq5210-gcc 24 + 25 + clocks: 26 + items: 27 + - description: Board XO source 28 + - description: Sleep clock source 29 + - description: PCIE30 PHY0 pipe clock source 30 + - description: PCIE30 PHY1 pipe clock source 31 + - description: USB3 PHY pipe clock source 32 + - description: NSS common clock source 33 + 34 + '#power-domain-cells': false 35 + 36 + '#interconnect-cells': 37 + const: 1 38 + 39 + required: 40 + - compatible 41 + - clocks 42 + 43 + allOf: 44 + - $ref: qcom,gcc.yaml# 45 + 46 + unevaluatedProperties: false 47 + 48 + examples: 49 + - | 50 + clock-controller@1800000 { 51 + compatible = "qcom,ipq5210-gcc"; 52 + reg = <0x01800000 0x40000>; 53 + clocks = <&xo_board_clk>, 54 + <&sleep_clk>, 55 + <&pcie30_phy0_pipe_clk>, 56 + <&pcie30_phy1_pipe_clk>, 57 + <&usb3phy_0_cc_pipe_clk>, 58 + <&nss_cmn_clk>; 59 + #clock-cells = <1>; 60 + #reset-cells = <1>; 61 + }; 62 + ...
+126
include/dt-bindings/clock/qcom,ipq5210-gcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H 7 + #define _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5210_H 8 + 9 + #define GCC_ADSS_PWM_CLK 0 10 + #define GCC_ADSS_PWM_CLK_SRC 1 11 + #define GCC_CMN_12GPLL_AHB_CLK 2 12 + #define GCC_CMN_12GPLL_SYS_CLK 3 13 + #define GCC_CNOC_LPASS_CFG_CLK 4 14 + #define GCC_CNOC_PCIE0_1LANE_S_CLK 5 15 + #define GCC_CNOC_PCIE1_2LANE_S_CLK 6 16 + #define GCC_CNOC_USB_CLK 7 17 + #define GCC_GEPHY_SYS_CLK 8 18 + #define GCC_LPASS_AXIM_CLK_SRC 9 19 + #define GCC_LPASS_CORE_AXIM_CLK 10 20 + #define GCC_LPASS_SWAY_CLK 11 21 + #define GCC_LPASS_SWAY_CLK_SRC 12 22 + #define GCC_MDIO_AHB_CLK 13 23 + #define GCC_MDIO_GEPHY_AHB_CLK 14 24 + #define GCC_NSS_TS_CLK 15 25 + #define GCC_NSS_TS_CLK_SRC 16 26 + #define GCC_NSSCC_CLK 17 27 + #define GCC_NSSCFG_CLK 18 28 + #define GCC_NSSNOC_ATB_CLK 19 29 + #define GCC_NSSNOC_MEMNOC_1_CLK 20 30 + #define GCC_NSSNOC_MEMNOC_BFDCD_CLK_SRC 21 31 + #define GCC_NSSNOC_MEMNOC_CLK 22 32 + #define GCC_NSSNOC_MEMNOC_DIV_CLK_SRC 23 33 + #define GCC_NSSNOC_NSSCC_CLK 24 34 + #define GCC_NSSNOC_PCNOC_1_CLK 25 35 + #define GCC_NSSNOC_QOSGEN_REF_CLK 26 36 + #define GCC_NSSNOC_SNOC_1_CLK 27 37 + #define GCC_NSSNOC_SNOC_CLK 28 38 + #define GCC_NSSNOC_TIMEOUT_REF_CLK 29 39 + #define GCC_NSSNOC_XO_DCD_CLK 30 40 + #define GCC_PCIE0_AHB_CLK 31 41 + #define GCC_PCIE0_AUX_CLK 32 42 + #define GCC_PCIE0_AXI_M_CLK 33 43 + #define GCC_PCIE0_AXI_M_CLK_SRC 34 44 + #define GCC_PCIE0_AXI_S_BRIDGE_CLK 35 45 + #define GCC_PCIE0_AXI_S_CLK 36 46 + #define GCC_PCIE0_AXI_S_CLK_SRC 37 47 + #define GCC_PCIE0_PIPE_CLK 38 48 + #define GCC_PCIE0_PIPE_CLK_SRC 39 49 + #define GCC_PCIE0_RCHNG_CLK 40 50 + #define GCC_PCIE0_RCHNG_CLK_SRC 41 51 + #define GCC_PCIE1_AHB_CLK 42 52 + #define GCC_PCIE1_AUX_CLK 43 53 + #define GCC_PCIE1_AXI_M_CLK 44 54 + #define GCC_PCIE1_AXI_M_CLK_SRC 45 55 + #define GCC_PCIE1_AXI_S_BRIDGE_CLK 46 56 + #define GCC_PCIE1_AXI_S_CLK 47 57 + #define GCC_PCIE1_AXI_S_CLK_SRC 48 58 + #define GCC_PCIE1_PIPE_CLK 49 59 + #define GCC_PCIE1_PIPE_CLK_SRC 50 60 + #define GCC_PCIE1_RCHNG_CLK 51 61 + #define GCC_PCIE1_RCHNG_CLK_SRC 52 62 + #define GCC_PCIE_AUX_CLK_SRC 53 63 + #define GCC_PCNOC_BFDCD_CLK_SRC 54 64 + #define GCC_PON_APB_CLK 55 65 + #define GCC_PON_TM_CLK 56 66 + #define GCC_PON_TM2X_CLK 57 67 + #define GCC_PON_TM2X_CLK_SRC 58 68 + #define GCC_QDSS_AT_CLK 59 69 + #define GCC_QDSS_AT_CLK_SRC 60 70 + #define GCC_QDSS_DAP_CLK 61 71 + #define GCC_QDSS_TSCTR_CLK_SRC 62 72 + #define GCC_QPIC_AHB_CLK 63 73 + #define GCC_QPIC_CLK 64 74 + #define GCC_QPIC_CLK_SRC 65 75 + #define GCC_QPIC_IO_MACRO_CLK 66 76 + #define GCC_QPIC_IO_MACRO_CLK_SRC 67 77 + #define GCC_QRNG_AHB_CLK 68 78 + #define GCC_QUPV3_AHB_MST_CLK 69 79 + #define GCC_QUPV3_AHB_SLV_CLK 70 80 + #define GCC_QUPV3_WRAP_SE0_CLK 71 81 + #define GCC_QUPV3_WRAP_SE0_CLK_SRC 72 82 + #define GCC_QUPV3_WRAP_SE1_CLK 73 83 + #define GCC_QUPV3_WRAP_SE1_CLK_SRC 74 84 + #define GCC_QUPV3_WRAP_SE2_CLK 75 85 + #define GCC_QUPV3_WRAP_SE2_CLK_SRC 76 86 + #define GCC_QUPV3_WRAP_SE3_CLK 77 87 + #define GCC_QUPV3_WRAP_SE3_CLK_SRC 78 88 + #define GCC_QUPV3_WRAP_SE4_CLK 79 89 + #define GCC_QUPV3_WRAP_SE4_CLK_SRC 80 90 + #define GCC_QUPV3_WRAP_SE5_CLK 81 91 + #define GCC_QUPV3_WRAP_SE5_CLK_SRC 82 92 + #define GCC_SDCC1_AHB_CLK 83 93 + #define GCC_SDCC1_APPS_CLK 84 94 + #define GCC_SDCC1_APPS_CLK_SRC 85 95 + #define GCC_SDCC1_ICE_CORE_CLK 86 96 + #define GCC_SDCC1_ICE_CORE_CLK_SRC 87 97 + #define GCC_SLEEP_CLK_SRC 88 98 + #define GCC_SNOC_LPASS_CLK 89 99 + #define GCC_SNOC_PCIE0_AXI_M_CLK 90 100 + #define GCC_SNOC_PCIE1_AXI_M_CLK 91 101 + #define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 92 102 + #define GCC_UNIPHY0_AHB_CLK 93 103 + #define GCC_UNIPHY0_SYS_CLK 94 104 + #define GCC_UNIPHY1_AHB_CLK 95 105 + #define GCC_UNIPHY1_SYS_CLK 96 106 + #define GCC_UNIPHY2_AHB_CLK 97 107 + #define GCC_UNIPHY2_SYS_CLK 98 108 + #define GCC_UNIPHY_SYS_CLK_SRC 99 109 + #define GCC_USB0_AUX_CLK 100 110 + #define GCC_USB0_AUX_CLK_SRC 101 111 + #define GCC_USB0_MASTER_CLK 102 112 + #define GCC_USB0_MASTER_CLK_SRC 103 113 + #define GCC_USB0_MOCK_UTMI_CLK 104 114 + #define GCC_USB0_MOCK_UTMI_CLK_SRC 105 115 + #define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 106 116 + #define GCC_USB0_PHY_CFG_AHB_CLK 107 117 + #define GCC_USB0_PIPE_CLK 108 118 + #define GCC_USB0_PIPE_CLK_SRC 109 119 + #define GCC_USB0_SLEEP_CLK 110 120 + #define GCC_XO_CLK_SRC 111 121 + #define GPLL0_MAIN 112 122 + #define GPLL0 113 123 + #define GPLL2_MAIN 114 124 + #define GPLL2 115 125 + #define GPLL4_MAIN 116 126 + #endif
+127
include/dt-bindings/reset/qcom,ipq5210-gcc.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H 7 + #define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5210_H 8 + 9 + #define GCC_ADSS_BCR 0 10 + #define GCC_ADSS_PWM_ARES 1 11 + #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 2 12 + #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_ARES 3 13 + #define GCC_APSS_AHB_ARES 4 14 + #define GCC_APSS_ATB_ARES 5 15 + #define GCC_APSS_AXI_ARES 6 16 + #define GCC_APSS_TS_ARES 7 17 + #define GCC_BOOT_ROM_AHB_ARES 8 18 + #define GCC_BOOT_ROM_BCR 9 19 + #define GCC_GEPHY_BCR 10 20 + #define GCC_GEPHY_SYS_ARES 11 21 + #define GCC_GP1_ARES 12 22 + #define GCC_GP2_ARES 13 23 + #define GCC_GP3_ARES 14 24 + #define GCC_MDIO_AHB_ARES 15 25 + #define GCC_MDIO_BCR 16 26 + #define GCC_MDIO_GEPHY_AHB_ARES 17 27 + #define GCC_NSS_BCR 18 28 + #define GCC_NSS_TS_ARES 19 29 + #define GCC_NSSCC_ARES 20 30 + #define GCC_NSSCFG_ARES 21 31 + #define GCC_NSSNOC_ATB_ARES 22 32 + #define GCC_NSSNOC_MEMNOC_1_ARES 23 33 + #define GCC_NSSNOC_MEMNOC_ARES 24 34 + #define GCC_NSSNOC_NSSCC_ARES 25 35 + #define GCC_NSSNOC_PCNOC_1_ARES 26 36 + #define GCC_NSSNOC_QOSGEN_REF_ARES 27 37 + #define GCC_NSSNOC_SNOC_1_ARES 28 38 + #define GCC_NSSNOC_SNOC_ARES 29 39 + #define GCC_NSSNOC_TIMEOUT_REF_ARES 30 40 + #define GCC_NSSNOC_XO_DCD_ARES 31 41 + #define GCC_PCIE0_AHB_ARES 32 42 + #define GCC_PCIE0_AUX_ARES 33 43 + #define GCC_PCIE0_AXI_M_ARES 34 44 + #define GCC_PCIE0_AXI_S_BRIDGE_ARES 35 45 + #define GCC_PCIE0_AXI_S_ARES 36 46 + #define GCC_PCIE0_BCR 37 47 + #define GCC_PCIE0_LINK_DOWN_BCR 38 48 + #define GCC_PCIE0_PHY_BCR 39 49 + #define GCC_PCIE0_PIPE_ARES 40 50 + #define GCC_PCIE0PHY_PHY_BCR 41 51 + #define GCC_PCIE1_AHB_ARES 42 52 + #define GCC_PCIE1_AUX_ARES 43 53 + #define GCC_PCIE1_AXI_M_ARES 44 54 + #define GCC_PCIE1_AXI_S_BRIDGE_ARES 45 55 + #define GCC_PCIE1_AXI_S_ARES 46 56 + #define GCC_PCIE1_BCR 47 57 + #define GCC_PCIE1_LINK_DOWN_BCR 48 58 + #define GCC_PCIE1_PHY_BCR 49 59 + #define GCC_PCIE1_PIPE_ARES 50 60 + #define GCC_PCIE1PHY_PHY_BCR 51 61 + #define GCC_QRNG_AHB_ARES 52 62 + #define GCC_QRNG_BCR 53 63 + #define GCC_QUPV3_2X_CORE_ARES 54 64 + #define GCC_QUPV3_AHB_MST_ARES 55 65 + #define GCC_QUPV3_AHB_SLV_ARES 56 66 + #define GCC_QUPV3_BCR 57 67 + #define GCC_QUPV3_CORE_ARES 58 68 + #define GCC_QUPV3_WRAP_SE0_ARES 59 69 + #define GCC_QUPV3_WRAP_SE0_BCR 60 70 + #define GCC_QUPV3_WRAP_SE1_ARES 61 71 + #define GCC_QUPV3_WRAP_SE1_BCR 62 72 + #define GCC_QUPV3_WRAP_SE2_ARES 63 73 + #define GCC_QUPV3_WRAP_SE2_BCR 64 74 + #define GCC_QUPV3_WRAP_SE3_ARES 65 75 + #define GCC_QUPV3_WRAP_SE3_BCR 66 76 + #define GCC_QUPV3_WRAP_SE4_ARES 67 77 + #define GCC_QUPV3_WRAP_SE4_BCR 68 78 + #define GCC_QUPV3_WRAP_SE5_ARES 69 79 + #define GCC_QUPV3_WRAP_SE5_BCR 70 80 + #define GCC_QUSB2_0_PHY_BCR 71 81 + #define GCC_SDCC1_AHB_ARES 72 82 + #define GCC_SDCC1_APPS_ARES 73 83 + #define GCC_SDCC1_ICE_CORE_ARES 74 84 + #define GCC_SDCC_BCR 75 85 + #define GCC_TLMM_AHB_ARES 76 86 + #define GCC_TLMM_ARES 77 87 + #define GCC_TLMM_BCR 78 88 + #define GCC_UNIPHY0_AHB_ARES 79 89 + #define GCC_UNIPHY0_BCR 80 90 + #define GCC_UNIPHY0_SYS_ARES 81 91 + #define GCC_UNIPHY1_AHB_ARES 82 92 + #define GCC_UNIPHY1_BCR 83 93 + #define GCC_UNIPHY1_SYS_ARES 84 94 + #define GCC_UNIPHY2_AHB_ARES 85 95 + #define GCC_UNIPHY2_BCR 86 96 + #define GCC_UNIPHY2_SYS_ARES 87 97 + #define GCC_USB0_AUX_ARES 88 98 + #define GCC_USB0_MASTER_ARES 89 99 + #define GCC_USB0_MOCK_UTMI_ARES 90 100 + #define GCC_USB0_PHY_BCR 91 101 + #define GCC_USB0_PHY_CFG_AHB_ARES 92 102 + #define GCC_USB0_PIPE_ARES 93 103 + #define GCC_USB0_SLEEP_ARES 94 104 + #define GCC_USB3PHY_0_PHY_BCR 95 105 + #define GCC_USB_BCR 96 106 + #define GCC_PCIE0_PIPE_RESET 97 107 + #define GCC_PCIE0_CORE_STICKY_RESET 98 108 + #define GCC_PCIE0_AXI_S_STICKY_RESET 99 109 + #define GCC_PCIE0_AXI_S_RESET 100 110 + #define GCC_PCIE0_AXI_M_STICKY_RESET 101 111 + #define GCC_PCIE0_AXI_M_RESET 102 112 + #define GCC_PCIE0_AUX_RESET 103 113 + #define GCC_PCIE0_AHB_RESET 104 114 + #define GCC_PCIE1_PIPE_RESET 105 115 + #define GCC_PCIE1_CORE_STICKY_RESET 106 116 + #define GCC_PCIE1_AXI_S_STICKY_RESET 107 117 + #define GCC_PCIE1_AXI_S_RESET 108 118 + #define GCC_PCIE1_AXI_M_STICKY_RESET 109 119 + #define GCC_PCIE1_AXI_M_RESET 110 120 + #define GCC_PCIE1_AUX_RESET 111 121 + #define GCC_PCIE1_AHB_RESET 112 122 + #define GCC_UNIPHY0_XPCS_ARES 113 123 + #define GCC_UNIPHY1_XPCS_ARES 114 124 + #define GCC_UNIPHY2_XPCS_ARES 115 125 + #define GCC_QDSS_BCR 116 126 + 127 + #endif