Merge tag 'timers-v5.15' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

-27

Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt

··· 1 - Rockchip rk timer 2 - 3 - Required properties: 4 - - compatible: should be: 5 - "rockchip,rv1108-timer", "rockchip,rk3288-timer": for Rockchip RV1108 6 - "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036 7 - "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066 8 - "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188 9 - "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228 10 - "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229 11 - "rockchip,rk3288-timer": for Rockchip RK3288 12 - "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368 13 - "rockchip,rk3399-timer": for Rockchip RK3399 14 - - reg: base address of the timer register starting with TIMERS CONTROL register 15 - - interrupts: should contain the interrupts for Timer0 16 - - clocks : must contain an entry for each entry in clock-names 17 - - clock-names : must include the following entries: 18 - "timer", "pclk" 19 - 20 - Example: 21 - timer: timer@ff810000 { 22 - compatible = "rockchip,rk3288-timer"; 23 - reg = <0xff810000 0x20>; 24 - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 25 - clocks = <&xin24m>, <&cru PCLK_TIMER>; 26 - clock-names = "timer", "pclk"; 27 - };

+64

Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/timer/rockchip,rk-timer.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Rockchip Timer Device Tree Bindings 8 + 9 + maintainers: 10 + - Daniel Lezcano <daniel.lezcano@linaro.org> 11 + 12 + properties: 13 + compatible: 14 + oneOf: 15 + - const: rockchip,rk3288-timer 16 + - const: rockchip,rk3399-timer 17 + - items: 18 + - enum: 19 + - rockchip,rv1108-timer 20 + - rockchip,rk3036-timer 21 + - rockchip,rk3066-timer 22 + - rockchip,rk3188-timer 23 + - rockchip,rk3228-timer 24 + - rockchip,rk3229-timer 25 + - rockchip,rk3288-timer 26 + - rockchip,rk3368-timer 27 + - rockchip,px30-timer 28 + - const: rockchip,rk3288-timer 29 + reg: 30 + maxItems: 1 31 + 32 + interrupts: 33 + maxItems: 1 34 + 35 + clocks: 36 + minItems: 2 37 + maxItems: 2 38 + 39 + clock-names: 40 + items: 41 + - const: pclk 42 + - const: timer 43 + 44 + required: 45 + - compatible 46 + - reg 47 + - interrupts 48 + - clocks 49 + - clock-names 50 + 51 + additionalProperties: false 52 + 53 + examples: 54 + - | 55 + #include <dt-bindings/interrupt-controller/arm-gic.h> 56 + #include <dt-bindings/clock/rk3288-cru.h> 57 + 58 + timer: timer@ff810000 { 59 + compatible = "rockchip,rk3288-timer"; 60 + reg = <0xff810000 0x20>; 61 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 62 + clocks = <&cru PCLK_TIMER>, <&xin24m>; 63 + clock-names = "pclk", "timer"; 64 + };

+13 -3

drivers/clocksource/exynos_mct.c

··· 51 51 52 52 #define TICK_BASE_CNT 1 53 53 54 + #ifdef CONFIG_ARM 55 + /* Use values higher than ARM arch timer. See 6282edb72bed. */ 56 + #define MCT_CLKSOURCE_RATING 450 57 + #define MCT_CLKEVENTS_RATING 500 58 + #else 59 + #define MCT_CLKSOURCE_RATING 350 60 + #define MCT_CLKEVENTS_RATING 350 61 + #endif 62 + 54 63 enum { 55 64 MCT_INT_SPI, 56 65 MCT_INT_PPI ··· 215 206 216 207 static struct clocksource mct_frc = { 217 208 .name = "mct-frc", 218 - .rating = 450, /* use value higher than ARM arch timer */ 209 + .rating = MCT_CLKSOURCE_RATING, 219 210 .read = exynos4_frc_read, 220 211 .mask = CLOCKSOURCE_MASK(32), 221 212 .flags = CLOCK_SOURCE_IS_CONTINUOUS, ··· 465 456 evt->set_state_oneshot = set_state_shutdown; 466 457 evt->set_state_oneshot_stopped = set_state_shutdown; 467 458 evt->tick_resume = set_state_shutdown; 468 - evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 469 - evt->rating = 500; /* use value higher than ARM arch timer */ 459 + evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | 460 + CLOCK_EVT_FEAT_PERCPU; 461 + evt->rating = MCT_CLKEVENTS_RATING, 470 462 471 463 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 472 464

+7 -6

drivers/clocksource/ingenic-sysost.c

··· 4 4 * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 5 5 */ 6 6 7 + #include <linux/bitfield.h> 7 8 #include <linux/bitops.h> 8 9 #include <linux/clk.h> 9 10 #include <linux/clk-provider.h> ··· 35 34 /* bits within the OSTCCR register */ 36 35 #define OSTCCR_PRESCALE1_MASK 0x3 37 36 #define OSTCCR_PRESCALE2_MASK 0xc 38 - #define OSTCCR_PRESCALE1_LSB 0 39 - #define OSTCCR_PRESCALE2_LSB 2 40 37 41 38 /* bits within the OSTCR register */ 42 39 #define OSTCR_OST1CLR BIT(0) ··· 97 98 98 99 prescale = readl(ost_clk->ost->base + info->ostccr_reg); 99 100 100 - prescale = (prescale & OSTCCR_PRESCALE1_MASK) >> OSTCCR_PRESCALE1_LSB; 101 + prescale = FIELD_GET(OSTCCR_PRESCALE1_MASK, prescale); 101 102 102 103 return parent_rate >> (prescale * 2); 103 104 } ··· 111 112 112 113 prescale = readl(ost_clk->ost->base + info->ostccr_reg); 113 114 114 - prescale = (prescale & OSTCCR_PRESCALE2_MASK) >> OSTCCR_PRESCALE2_LSB; 115 + prescale = FIELD_GET(OSTCCR_PRESCALE2_MASK, prescale); 115 116 116 117 return parent_rate >> (prescale * 2); 117 118 } ··· 150 151 int val; 151 152 152 153 val = readl(ost_clk->ost->base + info->ostccr_reg); 153 - val = (val & ~OSTCCR_PRESCALE1_MASK) | (prescale << OSTCCR_PRESCALE1_LSB); 154 + val &= ~OSTCCR_PRESCALE1_MASK; 155 + val |= FIELD_PREP(OSTCCR_PRESCALE1_MASK, prescale); 154 156 writel(val, ost_clk->ost->base + info->ostccr_reg); 155 157 156 158 return 0; ··· 166 166 int val; 167 167 168 168 val = readl(ost_clk->ost->base + info->ostccr_reg); 169 - val = (val & ~OSTCCR_PRESCALE2_MASK) | (prescale << OSTCCR_PRESCALE2_LSB); 169 + val &= ~OSTCCR_PRESCALE2_MASK; 170 + val |= FIELD_PREP(OSTCCR_PRESCALE2_MASK, prescale); 170 171 writel(val, ost_clk->ost->base + info->ostccr_reg); 171 172 172 173 return 0;

+18 -12

drivers/clocksource/sh_cmt.c

··· 579 579 ch->flags |= flag; 580 580 581 581 /* setup timeout if no clockevent */ 582 - if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT))) 582 + if (ch->cmt->num_channels == 1 && 583 + flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) 583 584 __sh_cmt_set_next(ch, ch->max_match_value); 584 585 out: 585 586 raw_spin_unlock_irqrestore(&ch->lock, flags); ··· 622 621 static u64 sh_cmt_clocksource_read(struct clocksource *cs) 623 622 { 624 623 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs); 625 - unsigned long flags; 626 624 u32 has_wrapped; 627 - u64 value; 628 - u32 raw; 629 625 630 - raw_spin_lock_irqsave(&ch->lock, flags); 631 - value = ch->total_cycles; 632 - raw = sh_cmt_get_counter(ch, &has_wrapped); 626 + if (ch->cmt->num_channels == 1) { 627 + unsigned long flags; 628 + u64 value; 629 + u32 raw; 633 630 634 - if (unlikely(has_wrapped)) 635 - raw += ch->match_value + 1; 636 - raw_spin_unlock_irqrestore(&ch->lock, flags); 631 + raw_spin_lock_irqsave(&ch->lock, flags); 632 + value = ch->total_cycles; 633 + raw = sh_cmt_get_counter(ch, &has_wrapped); 637 634 638 - return value + raw; 635 + if (unlikely(has_wrapped)) 636 + raw += ch->match_value + 1; 637 + raw_spin_unlock_irqrestore(&ch->lock, flags); 638 + 639 + return value + raw; 640 + } 641 + 642 + return sh_cmt_get_counter(ch, &has_wrapped); 639 643 } 640 644 641 645 static int sh_cmt_clocksource_enable(struct clocksource *cs) ··· 703 697 cs->disable = sh_cmt_clocksource_disable; 704 698 cs->suspend = sh_cmt_clocksource_suspend; 705 699 cs->resume = sh_cmt_clocksource_resume; 706 - cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8); 700 + cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); 707 701 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; 708 702 709 703 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",

+16 -16

drivers/clocksource/timer-fttmr010.c

··· 271 271 } 272 272 273 273 static int __init fttmr010_common_init(struct device_node *np, 274 - bool is_aspeed, 275 - int (*timer_shutdown)(struct clock_event_device *), 276 - irq_handler_t irq_handler) 274 + bool is_aspeed, bool is_ast2600) 277 275 { 278 276 struct fttmr010 *fttmr010; 279 277 int irq; ··· 372 374 fttmr010->tick_rate); 373 375 } 374 376 375 - fttmr010->timer_shutdown = timer_shutdown; 376 - 377 377 /* 378 378 * Setup clockevent timer (interrupt-driven) on timer 1. 379 379 */ ··· 379 383 writel(0, fttmr010->base + TIMER1_LOAD); 380 384 writel(0, fttmr010->base + TIMER1_MATCH1); 381 385 writel(0, fttmr010->base + TIMER1_MATCH2); 382 - ret = request_irq(irq, irq_handler, IRQF_TIMER, 383 - "FTTMR010-TIMER1", &fttmr010->clkevt); 386 + 387 + if (is_ast2600) { 388 + fttmr010->timer_shutdown = ast2600_timer_shutdown; 389 + ret = request_irq(irq, ast2600_timer_interrupt, 390 + IRQF_TIMER, "FTTMR010-TIMER1", 391 + &fttmr010->clkevt); 392 + } else { 393 + fttmr010->timer_shutdown = fttmr010_timer_shutdown; 394 + ret = request_irq(irq, fttmr010_timer_interrupt, 395 + IRQF_TIMER, "FTTMR010-TIMER1", 396 + &fttmr010->clkevt); 397 + } 384 398 if (ret) { 385 399 pr_err("FTTMR010-TIMER1 no IRQ\n"); 386 400 goto out_unmap; ··· 438 432 439 433 static __init int ast2600_timer_init(struct device_node *np) 440 434 { 441 - return fttmr010_common_init(np, true, 442 - ast2600_timer_shutdown, 443 - ast2600_timer_interrupt); 435 + return fttmr010_common_init(np, true, true); 444 436 } 445 437 446 438 static __init int aspeed_timer_init(struct device_node *np) 447 439 { 448 - return fttmr010_common_init(np, true, 449 - fttmr010_timer_shutdown, 450 - fttmr010_timer_interrupt); 440 + return fttmr010_common_init(np, true, false); 451 441 } 452 442 453 443 static __init int fttmr010_timer_init(struct device_node *np) 454 444 { 455 - return fttmr010_common_init(np, false, 456 - fttmr010_timer_shutdown, 457 - fttmr010_timer_interrupt); 445 + return fttmr010_common_init(np, false, false); 458 446 } 459 447 460 448 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);

+6 -2

drivers/clocksource/timer-mediatek.c

··· 60 60 * SYST_CON_EN: Clock enable. Shall be set to 61 61 * - Start timer countdown. 62 62 * - Allow timeout ticks being updated. 63 - * - Allow changing interrupt functions. 63 + * - Allow changing interrupt status,like clear irq pending. 64 64 * 65 - * SYST_CON_IRQ_EN: Set to allow interrupt. 65 + * SYST_CON_IRQ_EN: Set to enable interrupt. 66 66 * 67 67 * SYST_CON_IRQ_CLR: Set to clear interrupt. 68 68 */ ··· 75 75 static void mtk_syst_ack_irq(struct timer_of *to) 76 76 { 77 77 /* Clear and disable interrupt */ 78 + writel(SYST_CON_EN, SYST_CON_REG(to)); 78 79 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to)); 79 80 } 80 81 ··· 112 111 113 112 static int mtk_syst_clkevt_shutdown(struct clock_event_device *clkevt) 114 113 { 114 + /* Clear any irq */ 115 + mtk_syst_ack_irq(to_timer_of(clkevt)); 116 + 115 117 /* Disable timer */ 116 118 writel(0, SYST_CON_REG(to_timer_of(clkevt))); 117 119

+19

include/dt-bindings/clock/ingenic,sysost.h

··· 13 13 #define OST_CLK_PERCPU_TIMER2 3 14 14 #define OST_CLK_PERCPU_TIMER3 4 15 15 16 + #define OST_CLK_EVENT_TIMER 1 17 + 18 + #define OST_CLK_EVENT_TIMER0 0 19 + #define OST_CLK_EVENT_TIMER1 1 20 + #define OST_CLK_EVENT_TIMER2 2 21 + #define OST_CLK_EVENT_TIMER3 3 22 + #define OST_CLK_EVENT_TIMER4 4 23 + #define OST_CLK_EVENT_TIMER5 5 24 + #define OST_CLK_EVENT_TIMER6 6 25 + #define OST_CLK_EVENT_TIMER7 7 26 + #define OST_CLK_EVENT_TIMER8 8 27 + #define OST_CLK_EVENT_TIMER9 9 28 + #define OST_CLK_EVENT_TIMER10 10 29 + #define OST_CLK_EVENT_TIMER11 11 30 + #define OST_CLK_EVENT_TIMER12 12 31 + #define OST_CLK_EVENT_TIMER13 13 32 + #define OST_CLK_EVENT_TIMER14 14 33 + #define OST_CLK_EVENT_TIMER15 15 34 + 16 35 #endif /* __DT_BINDINGS_CLOCK_INGENIC_OST_H__ */

Configure Feed

Configure Feed