Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/rockchip: Add basic RK3588 HDMI output support
The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1
Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a
Samsung IP block.
Add just the basic support for now, i.e. RGB output up to 4K@60Hz,
without audio, CEC or any of the HDMI 2.1 specific features.
Co-developed-by: Algea Cao <algea.cao@rock-chips.com>
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241016-b4-rk3588-bridge-upstream-v10-3-87ef92a6d14e@collabora.com
Signed-off-by: Maxime Ripard <mripard@kernel.org>
authored by
Cristian Ciocaltea
and committed by
Maxime Ripard
128a9bf8
c0d28332
+437
+9
drivers/gpu/drm/rockchip/Kconfig
+9
drivers/gpu/drm/rockchip/Kconfig
···
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select VIDEOMODE_HELPERS
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select DRM_ANALOGIX_DP if ROCKCHIP_ANALOGIX_DP
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select DRM_DW_HDMI if ROCKCHIP_DW_HDMI
12
+
select DRM_DW_HDMI_QP if ROCKCHIP_DW_HDMI_QP
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select DRM_DW_MIPI_DSI if ROCKCHIP_DW_MIPI_DSI
13
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select GENERIC_PHY if ROCKCHIP_DW_MIPI_DSI
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select GENERIC_PHY_MIPI_DPHY if ROCKCHIP_DW_MIPI_DSI
···
64
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for the Synopsys DesignWare HDMI driver. If you want to
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enable HDMI on RK3288 or RK3399 based SoC, you should select
66
65
this option.
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+
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config ROCKCHIP_DW_HDMI_QP
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bool "Rockchip specific extensions for Synopsys DW HDMI QP"
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select DRM_BRIDGE_CONNECTOR
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help
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This selects support for Rockchip SoC specific extensions
72
+
for the Synopsys DesignWare HDMI QP driver. If you want to
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+
enable HDMI on RK3588 based SoC, you should select this option.
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config ROCKCHIP_DW_MIPI_DSI
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bool "Rockchip specific extensions for Synopsys DW MIPI DSI"
+1
drivers/gpu/drm/rockchip/Makefile
+1
drivers/gpu/drm/rockchip/Makefile
···
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rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
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rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
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rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
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+
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI_QP) += dw_hdmi_qp-rockchip.o
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rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
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rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
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rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
+424
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+424
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
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+
* Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2024 Collabora Ltd.
5
+
*
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+
* Author: Algea Cao <algea.cao@rock-chips.com>
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* Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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+
*/
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+
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#include <linux/clk.h>
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+
#include <linux/gpio/consumer.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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+
#include <linux/regmap.h>
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+
#include <linux/workqueue.h>
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+
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#include <drm/bridge/dw_hdmi_qp.h>
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#include <drm/display/drm_hdmi_helper.h>
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#include <drm/drm_bridge_connector.h>
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#include <drm/drm_of.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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+
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#include "rockchip_drm_drv.h"
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+
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#define RK3588_GRF_SOC_CON2 0x0308
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#define RK3588_HDMI0_HPD_INT_MSK BIT(13)
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#define RK3588_HDMI0_HPD_INT_CLR BIT(12)
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#define RK3588_GRF_SOC_CON7 0x031c
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#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12)
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#define RK3588_GRF_SOC_STATUS1 0x0384
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#define RK3588_HDMI0_LEVEL_INT BIT(16)
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#define RK3588_GRF_VO1_CON3 0x000c
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#define RK3588_SCLIN_MASK BIT(9)
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#define RK3588_SDAIN_MASK BIT(10)
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#define RK3588_MODE_MASK BIT(11)
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#define RK3588_I2S_SEL_MASK BIT(13)
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#define RK3588_GRF_VO1_CON9 0x0024
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#define RK3588_HDMI0_GRANT_SEL BIT(10)
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+
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#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
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#define HOTPLUG_DEBOUNCE_MS 150
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+
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struct rockchip_hdmi_qp {
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struct device *dev;
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struct regmap *regmap;
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struct regmap *vo_regmap;
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struct rockchip_encoder encoder;
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struct clk *ref_clk;
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struct dw_hdmi_qp *hdmi;
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struct phy *phy;
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struct gpio_desc *enable_gpio;
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struct delayed_work hpd_work;
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};
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+
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static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(struct drm_encoder *encoder)
59
+
{
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struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
61
+
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return container_of(rkencoder, struct rockchip_hdmi_qp, encoder);
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+
}
64
+
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static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder)
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+
{
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struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder);
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struct drm_crtc *crtc = encoder->crtc;
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unsigned long long rate;
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+
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/* Unconditionally switch to TMDS as FRL is not yet supported */
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gpiod_set_value(hdmi->enable_gpio, 1);
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+
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if (crtc && crtc->state) {
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rate = drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode,
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8, HDMI_COLORSPACE_RGB);
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clk_set_rate(hdmi->ref_clk, rate);
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/*
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* FIXME: Temporary workaround to pass pixel clock rate
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* to the PHY driver until phy_configure_opts_hdmi
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* becomes available in the PHY API. See also the related
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* comment in rk_hdptx_phy_power_on() from
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* drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
84
+
*/
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phy_set_bus_width(hdmi->phy, rate / 100);
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+
}
87
+
}
88
+
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static int
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dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
93
+
{
94
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struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
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+
96
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s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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s->output_type = DRM_MODE_CONNECTOR_HDMIA;
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+
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return 0;
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}
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+
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static const struct
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drm_encoder_helper_funcs dw_hdmi_qp_rockchip_encoder_helper_funcs = {
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.enable = dw_hdmi_qp_rockchip_encoder_enable,
105
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.atomic_check = dw_hdmi_qp_rockchip_encoder_atomic_check,
106
+
};
107
+
108
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static int dw_hdmi_qp_rk3588_phy_init(struct dw_hdmi_qp *dw_hdmi, void *data)
109
+
{
110
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
111
+
112
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return phy_power_on(hdmi->phy);
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+
}
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+
115
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static void dw_hdmi_qp_rk3588_phy_disable(struct dw_hdmi_qp *dw_hdmi,
116
+
void *data)
117
+
{
118
+
struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
119
+
120
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phy_power_off(hdmi->phy);
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+
}
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+
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static enum drm_connector_status
124
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dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
125
+
{
126
+
struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
127
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u32 val;
128
+
129
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val);
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+
131
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return val & RK3588_HDMI0_LEVEL_INT ?
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connector_status_connected : connector_status_disconnected;
133
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}
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+
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static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
136
+
{
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
138
+
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regmap_write(hdmi->regmap,
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RK3588_GRF_SOC_CON2,
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HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR |
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RK3588_HDMI0_HPD_INT_MSK));
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}
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+
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static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = {
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.init = dw_hdmi_qp_rk3588_phy_init,
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.disable = dw_hdmi_qp_rk3588_phy_disable,
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.read_hpd = dw_hdmi_qp_rk3588_read_hpd,
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.setup_hpd = dw_hdmi_qp_rk3588_setup_hpd,
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};
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+
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static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work)
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+
{
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struct rockchip_hdmi_qp *hdmi = container_of(work,
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struct rockchip_hdmi_qp,
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hpd_work.work);
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struct drm_device *drm = hdmi->encoder.encoder.dev;
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bool changed;
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+
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if (drm) {
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changed = drm_helper_hpd_irq_event(drm);
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if (changed)
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drm_dbg(hdmi, "connector status changed\n");
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}
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}
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+
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static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id)
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{
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struct rockchip_hdmi_qp *hdmi = dev_id;
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u32 intr_stat, val;
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+
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
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+
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if (intr_stat) {
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,
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RK3588_HDMI0_HPD_INT_MSK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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return IRQ_WAKE_THREAD;
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}
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+
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return IRQ_NONE;
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}
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+
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static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id)
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+
{
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struct rockchip_hdmi_qp *hdmi = dev_id;
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u32 intr_stat, val;
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+
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
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if (!intr_stat)
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return IRQ_NONE;
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+
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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+
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mod_delayed_work(system_wq, &hdmi->hpd_work,
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msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
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val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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+
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return IRQ_HANDLED;
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}
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+
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static const struct of_device_id dw_hdmi_qp_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3588-dw-hdmi-qp",
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.data = &rk3588_hdmi_phy_ops },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_hdmi_qp_rockchip_dt_ids);
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+
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static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
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void *data)
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{
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static const char * const clk_names[] = {
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"pclk", "earc", "aud", "hdp", "hclk_vo1",
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"ref" /* keep "ref" last */
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};
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struct platform_device *pdev = to_platform_device(dev);
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struct dw_hdmi_qp_plat_data plat_data;
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struct drm_device *drm = data;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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struct rockchip_hdmi_qp *hdmi;
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struct clk *clk;
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int ret, irq, i;
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u32 val;
230
+
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if (!pdev->dev.of_node)
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return -ENODEV;
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+
234
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hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
235
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if (!hdmi)
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return -ENOMEM;
237
+
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plat_data.phy_ops = of_device_get_match_data(dev);
239
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if (!plat_data.phy_ops)
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return -ENODEV;
241
+
242
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plat_data.phy_data = hdmi;
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+
hdmi->dev = &pdev->dev;
244
+
245
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encoder = &hdmi->encoder.encoder;
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
247
+
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rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
249
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dev->of_node, 0, 0);
250
+
/*
251
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* If we failed to find the CRTC(s) which this encoder is
252
+
* supposed to be connected to, it's because the CRTC has
253
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* not been registered yet. Defer probing, and hope that
254
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* the required CRTC is added later.
255
+
*/
256
+
if (encoder->possible_crtcs == 0)
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return -EPROBE_DEFER;
258
+
259
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hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
260
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"rockchip,grf");
261
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if (IS_ERR(hdmi->regmap)) {
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drm_err(hdmi, "Unable to get rockchip,grf\n");
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return PTR_ERR(hdmi->regmap);
264
+
}
265
+
266
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hdmi->vo_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
267
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"rockchip,vo-grf");
268
+
if (IS_ERR(hdmi->vo_regmap)) {
269
+
drm_err(hdmi, "Unable to get rockchip,vo-grf\n");
270
+
return PTR_ERR(hdmi->vo_regmap);
271
+
}
272
+
273
+
for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
274
+
clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]);
275
+
276
+
if (IS_ERR(clk)) {
277
+
ret = PTR_ERR(clk);
278
+
if (ret != -EPROBE_DEFER)
279
+
drm_err(hdmi, "Failed to get %s clock: %d\n",
280
+
clk_names[i], ret);
281
+
return ret;
282
+
}
283
+
}
284
+
hdmi->ref_clk = clk;
285
+
286
+
hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable",
287
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GPIOD_OUT_HIGH);
288
+
if (IS_ERR(hdmi->enable_gpio)) {
289
+
ret = PTR_ERR(hdmi->enable_gpio);
290
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drm_err(hdmi, "Failed to request enable GPIO: %d\n", ret);
291
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return ret;
292
+
}
293
+
294
+
hdmi->phy = devm_of_phy_get_by_index(dev, dev->of_node, 0);
295
+
if (IS_ERR(hdmi->phy)) {
296
+
ret = PTR_ERR(hdmi->phy);
297
+
if (ret != -EPROBE_DEFER)
298
+
drm_err(hdmi, "failed to get phy: %d\n", ret);
299
+
return ret;
300
+
}
301
+
302
+
val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
303
+
HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
304
+
HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
305
+
HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
306
+
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val);
307
+
308
+
val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
309
+
RK3588_SET_HPD_PATH_MASK);
310
+
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
311
+
312
+
val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
313
+
RK3588_HDMI0_GRANT_SEL);
314
+
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
315
+
316
+
val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);
317
+
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
318
+
319
+
INIT_DELAYED_WORK(&hdmi->hpd_work, dw_hdmi_qp_rk3588_hpd_work);
320
+
321
+
plat_data.main_irq = platform_get_irq_byname(pdev, "main");
322
+
if (plat_data.main_irq < 0)
323
+
return plat_data.main_irq;
324
+
325
+
irq = platform_get_irq_byname(pdev, "hpd");
326
+
if (irq < 0)
327
+
return irq;
328
+
329
+
ret = devm_request_threaded_irq(hdmi->dev, irq,
330
+
dw_hdmi_qp_rk3588_hardirq,
331
+
dw_hdmi_qp_rk3588_irq,
332
+
IRQF_SHARED, "dw-hdmi-qp-hpd",
333
+
hdmi);
334
+
if (ret)
335
+
return ret;
336
+
337
+
drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs);
338
+
drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
339
+
340
+
platform_set_drvdata(pdev, hdmi);
341
+
342
+
hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data);
343
+
if (IS_ERR(hdmi->hdmi)) {
344
+
ret = PTR_ERR(hdmi->hdmi);
345
+
drm_encoder_cleanup(encoder);
346
+
return ret;
347
+
}
348
+
349
+
connector = drm_bridge_connector_init(drm, encoder);
350
+
if (IS_ERR(connector)) {
351
+
ret = PTR_ERR(connector);
352
+
drm_err(hdmi, "failed to init bridge connector: %d\n", ret);
353
+
return ret;
354
+
}
355
+
356
+
return drm_connector_attach_encoder(connector, encoder);
357
+
}
358
+
359
+
static void dw_hdmi_qp_rockchip_unbind(struct device *dev,
360
+
struct device *master,
361
+
void *data)
362
+
{
363
+
struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
364
+
365
+
cancel_delayed_work_sync(&hdmi->hpd_work);
366
+
367
+
drm_encoder_cleanup(&hdmi->encoder.encoder);
368
+
}
369
+
370
+
static const struct component_ops dw_hdmi_qp_rockchip_ops = {
371
+
.bind = dw_hdmi_qp_rockchip_bind,
372
+
.unbind = dw_hdmi_qp_rockchip_unbind,
373
+
};
374
+
375
+
static int dw_hdmi_qp_rockchip_probe(struct platform_device *pdev)
376
+
{
377
+
return component_add(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
378
+
}
379
+
380
+
static void dw_hdmi_qp_rockchip_remove(struct platform_device *pdev)
381
+
{
382
+
component_del(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
383
+
}
384
+
385
+
static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev)
386
+
{
387
+
struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
388
+
u32 val;
389
+
390
+
val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
391
+
HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
392
+
HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
393
+
HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
394
+
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val);
395
+
396
+
val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
397
+
RK3588_SET_HPD_PATH_MASK);
398
+
regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
399
+
400
+
val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
401
+
RK3588_HDMI0_GRANT_SEL);
402
+
regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
403
+
404
+
dw_hdmi_qp_resume(dev, hdmi->hdmi);
405
+
406
+
if (hdmi->encoder.encoder.dev)
407
+
drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev);
408
+
409
+
return 0;
410
+
}
411
+
412
+
static const struct dev_pm_ops dw_hdmi_qp_rockchip_pm = {
413
+
SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_qp_rockchip_resume)
414
+
};
415
+
416
+
struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver = {
417
+
.probe = dw_hdmi_qp_rockchip_probe,
418
+
.remove = dw_hdmi_qp_rockchip_remove,
419
+
.driver = {
420
+
.name = "dwhdmiqp-rockchip",
421
+
.pm = &dw_hdmi_qp_rockchip_pm,
422
+
.of_match_table = dw_hdmi_qp_rockchip_dt_ids,
423
+
},
424
+
};
+2
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+2
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
···
532
532
ADD_ROCKCHIP_SUB_DRIVER(cdn_dp_driver, CONFIG_ROCKCHIP_CDN_DP);
533
533
ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_rockchip_pltfm_driver,
534
534
CONFIG_ROCKCHIP_DW_HDMI);
535
+
ADD_ROCKCHIP_SUB_DRIVER(dw_hdmi_qp_rockchip_pltfm_driver,
536
+
CONFIG_ROCKCHIP_DW_HDMI_QP);
535
537
ADD_ROCKCHIP_SUB_DRIVER(dw_mipi_dsi_rockchip_driver,
536
538
CONFIG_ROCKCHIP_DW_MIPI_DSI);
537
539
ADD_ROCKCHIP_SUB_DRIVER(inno_hdmi_driver, CONFIG_ROCKCHIP_INNO_HDMI);
+1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+1
drivers/gpu/drm/rockchip/rockchip_drm_drv.h
···
88
88
int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
89
89
extern struct platform_driver cdn_dp_driver;
90
90
extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
91
+
extern struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver;
91
92
extern struct platform_driver dw_mipi_dsi_rockchip_driver;
92
93
extern struct platform_driver inno_hdmi_driver;
93
94
extern struct platform_driver rockchip_dp_driver;