tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/amd/display: Update DTBCLK for DCN32

[Why&How]
- Implement interface to program DTBCLK DTO’s
according to reference DTBCLK returned by PMFW
- This is required because DTO programming
requires exact DTBCLK reference freq or it could
result in underflow

Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Alvin Lee and committed by
Alex Deucher 128c1ca0 3306ba4b

+27
+27
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
··· 233 233 DC_FP_END(); 234 234 } 235 235 236 + static void dcn32_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr, 237 + struct dc_state *context, 238 + int ref_dtbclk_khz) 239 + { 240 + struct dccg *dccg = clk_mgr->dccg; 241 + uint32_t tg_mask = 0; 242 + int i; 243 + 244 + for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { 245 + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 246 + struct dtbclk_dto_params dto_params = {0}; 247 + 248 + /* use mask to program DTO once per tg */ 249 + if (pipe_ctx->stream_res.tg && 250 + !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { 251 + tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); 252 + 253 + dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; 254 + dto_params.ref_dtbclk_khz = ref_dtbclk_khz; 255 + 256 + dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); 257 + //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); 258 + } 259 + } 260 + } 261 + 236 262 /* Since DPPCLK request to PMFW needs to be exact (due to DPP DTO programming), 237 263 * update DPPCLK to be the exact frequency that will be set after the DPPCLK 238 264 * divider is updated. This will prevent rounding issues that could cause DPP ··· 596 570 /* DCCG requires KHz precision for DTBCLK */ 597 571 clk_mgr_base->clks.ref_dtbclk_khz = 598 572 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz)); 573 + dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz); 599 574 } 600 575 601 576 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {