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drm/msm: adreno: fix deferencing ifpc_reglist when not declared

On plaforms with an a7xx GPU not supporting IFPC, the ifpc_reglist
if still deferenced in a7xx_patch_pwrup_reglist() which causes
a kernel crash:
Unable to handle kernel NULL pointer dereference at virtual address 0000000000000008
...
pc : a6xx_hw_init+0x155c/0x1e4c [msm]
lr : a6xx_hw_init+0x9a8/0x1e4c [msm]
...
Call trace:
a6xx_hw_init+0x155c/0x1e4c [msm] (P)
msm_gpu_hw_init+0x58/0x88 [msm]
adreno_load_gpu+0x94/0x1fc [msm]
msm_open+0xe4/0xf4 [msm]
drm_file_alloc+0x1a0/0x2e4 [drm]
drm_client_init+0x7c/0x104 [drm]
drm_fbdev_client_setup+0x94/0xcf0 [drm_client_lib]
drm_client_setup+0xb4/0xd8 [drm_client_lib]
msm_drm_kms_post_init+0x2c/0x3c [msm]
msm_drm_init+0x1a4/0x228 [msm]
msm_drm_bind+0x30/0x3c [msm]
...

Check the validity of ifpc_reglist before deferencing the table
to setup the register values.

Fixes: a6a0157cc68e ("drm/msm/a6xx: Enable IFPC on Adreno X1-85")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/688944/
Message-ID: <20251117-topic-sm8x50-fix-a6xx-non-ifpc-v1-1-e4473cbf5903@linaro.org>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Neil Armstrong and committed by
Rob Clark 129049d4 7bc29d5f

+10 -8
+10 -8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 873 873 lock->gpu_req = lock->cpu_req = lock->turn = 0; 874 874 875 875 reglist = adreno_gpu->info->a6xx->ifpc_reglist; 876 - lock->ifpc_list_len = reglist->count; 876 + if (reglist) { 877 + lock->ifpc_list_len = reglist->count; 877 878 878 - /* 879 - * For each entry in each of the lists, write the offset and the current 880 - * register value into the GPU buffer 881 - */ 882 - for (i = 0; i < reglist->count; i++) { 883 - *dest++ = reglist->regs[i]; 884 - *dest++ = gpu_read(gpu, reglist->regs[i]); 879 + /* 880 + * For each entry in each of the lists, write the offset and the current 881 + * register value into the GPU buffer 882 + */ 883 + for (i = 0; i < reglist->count; i++) { 884 + *dest++ = reglist->regs[i]; 885 + *dest++ = gpu_read(gpu, reglist->regs[i]); 886 + } 885 887 } 886 888 887 889 reglist = adreno_gpu->info->a6xx->pwrup_reglist;