Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock driver fixes from Mike Turquette:
"Small number of fixes for clock drivers and a single null pointer
dereference fix in the framework core code.
The driver fixes vary from fixing section mismatch warnings to
preventing machines from hanging (and preventing developers from
crying)"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: fix possible null pointer dereference
Revert "clk: ppc-corenet: Fix Section mismatch warning"
clk: rockchip: fix deadlock possibility in cpuclk
clk: berlin: bg2q: remove non-exist "smemc" gate clock
clk: at91: keep slow clk enabled to prevent system hang
clk: rockchip: fix rk3288 cpuclk core dividers
clk: rockchip: fix rk3066 pll lock bit location
clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri
clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host
+69
-28
+27
drivers/clk/at91/clk-slow.c
+27
drivers/clk/at91/clk-slow.c
···
70
70
71
71
#define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
72
72
73
+
static struct clk *slow_clk;
73
74
74
75
static int clk_slow_osc_prepare(struct clk_hw *hw)
75
76
{
···
358
357
clk = clk_register(NULL, &slowck->hw);
359
358
if (IS_ERR(clk))
360
359
kfree(slowck);
360
+
else
361
+
slow_clk = clk;
361
362
362
363
return clk;
363
364
}
···
436
433
clk = clk_register(NULL, &slowck->hw);
437
434
if (IS_ERR(clk))
438
435
kfree(slowck);
436
+
else
437
+
slow_clk = clk;
439
438
440
439
return clk;
441
440
}
···
470
465
471
466
of_clk_add_provider(np, of_clk_src_simple_get, clk);
472
467
}
468
+
469
+
/*
470
+
* FIXME: All slow clk users are not properly claiming it (get + prepare +
471
+
* enable) before using it.
472
+
* If all users properly claiming this clock decide that they don't need it
473
+
* anymore (or are removed), it is disabled while faulty users are still
474
+
* requiring it, and the system hangs.
475
+
* Prevent this clock from being disabled until all users are properly
476
+
* requesting it.
477
+
* Once this is done we should remove this function and the slow_clk variable.
478
+
*/
479
+
static int __init of_at91_clk_slow_retain(void)
480
+
{
481
+
if (!slow_clk)
482
+
return 0;
483
+
484
+
__clk_get(slow_clk);
485
+
clk_prepare_enable(slow_clk);
486
+
487
+
return 0;
488
+
}
489
+
arch_initcall(of_at91_clk_slow_retain);
-1
drivers/clk/berlin/bg2q.c
-1
drivers/clk/berlin/bg2q.c
+1
-1
drivers/clk/clk-ppc-corenet.c
+1
-1
drivers/clk/clk-ppc-corenet.c
+1
-1
drivers/clk/clk.c
+1
-1
drivers/clk/clk.c
···
1366
1366
new_rate = clk->ops->determine_rate(clk->hw, rate,
1367
1367
&best_parent_rate,
1368
1368
&parent_hw);
1369
-
parent = parent_hw->clk;
1369
+
parent = parent_hw ? parent_hw->clk : NULL;
1370
1370
} else if (clk->ops->round_rate) {
1371
1371
new_rate = clk->ops->round_rate(clk->hw, rate,
1372
1372
&best_parent_rate);
+6
-4
drivers/clk/rockchip/clk-cpu.c
+6
-4
drivers/clk/rockchip/clk-cpu.c
···
124
124
{
125
125
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
126
126
unsigned long alt_prate, alt_div;
127
+
unsigned long flags;
127
128
128
129
alt_prate = clk_get_rate(cpuclk->alt_parent);
129
130
130
-
spin_lock(cpuclk->lock);
131
+
spin_lock_irqsave(cpuclk->lock, flags);
131
132
132
133
/*
133
134
* If the old parent clock speed is less than the clock speed
···
165
164
cpuclk->reg_base + reg_data->core_reg);
166
165
}
167
166
168
-
spin_unlock(cpuclk->lock);
167
+
spin_unlock_irqrestore(cpuclk->lock, flags);
169
168
return 0;
170
169
}
171
170
···
174
173
{
175
174
const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
176
175
const struct rockchip_cpuclk_rate_table *rate;
176
+
unsigned long flags;
177
177
178
178
rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
179
179
if (!rate) {
···
183
181
return -EINVAL;
184
182
}
185
183
186
-
spin_lock(cpuclk->lock);
184
+
spin_lock_irqsave(cpuclk->lock, flags);
187
185
188
186
if (ndata->old_rate < ndata->new_rate)
189
187
rockchip_cpuclk_set_dividers(cpuclk, rate);
···
203
201
if (ndata->old_rate > ndata->new_rate)
204
202
rockchip_cpuclk_set_dividers(cpuclk, rate);
205
203
206
-
spin_unlock(cpuclk->lock);
204
+
spin_unlock_irqrestore(cpuclk->lock, flags);
207
205
return 0;
208
206
}
209
207
+20
-7
drivers/clk/rockchip/clk-rk3188.c
+20
-7
drivers/clk/rockchip/clk-rk3188.c
···
210
210
PNAME(mux_mac_p) = { "gpll", "dpll" };
211
211
PNAME(mux_sclk_macref_p) = { "mac_src", "ext_rmii" };
212
212
213
+
static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
214
+
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215
+
RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
216
+
[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
217
+
RK2928_MODE_CON, 4, 4, 0, NULL),
218
+
[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
219
+
RK2928_MODE_CON, 8, 6, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
220
+
[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
221
+
RK2928_MODE_CON, 12, 7, ROCKCHIP_PLL_SYNC_RATE, rk3188_pll_rates),
222
+
};
223
+
213
224
static struct rockchip_pll_clock rk3188_pll_clks[] __initdata = {
214
225
[apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
215
226
RK2928_MODE_CON, 0, 6, 0, rk3188_pll_rates),
···
438
427
/* hclk_peri gates */
439
428
GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 0, GFLAGS),
440
429
GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 6, GFLAGS),
441
-
GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, GFLAGS),
430
+
GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 7, GFLAGS),
442
431
GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, GFLAGS),
443
432
GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
444
-
GATE(0, "hclk_usb_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 5, GFLAGS),
445
-
GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 13, GFLAGS),
433
+
GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(4), 5, GFLAGS),
434
+
GATE(HCLK_OTG0, "hclk_usbotg0", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 13, GFLAGS),
446
435
GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 5, GFLAGS),
447
436
GATE(HCLK_PIDF, "hclk_pidfilter", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 6, GFLAGS),
448
437
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 10, GFLAGS),
···
603
592
GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
604
593
GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
605
594
606
-
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
595
+
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
596
+
RK2928_CLKGATE_CON(5), 14, GFLAGS),
607
597
608
598
GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
609
599
···
692
680
GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
693
681
GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
694
682
695
-
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
683
+
GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
684
+
RK2928_CLKGATE_CON(7), 3, GFLAGS),
696
685
GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
697
686
698
687
GATE(PCLK_TIMER3, "pclk_timer3", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
···
748
735
static void __init rk3066a_clk_init(struct device_node *np)
749
736
{
750
737
rk3188_common_clk_init(np);
751
-
rockchip_clk_register_plls(rk3188_pll_clks,
752
-
ARRAY_SIZE(rk3188_pll_clks),
738
+
rockchip_clk_register_plls(rk3066_pll_clks,
739
+
ARRAY_SIZE(rk3066_pll_clks),
753
740
RK3066_GRF_SOC_STATUS);
754
741
rockchip_clk_register_branches(rk3066a_clk_branches,
755
742
ARRAY_SIZE(rk3066a_clk_branches));
+14
-14
drivers/clk/rockchip/clk-rk3288.c
+14
-14
drivers/clk/rockchip/clk-rk3288.c
···
145
145
}
146
146
147
147
static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
148
-
RK3288_CPUCLK_RATE(1800000000, 2, 4, 2, 4, 4),
149
-
RK3288_CPUCLK_RATE(1704000000, 2, 4, 2, 4, 4),
150
-
RK3288_CPUCLK_RATE(1608000000, 2, 4, 2, 4, 4),
151
-
RK3288_CPUCLK_RATE(1512000000, 2, 4, 2, 4, 4),
152
-
RK3288_CPUCLK_RATE(1416000000, 2, 4, 2, 4, 4),
153
-
RK3288_CPUCLK_RATE(1200000000, 2, 4, 2, 4, 4),
154
-
RK3288_CPUCLK_RATE(1008000000, 2, 4, 2, 4, 4),
155
-
RK3288_CPUCLK_RATE( 816000000, 2, 4, 2, 4, 4),
156
-
RK3288_CPUCLK_RATE( 696000000, 2, 4, 2, 4, 4),
157
-
RK3288_CPUCLK_RATE( 600000000, 2, 4, 2, 4, 4),
158
-
RK3288_CPUCLK_RATE( 408000000, 2, 4, 2, 4, 4),
159
-
RK3288_CPUCLK_RATE( 312000000, 2, 4, 2, 4, 4),
160
-
RK3288_CPUCLK_RATE( 216000000, 2, 4, 2, 4, 4),
161
-
RK3288_CPUCLK_RATE( 126000000, 2, 4, 2, 4, 4),
148
+
RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
149
+
RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
150
+
RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
151
+
RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
152
+
RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
153
+
RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
154
+
RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
155
+
RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
156
+
RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
157
+
RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
158
+
RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
159
+
RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
160
+
RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
161
+
RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
162
162
};
163
163
164
164
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {