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dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant

The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
control the power and frequency of the GPU. This is modelled as a power
domain and clock provider.

It lets us omit the OPP tables from the device tree, as those can now be
enumerated at runtime from the MCU.

Add the necessary schema logic to handle what this SoC expects in terms
of clocks and power-domains.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://patch.msgid.link/20251017-mt8196-gpufreq-v8-1-98fc1cc566a1@collabora.com
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>

authored by

Nicolas Frattaroli and committed by
Liviu Dudau 12c069e0 67934f24

+36 -1
+36 -1
Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
··· 46 46 minItems: 1 47 47 items: 48 48 - const: core 49 - - const: coregroup 49 + - enum: 50 + - coregroup 51 + - stacks 50 52 - const: stacks 51 53 52 54 mali-supply: true ··· 113 111 power-domain-names: false 114 112 required: 115 113 - mali-supply 114 + - if: 115 + properties: 116 + compatible: 117 + contains: 118 + const: mediatek,mt8196-mali 119 + then: 120 + properties: 121 + mali-supply: false 122 + sram-supply: false 123 + operating-points-v2: false 124 + power-domains: 125 + maxItems: 1 126 + power-domain-names: false 127 + clocks: 128 + maxItems: 2 129 + clock-names: 130 + items: 131 + - const: core 132 + - const: stacks 133 + required: 134 + - power-domains 116 135 117 136 examples: 118 137 - | ··· 168 145 opp-microvolt = <675000 675000 850000>; 169 146 }; 170 147 }; 148 + }; 149 + - | 150 + gpu@48000000 { 151 + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf"; 152 + reg = <0x48000000 0x480000>; 153 + clocks = <&gpufreq 0>, <&gpufreq 1>; 154 + clock-names = "core", "stacks"; 155 + interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>, 156 + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>, 157 + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>; 158 + interrupt-names = "job", "mmu", "gpu"; 159 + power-domains = <&gpufreq>; 171 160 }; 172 161 173 162 ...