Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'tty-6.4-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty/serial driver fixes from Greg KH:
"Here are some small tty/serial driver fixes for 6.4-rc5 that have all
been in linux-next this past week with no reported problems. Included
in here are:
- 8250_tegra driver bugfix
- fsl uart driver bugfixes
- Kconfig fix for dependancy issue
- dt-bindings fix for the 8250_omap driver"
* tag 'tty-6.4-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty:
dt-bindings: serial: 8250_omap: add rs485-rts-active-high
serial: cpm_uart: Fix a COMPILE_TEST dependency
soc: fsl: cpm1: Fix TSA and QMC dependencies in case of COMPILE_TEST
tty: serial: fsl_lpuart: use UARTCTRL_TXINV to send break instead of UARTCTRL_SBK
serial: 8250_tegra: Fix an error handling path in tegra_uart_probe()
+30
-27
+1
Documentation/devicetree/bindings/serial/8250_omap.yaml
+1
Documentation/devicetree/bindings/serial/8250_omap.yaml
+2
-2
drivers/soc/fsl/qe/Kconfig
+2
-2
drivers/soc/fsl/qe/Kconfig
···
36
36
config CPM_TSA
37
37
tristate "CPM TSA support"
38
38
depends on OF && HAS_IOMEM
39
-
depends on CPM1 || COMPILE_TEST
39
+
depends on CPM1 || (CPM && COMPILE_TEST)
40
40
help
41
41
Freescale CPM Time Slot Assigner (TSA)
42
42
controller.
···
47
47
config CPM_QMC
48
48
tristate "CPM QMC support"
49
49
depends on OF && HAS_IOMEM
50
-
depends on CPM1 || (FSL_SOC && COMPILE_TEST)
50
+
depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST)
51
51
depends on CPM_TSA
52
52
help
53
53
Freescale CPM QUICC Multichannel Controller
+3
-1
drivers/tty/serial/8250/8250_tegra.c
+3
-1
drivers/tty/serial/8250/8250_tegra.c
···
113
113
114
114
ret = serial8250_register_8250_port(&port8250);
115
115
if (ret < 0)
116
-
goto err_clkdisable;
116
+
goto err_ctrl_assert;
117
117
118
118
platform_set_drvdata(pdev, uart);
119
119
uart->line = ret;
120
120
121
121
return 0;
122
122
123
+
err_ctrl_assert:
124
+
reset_control_assert(uart->rst);
123
125
err_clkdisable:
124
126
clk_disable_unprepare(uart->clk);
125
127
+1
-1
drivers/tty/serial/Kconfig
+1
-1
drivers/tty/serial/Kconfig
-2
drivers/tty/serial/cpm_uart/cpm_uart.h
-2
drivers/tty/serial/cpm_uart/cpm_uart.h
+23
-21
drivers/tty/serial/fsl_lpuart.c
+23
-21
drivers/tty/serial/fsl_lpuart.c
···
1495
1495
1496
1496
static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1497
1497
{
1498
-
unsigned long temp, modem;
1499
-
struct tty_struct *tty;
1500
-
unsigned int cflag = 0;
1498
+
unsigned long temp;
1501
1499
1502
-
tty = tty_port_tty_get(&port->state->port);
1503
-
if (tty) {
1504
-
cflag = tty->termios.c_cflag;
1505
-
tty_kref_put(tty);
1506
-
}
1500
+
temp = lpuart32_read(port, UARTCTRL);
1507
1501
1508
-
temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1509
-
modem = lpuart32_read(port, UARTMODIR);
1510
-
1502
+
/*
1503
+
* LPUART IP now has two known bugs, one is CTS has higher priority than the
1504
+
* break signal, which causes the break signal sending through UARTCTRL_SBK
1505
+
* may impacted by the CTS input if the HW flow control is enabled. It
1506
+
* exists on all platforms we support in this driver.
1507
+
* Another bug is i.MX8QM LPUART may have an additional break character
1508
+
* being sent after SBK was cleared.
1509
+
* To avoid above two bugs, we use Transmit Data Inversion function to send
1510
+
* the break signal instead of UARTCTRL_SBK.
1511
+
*/
1511
1512
if (break_state != 0) {
1512
-
temp |= UARTCTRL_SBK;
1513
1513
/*
1514
-
* LPUART CTS has higher priority than SBK, need to disable CTS before
1515
-
* asserting SBK to avoid any interference if flow control is enabled.
1514
+
* Disable the transmitter to prevent any data from being sent out
1515
+
* during break, then invert the TX line to send break.
1516
1516
*/
1517
-
if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE)
1518
-
lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR);
1517
+
temp &= ~UARTCTRL_TE;
1518
+
lpuart32_write(port, temp, UARTCTRL);
1519
+
temp |= UARTCTRL_TXINV;
1520
+
lpuart32_write(port, temp, UARTCTRL);
1519
1521
} else {
1520
-
/* Re-enable the CTS when break off. */
1521
-
if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE))
1522
-
lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR);
1522
+
/* Disable the TXINV to turn off break and re-enable transmitter. */
1523
+
temp &= ~UARTCTRL_TXINV;
1524
+
lpuart32_write(port, temp, UARTCTRL);
1525
+
temp |= UARTCTRL_TE;
1526
+
lpuart32_write(port, temp, UARTCTRL);
1523
1527
}
1524
-
1525
-
lpuart32_write(port, temp, UARTCTRL);
1526
1528
}
1527
1529
1528
1530
static void lpuart_setup_watermark(struct lpuart_port *sport)