Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'arc-4.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta:
- support IDU intc for UP builds
- support gz, lzma compressed uImage [Daniel Mentz]
- adjust /proc/cpuinfo for non-continuous cpu ids [Noam Camus]
- syscall for userspace cmpxchg assist for configs lacking hardware atomics
- rework of boot log printing mainly for identifying older arc700 cores
- retiring some old code, build toggles
* tag 'arc-4.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ARCv2: IOC: use @ioc_enable not @ioc_exist where intended
ARC: syscall for userspace cmpxchg assist
ARC: fix build warning in elf.h
ARC: Adjust cpuinfo for non-continuous cpu ids
ARC: [build] Support gz, lzma compressed uImage
ARCv2: intc: untangle SMP, MCIP and IDU
+203
-273
+11
-16
arch/arc/Kconfig
+11
-16
arch/arc/Kconfig
···
41
41
select PERF_USE_VMALLOC
42
42
select HAVE_DEBUG_STACKOVERFLOW
43
43
select HAVE_GENERIC_DMA_COHERENT
44
+
select HAVE_KERNEL_GZIP
45
+
select HAVE_KERNEL_LZMA
44
46
45
47
config MIGHT_HAVE_PCI
46
48
bool
···
188
186
config ARC_HAS_COH_CACHES
189
187
def_bool n
190
188
191
-
config ARC_MCIP
192
-
bool "ARConnect Multicore IP (MCIP) Support "
193
-
depends on ISA_ARCV2
194
-
help
195
-
This IP block enables SMP in ARC-HS38 cores.
196
-
It provides for cross-core interrupts, multi-core debug
197
-
hardware semaphores, shared memory,....
198
-
199
189
config NR_CPUS
200
190
int "Maximum number of CPUs (2-4096)"
201
191
range 2 4096
···
204
210
entry point and spin wait for Master's signal.
205
211
206
212
endif #SMP
213
+
214
+
config ARC_MCIP
215
+
bool "ARConnect Multicore IP (MCIP) Support "
216
+
depends on ISA_ARCV2
217
+
default y if SMP
218
+
help
219
+
This IP block enables SMP in ARC-HS38 cores.
220
+
It provides for cross-core interrupts, multi-core debug
221
+
hardware semaphores, shared memory,....
207
222
208
223
menuconfig ARC_CACHE
209
224
bool "Enable Cache Support"
···
539
536
config ARC_DBG_TLB_PARANOIA
540
537
bool "Paranoia Checks in Low Level TLB Handlers"
541
538
default n
542
-
543
-
config ARC_DBG_TLB_MISS_COUNT
544
-
bool "Profile TLB Misses"
545
-
default n
546
-
select DEBUG_FS
547
-
help
548
-
Counts number of I and D TLB Misses and exports them via Debugfs
549
-
The counters can be cleared via Debugfs as well
550
539
551
540
endif
552
541
-3
arch/arc/Makefile
-3
arch/arc/Makefile
+14
-2
arch/arc/boot/Makefile
+14
-2
arch/arc/boot/Makefile
···
14
14
15
15
suffix-y := bin
16
16
suffix-$(CONFIG_KERNEL_GZIP) := gz
17
+
suffix-$(CONFIG_KERNEL_LZMA) := lzma
17
18
18
-
targets += uImage uImage.bin uImage.gz
19
-
extra-y += vmlinux.bin vmlinux.bin.gz
19
+
targets += uImage
20
+
targets += uImage.bin
21
+
targets += uImage.gz
22
+
targets += uImage.lzma
23
+
extra-y += vmlinux.bin
24
+
extra-y += vmlinux.bin.gz
25
+
extra-y += vmlinux.bin.lzma
20
26
21
27
$(obj)/vmlinux.bin: vmlinux FORCE
22
28
$(call if_changed,objcopy)
···
30
24
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
31
25
$(call if_changed,gzip)
32
26
27
+
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
28
+
$(call if_changed,lzma)
29
+
33
30
$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
34
31
$(call if_changed,uimage,none)
35
32
36
33
$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
37
34
$(call if_changed,uimage,gzip)
35
+
36
+
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
37
+
$(call if_changed,uimage,lzma)
38
38
39
39
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
40
40
@ln -sf $(notdir $<) $@
+2
-1
arch/arc/include/asm/arcregs.h
+2
-1
arch/arc/include/asm/arcregs.h
···
349
349
struct cpuinfo_arc_bpu bpu;
350
350
struct bcr_identity core;
351
351
struct bcr_isa isa;
352
+
const char *details, *name;
352
353
unsigned int vec_base;
353
354
struct cpuinfo_arc_ccm iccm, dccm;
354
355
struct {
355
-
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
356
+
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
356
357
fpu_sp:1, fpu_dp:1, pad2:6,
357
358
debug:1, ap:1, smart:1, rtt:1, pad3:4,
358
359
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
+1
-1
arch/arc/include/asm/cache.h
+1
-1
arch/arc/include/asm/cache.h
+1
-1
arch/arc/include/asm/elf.h
+1
-1
arch/arc/include/asm/elf.h
···
54
54
* the loader. We need to make sure that it is out of the way of the program
55
55
* that it will "exec", and that there is sufficient room for the brk.
56
56
*/
57
-
#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
57
+
#define ELF_ET_DYN_BASE (2UL * TASK_SIZE / 3)
58
58
59
59
/*
60
60
* When the program starts, a1 contains a pointer to a function to be
+16
arch/arc/include/asm/mcip.h
+16
arch/arc/include/asm/mcip.h
···
55
55
#define IDU_M_DISTRI_DEST 0x2
56
56
};
57
57
58
+
struct mcip_bcr {
59
+
#ifdef CONFIG_CPU_BIG_ENDIAN
60
+
unsigned int pad3:8,
61
+
idu:1, llm:1, num_cores:6,
62
+
iocoh:1, gfrc:1, dbg:1, pad2:1,
63
+
msg:1, sem:1, ipi:1, pad:1,
64
+
ver:8;
65
+
#else
66
+
unsigned int ver:8,
67
+
pad:1, ipi:1, sem:1, msg:1,
68
+
pad2:1, dbg:1, gfrc:1, iocoh:1,
69
+
num_cores:6, llm:1, idu:1,
70
+
pad3:8;
71
+
#endif
72
+
};
73
+
58
74
/*
59
75
* MCIP programming model
60
76
*
+1
arch/arc/include/asm/module.h
+1
arch/arc/include/asm/module.h
+1
-5
arch/arc/include/asm/setup.h
+1
-5
arch/arc/include/asm/setup.h
···
27
27
const char *str;
28
28
};
29
29
30
-
struct cpuinfo_data {
31
-
struct id_to_str info;
32
-
int up_range;
33
-
};
34
-
35
30
extern int root_mountflags, end_mem;
36
31
37
32
void setup_processor(void);
···
38
43
#define IS_USED_RUN(v) ((v) ? "" : "(not used) ")
39
44
#define IS_USED_CFG(cfg) IS_USED_RUN(IS_ENABLED(cfg))
40
45
#define IS_AVAIL2(v, s, cfg) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg))
46
+
#define IS_AVAIL3(v, v2, s) IS_AVAIL1(v, s), IS_AVAIL1(v, IS_DISABLED_RUN(v2))
41
47
42
48
#endif /* __ASMARC_SETUP_H */
+1
arch/arc/include/asm/syscalls.h
+1
arch/arc/include/asm/syscalls.h
+5
-4
arch/arc/include/uapi/asm/unistd.h
+5
-4
arch/arc/include/uapi/asm/unistd.h
···
27
27
28
28
#define NR_syscalls __NR_syscalls
29
29
30
+
/* Generic syscall (fs/filesystems.c - lost in asm-generic/unistd.h */
31
+
#define __NR_sysfs (__NR_arch_specific_syscall + 3)
32
+
30
33
/* ARC specific syscall */
31
34
#define __NR_cacheflush (__NR_arch_specific_syscall + 0)
32
35
#define __NR_arc_settls (__NR_arch_specific_syscall + 1)
33
36
#define __NR_arc_gettls (__NR_arch_specific_syscall + 2)
37
+
#define __NR_arc_usr_cmpxchg (__NR_arch_specific_syscall + 4)
34
38
35
39
__SYSCALL(__NR_cacheflush, sys_cacheflush)
36
40
__SYSCALL(__NR_arc_settls, sys_arc_settls)
37
41
__SYSCALL(__NR_arc_gettls, sys_arc_gettls)
38
-
39
-
40
-
/* Generic syscall (fs/filesystems.c - lost in asm-generic/unistd.h */
41
-
#define __NR_sysfs (__NR_arch_specific_syscall + 3)
42
+
__SYSCALL(__NR_arc_usr_cmpxchg, sys_arc_usr_cmpxchg)
42
43
__SYSCALL(__NR_sysfs, sys_sysfs)
43
44
44
45
#undef __SYSCALL
+11
-20
arch/arc/kernel/mcip.c
+11
-20
arch/arc/kernel/mcip.c
···
15
15
#include <asm/mcip.h>
16
16
#include <asm/setup.h>
17
17
18
-
static char smp_cpuinfo_buf[128];
19
-
static int idu_detected;
20
-
21
18
static DEFINE_RAW_SPINLOCK(mcip_lock);
19
+
20
+
#ifdef CONFIG_SMP
21
+
22
+
static char smp_cpuinfo_buf[128];
22
23
23
24
static void mcip_setup_per_cpu(int cpu)
24
25
{
···
87
86
88
87
static void mcip_probe_n_setup(void)
89
88
{
90
-
struct mcip_bcr {
91
-
#ifdef CONFIG_CPU_BIG_ENDIAN
92
-
unsigned int pad3:8,
93
-
idu:1, llm:1, num_cores:6,
94
-
iocoh:1, gfrc:1, dbg:1, pad2:1,
95
-
msg:1, sem:1, ipi:1, pad:1,
96
-
ver:8;
97
-
#else
98
-
unsigned int ver:8,
99
-
pad:1, ipi:1, sem:1, msg:1,
100
-
pad2:1, dbg:1, gfrc:1, iocoh:1,
101
-
num_cores:6, llm:1, idu:1,
102
-
pad3:8;
103
-
#endif
104
-
} mp;
89
+
struct mcip_bcr mp;
105
90
106
91
READ_BCR(ARC_REG_MCIP_BCR, mp);
107
92
···
101
114
IS_AVAIL1(mp.gfrc, "GFRC"));
102
115
103
116
cpuinfo_arc700[0].extn.gfrc = mp.gfrc;
104
-
idu_detected = mp.idu;
105
117
106
118
if (mp.dbg) {
107
119
__mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf);
···
115
129
.ipi_send = mcip_ipi_send,
116
130
.ipi_clear = mcip_ipi_clear,
117
131
};
132
+
133
+
#endif
118
134
119
135
/***************************************************************************
120
136
* ARCv2 Interrupt Distribution Unit (IDU)
···
283
295
/* Read IDU BCR to confirm nr_irqs */
284
296
int nr_irqs = of_irq_count(intc);
285
297
int i, irq;
298
+
struct mcip_bcr mp;
286
299
287
-
if (!idu_detected)
300
+
READ_BCR(ARC_REG_MCIP_BCR, mp);
301
+
302
+
if (!mp.idu)
288
303
panic("IDU not detected, but DeviceTree using it");
289
304
290
305
pr_info("MCIP: IDU referenced from Devicetree %d irqs\n", nr_irqs);
+28
-23
arch/arc/kernel/module.c
+28
-23
arch/arc/kernel/module.c
···
30
30
char *secstr, struct module *mod)
31
31
{
32
32
#ifdef CONFIG_ARC_DW2_UNWIND
33
-
int i;
34
-
35
33
mod->arch.unw_sec_idx = 0;
36
34
mod->arch.unw_info = NULL;
37
-
38
-
for (i = 1; i < hdr->e_shnum; i++) {
39
-
if (strcmp(secstr+sechdrs[i].sh_name, ".eh_frame") == 0) {
40
-
mod->arch.unw_sec_idx = i;
41
-
break;
42
-
}
43
-
}
35
+
mod->arch.secstr = secstr;
44
36
#endif
45
37
return 0;
46
38
}
···
51
59
unsigned int relsec, /* sec index for relo sec */
52
60
struct module *module)
53
61
{
54
-
int i, n;
62
+
int i, n, relo_type;
55
63
Elf32_Rela *rel_entry = (void *)sechdrs[relsec].sh_addr;
56
64
Elf32_Sym *sym_entry, *sym_sec;
57
-
Elf32_Addr relocation;
58
-
Elf32_Addr location;
59
-
Elf32_Addr sec_to_patch;
60
-
int relo_type;
65
+
Elf32_Addr relocation, location, tgt_addr;
66
+
unsigned int tgtsec;
61
67
62
-
sec_to_patch = sechdrs[sechdrs[relsec].sh_info].sh_addr;
68
+
/*
69
+
* @relsec has relocations e.g. .rela.init.text
70
+
* @tgtsec is section to patch e.g. .init.text
71
+
*/
72
+
tgtsec = sechdrs[relsec].sh_info;
73
+
tgt_addr = sechdrs[tgtsec].sh_addr;
63
74
sym_sec = (Elf32_Sym *) sechdrs[symindex].sh_addr;
64
75
n = sechdrs[relsec].sh_size / sizeof(*rel_entry);
65
76
66
-
pr_debug("\n========== Module Sym reloc ===========================\n");
67
-
pr_debug("Section to fixup %x\n", sec_to_patch);
77
+
pr_debug("\nSection to fixup %s @%x\n",
78
+
module->arch.secstr + sechdrs[tgtsec].sh_name, tgt_addr);
68
79
pr_debug("=========================================================\n");
69
-
pr_debug("rela->r_off | rela->addend | sym->st_value | ADDR | VALUE\n");
80
+
pr_debug("r_off\tr_add\tst_value ADDRESS VALUE\n");
70
81
pr_debug("=========================================================\n");
71
82
72
83
/* Loop thru entries in relocation section */
73
84
for (i = 0; i < n; i++) {
85
+
const char *s;
74
86
75
87
/* This is where to make the change */
76
-
location = sec_to_patch + rel_entry[i].r_offset;
88
+
location = tgt_addr + rel_entry[i].r_offset;
77
89
78
90
/* This is the symbol it is referring to. Note that all
79
91
undefined symbols have been resolved. */
···
85
89
86
90
relocation = sym_entry->st_value + rel_entry[i].r_addend;
87
91
88
-
pr_debug("\t%x\t\t%x\t\t%x %x %x [%s]\n",
89
-
rel_entry[i].r_offset, rel_entry[i].r_addend,
90
-
sym_entry->st_value, location, relocation,
91
-
strtab + sym_entry->st_name);
92
+
if (sym_entry->st_name == 0 && ELF_ST_TYPE (sym_entry->st_info) == STT_SECTION) {
93
+
s = module->arch.secstr + sechdrs[sym_entry->st_shndx].sh_name;
94
+
} else {
95
+
s = strtab + sym_entry->st_name;
96
+
}
97
+
98
+
pr_debug(" %x\t%x\t%x %x %x [%s]\n",
99
+
rel_entry[i].r_offset, rel_entry[i].r_addend,
100
+
sym_entry->st_value, location, relocation, s);
92
101
93
102
/* This assumes modules are built with -mlong-calls
94
103
* so any branches/jumps are absolute 32 bit jmps
···
112
111
goto relo_err;
113
112
114
113
}
114
+
115
+
if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0)
116
+
module->arch.unw_sec_idx = tgtsec;
117
+
115
118
return 0;
116
119
117
120
relo_err:
+33
arch/arc/kernel/process.c
+33
arch/arc/kernel/process.c
···
41
41
return task_thread_info(current)->thr_ptr;
42
42
}
43
43
44
+
SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new)
45
+
{
46
+
int uval;
47
+
int ret;
48
+
49
+
/*
50
+
* This is only for old cores lacking LLOCK/SCOND, which by defintion
51
+
* can't possibly be SMP. Thus doesn't need to be SMP safe.
52
+
* And this also helps reduce the overhead for serializing in
53
+
* the UP case
54
+
*/
55
+
WARN_ON_ONCE(IS_ENABLED(CONFIG_SMP));
56
+
57
+
if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
58
+
return -EFAULT;
59
+
60
+
preempt_disable();
61
+
62
+
ret = __get_user(uval, uaddr);
63
+
if (ret)
64
+
goto done;
65
+
66
+
if (uval != expected)
67
+
ret = -EAGAIN;
68
+
else
69
+
ret = __put_user(new, uaddr);
70
+
71
+
done:
72
+
preempt_enable();
73
+
74
+
return ret;
75
+
}
76
+
44
77
void arch_cpu_idle(void)
45
78
{
46
79
/* sleep, but enable all interrupts before committing */
+64
-51
arch/arc/kernel/setup.c
+64
-51
arch/arc/kernel/setup.c
···
40
40
41
41
struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
42
42
43
+
static const struct id_to_str arc_cpu_rel[] = {
44
+
#ifdef CONFIG_ISA_ARCOMPACT
45
+
{ 0x34, "R4.10"},
46
+
{ 0x35, "R4.11"},
47
+
#else
48
+
{ 0x51, "R2.0" },
49
+
{ 0x52, "R2.1" },
50
+
{ 0x53, "R3.0" },
51
+
#endif
52
+
{ 0x00, NULL }
53
+
};
54
+
55
+
static const struct id_to_str arc_cpu_nm[] = {
56
+
#ifdef CONFIG_ISA_ARCOMPACT
57
+
{ 0x20, "ARC 600" },
58
+
{ 0x30, "ARC 770" }, /* 750 identified seperately */
59
+
#else
60
+
{ 0x40, "ARC EM" },
61
+
{ 0x50, "ARC HS38" },
62
+
#endif
63
+
{ 0x00, "Unknown" }
64
+
};
65
+
43
66
static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
44
67
{
45
68
if (is_isa_arcompact()) {
···
115
92
struct bcr_timer timer;
116
93
struct bcr_generic bcr;
117
94
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
95
+
const struct id_to_str *tbl;
96
+
118
97
FIX_PTR(cpu);
119
98
120
99
READ_BCR(AUX_IDENTITY, cpu->core);
121
100
READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
101
+
102
+
for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
103
+
if (cpu->core.family == tbl->id) {
104
+
cpu->details = tbl->str;
105
+
break;
106
+
}
107
+
}
108
+
109
+
for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
110
+
if ((cpu->core.family & 0xF0) == tbl->id)
111
+
break;
112
+
}
113
+
cpu->name = tbl->str;
122
114
123
115
READ_BCR(ARC_REG_TIMERS_BCR, timer);
124
116
cpu->extn.timer0 = timer.t0;
···
149
111
cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
150
112
cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
151
113
cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
114
+
cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 :
115
+
IS_ENABLED(CONFIG_ARC_HAS_SWAPE);
116
+
152
117
READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
153
118
154
119
/* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
···
201
160
cpu->extn.rtt = bcr.ver ? 1 : 0;
202
161
203
162
cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
163
+
164
+
/* some hacks for lack of feature BCR info in old ARC700 cores */
165
+
if (is_isa_arcompact()) {
166
+
if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
167
+
cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
168
+
else
169
+
cpu->isa.atomic = cpu->isa.atomic1;
170
+
171
+
cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
172
+
173
+
/* there's no direct way to distinguish 750 vs. 770 */
174
+
if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
175
+
cpu->name = "ARC750";
176
+
}
204
177
}
205
-
206
-
static const struct cpuinfo_data arc_cpu_tbl[] = {
207
-
#ifdef CONFIG_ISA_ARCOMPACT
208
-
{ {0x20, "ARC 600" }, 0x2F},
209
-
{ {0x30, "ARC 700" }, 0x33},
210
-
{ {0x34, "ARC 700 R4.10"}, 0x34},
211
-
{ {0x35, "ARC 700 R4.11"}, 0x35},
212
-
#else
213
-
{ {0x50, "ARC HS38 R2.0"}, 0x51},
214
-
{ {0x52, "ARC HS38 R2.1"}, 0x52},
215
-
{ {0x53, "ARC HS38 R3.0"}, 0x53},
216
-
#endif
217
-
{ {0x00, NULL } }
218
-
};
219
-
220
178
221
179
static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
222
180
{
223
181
struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
224
182
struct bcr_identity *core = &cpu->core;
225
-
const struct cpuinfo_data *tbl;
226
-
char *isa_nm;
227
-
int i, be, atomic;
228
-
int n = 0;
183
+
int i, n = 0;
229
184
230
185
FIX_PTR(cpu);
231
-
232
-
if (is_isa_arcompact()) {
233
-
isa_nm = "ARCompact";
234
-
be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
235
-
236
-
atomic = cpu->isa.atomic1;
237
-
if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
238
-
atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
239
-
} else {
240
-
isa_nm = "ARCv2";
241
-
be = cpu->isa.be;
242
-
atomic = cpu->isa.atomic;
243
-
}
244
186
245
187
n += scnprintf(buf + n, len - n,
246
188
"\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
247
189
core->family, core->cpu_id, core->chip_id);
248
190
249
-
for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
250
-
if ((core->family >= tbl->info.id) &&
251
-
(core->family <= tbl->up_range)) {
252
-
n += scnprintf(buf + n, len - n,
253
-
"processor [%d]\t: %s (%s ISA) %s\n",
254
-
cpu_id, tbl->info.str, isa_nm,
255
-
IS_AVAIL1(be, "[Big-Endian]"));
256
-
break;
257
-
}
258
-
}
259
-
260
-
if (tbl->info.id == 0)
261
-
n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
191
+
n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
192
+
cpu_id, cpu->name, cpu->details,
193
+
is_isa_arcompact() ? "ARCompact" : "ARCv2",
194
+
IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
262
195
263
196
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
264
197
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
···
241
226
CONFIG_ARC_HAS_RTC));
242
227
243
228
n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
244
-
IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
229
+
IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
245
230
IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
246
231
IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
247
232
···
268
253
IS_AVAIL1(cpu->extn.swap, "swap "),
269
254
IS_AVAIL1(cpu->extn.minmax, "minmax "),
270
255
IS_AVAIL1(cpu->extn.crc, "crc "),
271
-
IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
256
+
IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE));
272
257
273
258
if (cpu->bpu.ver)
274
259
n += scnprintf(buf + n, len - n,
···
287
272
288
273
FIX_PTR(cpu);
289
274
290
-
n += scnprintf(buf + n, len - n,
291
-
"Vector Table\t: %#x\nPeripherals\t: %#lx:%#lx\n",
292
-
cpu->vec_base, perip_base, perip_end);
275
+
n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
293
276
294
277
if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
295
278
n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
···
520
507
* way to pass it w/o having to kmalloc/free a 2 byte string.
521
508
* Encode cpu-id as 0xFFcccc, which is decoded by show routine.
522
509
*/
523
-
return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
510
+
return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
524
511
}
525
512
526
513
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
-110
arch/arc/kernel/troubleshoot.c
-110
arch/arc/kernel/troubleshoot.c
···
237
237
if (!user_mode(regs))
238
238
show_stacktrace(current, regs);
239
239
}
240
-
241
-
#ifdef CONFIG_DEBUG_FS
242
-
243
-
#include <linux/module.h>
244
-
#include <linux/fs.h>
245
-
#include <linux/mount.h>
246
-
#include <linux/pagemap.h>
247
-
#include <linux/init.h>
248
-
#include <linux/namei.h>
249
-
#include <linux/debugfs.h>
250
-
251
-
static struct dentry *test_dentry;
252
-
static struct dentry *test_dir;
253
-
static struct dentry *test_u32_dentry;
254
-
255
-
static u32 clr_on_read = 1;
256
-
257
-
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
258
-
u32 numitlb, numdtlb, num_pte_not_present;
259
-
260
-
static int fill_display_data(char *kbuf)
261
-
{
262
-
size_t num = 0;
263
-
num += sprintf(kbuf + num, "I-TLB Miss %x\n", numitlb);
264
-
num += sprintf(kbuf + num, "D-TLB Miss %x\n", numdtlb);
265
-
num += sprintf(kbuf + num, "PTE not present %x\n", num_pte_not_present);
266
-
267
-
if (clr_on_read)
268
-
numitlb = numdtlb = num_pte_not_present = 0;
269
-
270
-
return num;
271
-
}
272
-
273
-
static int tlb_stats_open(struct inode *inode, struct file *file)
274
-
{
275
-
file->private_data = (void *)__get_free_page(GFP_KERNEL);
276
-
return 0;
277
-
}
278
-
279
-
/* called on user read(): display the counters */
280
-
static ssize_t tlb_stats_output(struct file *file, /* file descriptor */
281
-
char __user *user_buf, /* user buffer */
282
-
size_t len, /* length of buffer */
283
-
loff_t *offset) /* offset in the file */
284
-
{
285
-
size_t num;
286
-
char *kbuf = (char *)file->private_data;
287
-
288
-
/* All of the data can he shoved in one iteration */
289
-
if (*offset != 0)
290
-
return 0;
291
-
292
-
num = fill_display_data(kbuf);
293
-
294
-
/* simple_read_from_buffer() is helper for copy to user space
295
-
It copies up to @2 (num) bytes from kernel buffer @4 (kbuf) at offset
296
-
@3 (offset) into the user space address starting at @1 (user_buf).
297
-
@5 (len) is max size of user buffer
298
-
*/
299
-
return simple_read_from_buffer(user_buf, num, offset, kbuf, len);
300
-
}
301
-
302
-
/* called on user write : clears the counters */
303
-
static ssize_t tlb_stats_clear(struct file *file, const char __user *user_buf,
304
-
size_t length, loff_t *offset)
305
-
{
306
-
numitlb = numdtlb = num_pte_not_present = 0;
307
-
return length;
308
-
}
309
-
310
-
static int tlb_stats_close(struct inode *inode, struct file *file)
311
-
{
312
-
free_page((unsigned long)(file->private_data));
313
-
return 0;
314
-
}
315
-
316
-
static const struct file_operations tlb_stats_file_ops = {
317
-
.read = tlb_stats_output,
318
-
.write = tlb_stats_clear,
319
-
.open = tlb_stats_open,
320
-
.release = tlb_stats_close
321
-
};
322
-
#endif
323
-
324
-
static int __init arc_debugfs_init(void)
325
-
{
326
-
test_dir = debugfs_create_dir("arc", NULL);
327
-
328
-
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
329
-
test_dentry = debugfs_create_file("tlb_stats", 0444, test_dir, NULL,
330
-
&tlb_stats_file_ops);
331
-
#endif
332
-
333
-
test_u32_dentry =
334
-
debugfs_create_u32("clr_on_read", 0444, test_dir, &clr_on_read);
335
-
336
-
return 0;
337
-
}
338
-
339
-
module_init(arc_debugfs_init);
340
-
341
-
static void __exit arc_debugfs_exit(void)
342
-
{
343
-
debugfs_remove(test_u32_dentry);
344
-
debugfs_remove(test_dentry);
345
-
debugfs_remove(test_dir);
346
-
}
347
-
module_exit(arc_debugfs_exit);
348
-
349
-
#endif
+9
-10
arch/arc/mm/cache.c
+9
-10
arch/arc/mm/cache.c
···
22
22
#include <asm/setup.h>
23
23
24
24
static int l2_line_sz;
25
-
int ioc_exists;
26
-
volatile int slc_enable = 1, ioc_enable = 1;
25
+
static int ioc_exists;
26
+
int slc_enable = 1, ioc_enable = 1;
27
27
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
28
28
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
29
29
···
53
53
PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache");
54
54
PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache");
55
55
56
-
if (!is_isa_arcv2())
57
-
return buf;
58
-
59
56
p = &cpuinfo_arc700[c].slc;
60
57
if (p->ver)
61
58
n += scnprintf(buf + n, len - n,
62
59
"SLC\t\t: %uK, %uB Line%s\n",
63
60
p->sz_k, p->line_len, IS_USED_RUN(slc_enable));
64
61
65
-
if (ioc_exists)
66
-
n += scnprintf(buf + n, len - n, "IOC\t\t:%s\n",
67
-
IS_DISABLED_RUN(ioc_enable));
62
+
n += scnprintf(buf + n, len - n, "Peripherals\t: %#lx%s%s\n",
63
+
perip_base,
64
+
IS_AVAIL3(ioc_exists, ioc_enable, ", IO-Coherency "));
68
65
69
66
return buf;
70
67
}
···
110
113
}
111
114
112
115
READ_BCR(ARC_REG_CLUSTER_BCR, cbcr);
113
-
if (cbcr.c && ioc_enable)
116
+
if (cbcr.c)
114
117
ioc_exists = 1;
118
+
else
119
+
ioc_enable = 0;
115
120
116
121
/* HS 2.0 didn't have AUX_VOL */
117
122
if (cpuinfo_arc700[cpu].core.family > 0x51) {
···
1001
1002
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
1002
1003
}
1003
1004
1004
-
if (is_isa_arcv2() && ioc_exists) {
1005
+
if (is_isa_arcv2() && ioc_enable) {
1005
1006
/* IO coherency base - 0x8z */
1006
1007
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
1007
1008
/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
+2
-2
arch/arc/mm/dma.c
+2
-2
arch/arc/mm/dma.c
···
45
45
* -For coherent data, Read/Write to buffers terminate early in cache
46
46
* (vs. always going to memory - thus are faster)
47
47
*/
48
-
if ((is_isa_arcv2() && ioc_exists) ||
48
+
if ((is_isa_arcv2() && ioc_enable) ||
49
49
(attrs & DMA_ATTR_NON_CONSISTENT))
50
50
need_coh = 0;
51
51
···
97
97
int is_non_coh = 1;
98
98
99
99
is_non_coh = (attrs & DMA_ATTR_NON_CONSISTENT) ||
100
-
(is_isa_arcv2() && ioc_exists);
100
+
(is_isa_arcv2() && ioc_enable);
101
101
102
102
if (PageHighMem(page) || !is_non_coh)
103
103
iounmap((void __force __iomem *)vaddr);
+3
-3
arch/arc/mm/tlb.c
+3
-3
arch/arc/mm/tlb.c
···
793
793
char super_pg[64] = "";
794
794
795
795
if (p_mmu->s_pg_sz_m)
796
-
scnprintf(super_pg, 64, "%dM Super Page%s, ",
796
+
scnprintf(super_pg, 64, "%dM Super Page %s",
797
797
p_mmu->s_pg_sz_m,
798
798
IS_USED_CFG(CONFIG_TRANSPARENT_HUGEPAGE));
799
799
800
800
n += scnprintf(buf + n, len - n,
801
-
"MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s%s\n",
801
+
"MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d%s%s\n",
802
802
p_mmu->ver, p_mmu->pg_sz_k, super_pg,
803
803
p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
804
804
p_mmu->u_dtlb, p_mmu->u_itlb,
805
-
IS_AVAIL2(p_mmu->pae, "PAE40 ", CONFIG_ARC_HAS_PAE40));
805
+
IS_AVAIL2(p_mmu->pae, ", PAE40 ", CONFIG_ARC_HAS_PAE40));
806
806
807
807
return buf;
808
808
}
-21
arch/arc/mm/tlbex.S
-21
arch/arc/mm/tlbex.S
···
237
237
238
238
2:
239
239
240
-
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
241
-
and.f 0, r0, _PAGE_PRESENT
242
-
bz 1f
243
-
ld r3, [num_pte_not_present]
244
-
add r3, r3, 1
245
-
st r3, [num_pte_not_present]
246
-
1:
247
-
#endif
248
-
249
240
.endm
250
241
251
242
;-----------------------------------------------------------------
···
300
309
301
310
TLBMISS_FREEUP_REGS
302
311
303
-
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
304
-
ld r0, [@numitlb]
305
-
add r0, r0, 1
306
-
st r0, [@numitlb]
307
-
#endif
308
-
309
312
;----------------------------------------------------------------
310
313
; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
311
314
LOAD_FAULT_PTE
···
333
348
ENTRY(EV_TLBMissD)
334
349
335
350
TLBMISS_FREEUP_REGS
336
-
337
-
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
338
-
ld r0, [@numdtlb]
339
-
add r0, r0, 1
340
-
st r0, [@numdtlb]
341
-
#endif
342
351
343
352
;----------------------------------------------------------------
344
353
; Get the PTE corresponding to V-addr accessed