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perf jevents: Add mem_bw metric for Intel

Break down memory bandwidth using uncore counters. For many models
this matches the memory_bandwidth_* metrics, but these metrics aren't
made available on all models.

Add support for free running counters. Query the event JSON when
determining which what events/counters are available.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

authored by

Ian Rogers and committed by
Arnaldo Carvalho de Melo 130f4245 426b8442

+62
+62
tools/perf/pmu-events/intel_metrics.py
··· 815 815 ], description="Breakdown of load/store instructions") 816 816 817 817 818 + def UncoreMemBw() -> Optional[MetricGroup]: 819 + mem_events = [] 820 + try: 821 + mem_events = json.load(open(f"{os.path.dirname(os.path.realpath(__file__))}" 822 + f"/arch/x86/{args.model}/uncore-memory.json")) 823 + except: 824 + pass 825 + 826 + ddr_rds = 0 827 + ddr_wrs = 0 828 + ddr_total = 0 829 + for x in mem_events: 830 + if "EventName" in x: 831 + name = x["EventName"] 832 + if re.search("^UNC_MC[0-9]+_RDCAS_COUNT_FREERUN", name): 833 + ddr_rds += Event(name) 834 + elif re.search("^UNC_MC[0-9]+_WRCAS_COUNT_FREERUN", name): 835 + ddr_wrs += Event(name) 836 + # elif re.search("^UNC_MC[0-9]+_TOTAL_REQCOUNT_FREERUN", name): 837 + # ddr_total += Event(name) 838 + 839 + if ddr_rds == 0: 840 + try: 841 + ddr_rds = Event("UNC_M_CAS_COUNT.RD") 842 + ddr_wrs = Event("UNC_M_CAS_COUNT.WR") 843 + except: 844 + return None 845 + 846 + ddr_total = ddr_rds + ddr_wrs 847 + 848 + pmm_rds = 0 849 + pmm_wrs = 0 850 + try: 851 + pmm_rds = Event("UNC_M_PMM_RPQ_INSERTS") 852 + pmm_wrs = Event("UNC_M_PMM_WPQ_INSERTS") 853 + except: 854 + pass 855 + 856 + pmm_total = pmm_rds + pmm_wrs 857 + 858 + scale = 64 / 1_000_000 859 + return MetricGroup("lpm_mem_bw", [ 860 + MetricGroup("lpm_mem_bw_ddr", [ 861 + Metric("lpm_mem_bw_ddr_read", "DDR memory read bandwidth", 862 + d_ratio(ddr_rds, interval_sec), f"{scale}MB/s"), 863 + Metric("lpm_mem_bw_ddr_write", "DDR memory write bandwidth", 864 + d_ratio(ddr_wrs, interval_sec), f"{scale}MB/s"), 865 + Metric("lpm_mem_bw_ddr_total", "DDR memory write bandwidth", 866 + d_ratio(ddr_total, interval_sec), f"{scale}MB/s"), 867 + ], description="DDR Memory Bandwidth"), 868 + MetricGroup("lpm_mem_bw_pmm", [ 869 + Metric("lpm_mem_bw_pmm_read", "PMM memory read bandwidth", 870 + d_ratio(pmm_rds, interval_sec), f"{scale}MB/s"), 871 + Metric("lpm_mem_bw_pmm_write", "PMM memory write bandwidth", 872 + d_ratio(pmm_wrs, interval_sec), f"{scale}MB/s"), 873 + Metric("lpm_mem_bw_pmm_total", "PMM memory write bandwidth", 874 + d_ratio(pmm_total, interval_sec), f"{scale}MB/s"), 875 + ], description="PMM Memory Bandwidth") if pmm_rds != 0 else None, 876 + ], description="Memory Bandwidth") 877 + 878 + 818 879 def main() -> None: 819 880 global _args 820 881 ··· 914 853 IntelMlp(), 915 854 IntelPorts(), 916 855 IntelSwpf(), 856 + UncoreMemBw(), 917 857 ]) 918 858 919 859 if _args.metricgroups: