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drm/amd/display: move memory latency update to dml for dcn42

Memory latencies are soc specific and should be part of dml soc
bounding box. This change removes them from clk_mgr and has
latency update happen based on memory type when dml socbb is being
updated.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Dmytro Laktyushkin and committed by
Alex Deucher 136d15b0 35540804

+4 -78
-78
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
··· 611 611 612 612 }; 613 613 614 - static struct wm_table ddr5_wm_table = { 615 - .entries = { 616 - { 617 - .wm_inst = WM_A, 618 - .wm_type = WM_TYPE_PSTATE_CHG, 619 - .pstate_latency_us = 11.72, 620 - .sr_exit_time_us = 28.0, 621 - .sr_enter_plus_exit_time_us = 30.0, 622 - .valid = true, 623 - }, 624 - { 625 - .wm_inst = WM_B, 626 - .wm_type = WM_TYPE_PSTATE_CHG, 627 - .pstate_latency_us = 11.72, 628 - .sr_exit_time_us = 28.0, 629 - .sr_enter_plus_exit_time_us = 30.0, 630 - .valid = true, 631 - }, 632 - { 633 - .wm_inst = WM_C, 634 - .wm_type = WM_TYPE_PSTATE_CHG, 635 - .pstate_latency_us = 11.72, 636 - .sr_exit_time_us = 28.0, 637 - .sr_enter_plus_exit_time_us = 30.0, 638 - .valid = true, 639 - }, 640 - { 641 - .wm_inst = WM_D, 642 - .wm_type = WM_TYPE_PSTATE_CHG, 643 - .pstate_latency_us = 11.72, 644 - .sr_exit_time_us = 28.0, 645 - .sr_enter_plus_exit_time_us = 30.0, 646 - .valid = true, 647 - }, 648 - } 649 - }; 650 - 651 - static struct wm_table lpddr5_wm_table = { 652 - .entries = { 653 - { 654 - .wm_inst = WM_A, 655 - .wm_type = WM_TYPE_PSTATE_CHG, 656 - .pstate_latency_us = 11.65333, 657 - .sr_exit_time_us = 28.0, 658 - .sr_enter_plus_exit_time_us = 30.0, 659 - .valid = true, 660 - }, 661 - { 662 - .wm_inst = WM_B, 663 - .wm_type = WM_TYPE_PSTATE_CHG, 664 - .pstate_latency_us = 11.65333, 665 - .sr_exit_time_us = 28.0, 666 - .sr_enter_plus_exit_time_us = 30.0, 667 - .valid = true, 668 - }, 669 - { 670 - .wm_inst = WM_C, 671 - .wm_type = WM_TYPE_PSTATE_CHG, 672 - .pstate_latency_us = 11.65333, 673 - .sr_exit_time_us = 28.0, 674 - .sr_enter_plus_exit_time_us = 30.0, 675 - .valid = true, 676 - }, 677 - { 678 - .wm_inst = WM_D, 679 - .wm_type = WM_TYPE_PSTATE_CHG, 680 - .pstate_latency_us = 11.65333, 681 - .sr_exit_time_us = 28.0, 682 - .sr_enter_plus_exit_time_us = 30.0, 683 - .valid = true, 684 - }, 685 - } 686 - }; 687 - 688 614 struct dcn42_ss_info_table dcn42_ss_info_table = { 689 615 .ss_divider = 1000, 690 616 .ss_percentage = {0, 0, 375, 375, 375} ··· 1067 1141 if (ctx->dc_bios->integrated_info) { 1068 1142 clk_mgr->base.base.dentist_vco_freq_khz = ctx->dc_bios->integrated_info->dentist_vco_freq; 1069 1143 1070 - if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) 1071 - dcn42_bw_params.wm_table = lpddr5_wm_table; 1072 - else 1073 - dcn42_bw_params.wm_table = ddr5_wm_table; 1074 1144 dcn42_bw_params.vram_type = ctx->dc_bios->integrated_info->memory_type; 1075 1145 dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; 1076 1146 dcn42_bw_params.num_channels = ctx->dc_bios->integrated_info->ma_channel_number ? ctx->dc_bios->integrated_info->ma_channel_number : 1;
+4
drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
··· 155 155 dcn42_convert_dc_clock_table_to_soc_bb_clock_table(&soc_bb->clk_table, &soc_bb->vmin_limit, 156 156 dc->clk_mgr->bw_params); 157 157 } 158 + 159 + if (dc->clk_mgr->bw_params->vram_type == Ddr5MemType) { 160 + soc_bb->power_management_parameters = dcn42_ddr5_power_management_parameters; 161 + } 158 162 } 159 163 160 164 static void apply_soc_bb_updates(struct dml2_soc_bb *soc_bb, const struct dc *dc, const struct dml2_configuration_options *config)