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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: move features out of the DPU_HW_BLK_INFO
As features bits are now unused by some of the hardware block
configuration structures, remove the 'features' from the DPU_HW_BLK_INFO
so that it doesn't get included into hw info structures by default and
only include it when necessary.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655420/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-30-3b2085a07884@oss.qualcomm.com
authored by
Dmitry Baryshkov
and committed by
Dmitry Baryshkov
139d9964
3d6cce0b
+13
-20
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+7
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+7
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
···
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* @id: enum identifying this block
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* @base: register base offset to mdss
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* @len: length of hardware block
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-
* @features bit mask identifying sub-blocks/features
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*/
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#define DPU_HW_BLK_INFO \
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char name[DPU_HW_BLK_NAME_LEN]; \
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u32 id; \
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u32 base; \
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-
u32 len; \
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-
unsigned long features
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+
u32 len
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/**
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* struct dpu_scaler_blk: Scaler information
···
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/* struct dpu_mdp_cfg : MDP TOP-BLK instance info
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* @id: index identifying this block
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* @base: register base offset to mdss
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-
* @features bit mask identifying sub-blocks/features
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* @clk_ctrls clock control register definition
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*/
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struct dpu_mdp_cfg {
···
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*/
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struct dpu_ctl_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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unsigned int intr_start;
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};
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···
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*/
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struct dpu_sspp_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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const struct dpu_sspp_sub_blks *sblk;
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u32 xin_id;
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enum dpu_clk_ctrl_type clk_ctrl;
···
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*/
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struct dpu_lm_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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const struct dpu_lm_sub_blks *sblk;
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u32 pingpong;
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u32 dspp;
···
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* struct dpu_dspp_cfg - information of DSPP blocks
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* @id enum identifying this block
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* @base register offset of this block
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-
* @features bit mask identifying sub-blocks/features
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* supported by this block
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* @sblk sub-blocks information
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*/
···
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* struct dpu_pingpong_cfg - information of PING-PONG blocks
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* @id enum identifying this block
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* @base register offset of this block
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-
* @features bit mask identifying sub-blocks/features
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* @intr_done: index for PINGPONG done interrupt
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* @intr_rdptr: index for PINGPONG readpointer done interrupt
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* @sblk sub-blocks information
···
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* struct dpu_merge_3d_cfg - information of DSPP blocks
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* @id enum identifying this block
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* @base register offset of this block
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-
* @features bit mask identifying sub-blocks/features
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-
* supported by this block
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* @sblk sub-blocks information
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*/
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struct dpu_merge_3d_cfg {
···
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*/
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struct dpu_dsc_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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const struct dpu_dsc_sub_blks *sblk;
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};
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···
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* struct dpu_intf_cfg - information of timing engine blocks
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* @id enum identifying this block
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* @base register offset of this block
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-
* @features bit mask identifying sub-blocks/features
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* @type: Interface type(DSI, DP, HDMI)
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* @controller_id: Controller Instance ID in case of multiple of intf type
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* @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
···
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*/
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struct dpu_wb_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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u8 vbif_idx;
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u32 maxlinewidth;
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u32 xin_id;
···
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*/
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struct dpu_vbif_cfg {
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DPU_HW_BLK_INFO;
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+
unsigned long features;
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u32 default_ot_rd_limit;
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u32 default_ot_wr_limit;
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u32 xin_halt_timeout;
···
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* @name string name for debug purposes
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* @id enum identifying this block
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* @base register offset of this block
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-
* @features bit mask identifying sub-blocks/features
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*/
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struct dpu_cdm_cfg {
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DPU_HW_BLK_INFO;
+2
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
+2
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
···
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DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);
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}
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-
static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
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-
const unsigned long features)
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static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops)
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{
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ops->dsc_disable = dpu_hw_dsc_disable_1_2;
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ops->dsc_config = dpu_hw_dsc_config_1_2;
···
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c->idx = cfg->id;
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c->caps = cfg;
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-
_setup_dcs_ops_1_2(&c->ops, c->caps->features);
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+
_setup_dcs_ops_1_2(&c->ops);
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return c;
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}
+2
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
+2
-3
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
···
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}
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}
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-
static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,
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-
unsigned long features)
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+
static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c)
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{
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c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
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};
···
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c->idx = cfg->id;
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c->caps = cfg;
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-
_setup_merge_3d_ops(c, c->caps->features);
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+
_setup_merge_3d_ops(c);
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return c;
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}
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+2
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
···
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}
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static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
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-
unsigned long cap, const struct dpu_mdss_version *mdss_rev)
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const struct dpu_mdss_version *mdss_rev)
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{
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ops->setup_split_pipe = dpu_hw_setup_split_pipe;
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ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
···
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* Assign ops
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*/
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mdp->caps = cfg;
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-
_setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev);
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_setup_mdp_ops(&mdp->ops, mdss_rev);
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return mdp;
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}