Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin:
Blackfin: debug-mmrs: include RSI_PID[4567] MMRs
Blackfin: bf51x: fix up RSI_PID# MMR defines
Blackfin: bf52x/bf54x: fix up usb MMR defines
Blackfin: debug-mmrs: fix typos with gptimers/mdma/ppi
Blackfin: gptimers: add structure for hardware register layout
Blackfin: wire up new sendmmsg syscall
Blackfin: mach/bfin_serial_5xx.h: punt now-unused header
Blackfin: bfin_serial.h: turn default port wrappers into stubs
+62
-569
+3
-3
arch/blackfin/include/asm/bfin_serial.h
+3
-3
arch/blackfin/include/asm/bfin_serial.h
···
184
184
#undef __BFP
185
185
186
186
#ifndef port_membase
187
-
# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
187
+
# define port_membase(p) 0
188
188
#endif
189
189
190
190
#define UART_GET_CHAR(p) bfin_read16(port_membase(p) + OFFSET_RBR)
···
235
235
#define UART_SET_DLAB(p) do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
236
236
237
237
#ifndef put_lsr_cache
238
-
# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
238
+
# define put_lsr_cache(p, v)
239
239
#endif
240
240
#ifndef get_lsr_cache
241
-
# define get_lsr_cache(p) (((struct bfin_serial_port *)(p))->lsr)
241
+
# define get_lsr_cache(p) 0
242
242
#endif
243
243
244
244
/* The hardware clears the LSR bits upon read, so we need to cache
+18
arch/blackfin/include/asm/gptimers.h
+18
arch/blackfin/include/asm/gptimers.h
···
193
193
uint32_t get_gptimer_status(unsigned int group);
194
194
void set_gptimer_status(unsigned int group, uint32_t value);
195
195
196
+
/*
197
+
* All Blackfin system MMRs are padded to 32bits even if the register
198
+
* itself is only 16bits. So use a helper macro to streamline this.
199
+
*/
200
+
#define __BFP(m) u16 m; u16 __pad_##m
201
+
202
+
/*
203
+
* bfin timer registers layout
204
+
*/
205
+
struct bfin_gptimer_regs {
206
+
__BFP(config);
207
+
u32 counter;
208
+
u32 period;
209
+
u32 width;
210
+
};
211
+
212
+
#undef __BFP
213
+
196
214
#endif
+2
-1
arch/blackfin/include/asm/unistd.h
+2
-1
arch/blackfin/include/asm/unistd.h
···
398
398
#define __NR_clock_adjtime 377
399
399
#define __NR_syncfs 378
400
400
#define __NR_setns 379
401
+
#define __NR_sendmmsg 380
401
402
402
-
#define __NR_syscall 380
403
+
#define __NR_syscall 381
403
404
#define NR_syscalls __NR_syscall
404
405
405
406
/* Old optional stuff no one actually uses */
+18
-18
arch/blackfin/kernel/debug-mmrs.c
+18
-18
arch/blackfin/kernel/debug-mmrs.c
···
13
13
14
14
#include <asm/blackfin.h>
15
15
#include <asm/gpio.h>
16
+
#include <asm/gptimers.h>
16
17
#include <asm/bfin_can.h>
17
18
#include <asm/bfin_dma.h>
18
19
#include <asm/bfin_ppi.h>
···
231
230
#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
232
231
#define _MDMA(num, x) \
233
232
do { \
234
-
_DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
235
-
_DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
233
+
_DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
234
+
_DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
236
235
} while (0)
237
236
#define MDMA(num) _MDMA(num, M)
238
237
#define IMDMA(num) _MDMA(num, IM)
···
265
264
/*
266
265
* General Purpose Timers
267
266
*/
268
-
#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
269
-
#define __GPTIMER(name) \
270
-
do { \
271
-
strcpy(_buf, #name); \
272
-
debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
273
-
} while (0)
267
+
#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
274
268
static void __init __maybe_unused
275
269
bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
276
270
{
277
271
char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
278
-
__GPTIMER(CONFIG);
279
-
__GPTIMER(COUNTER);
280
-
__GPTIMER(PERIOD);
281
-
__GPTIMER(WIDTH);
272
+
__GPTIMER(CONFIG, config);
273
+
__GPTIMER(COUNTER, counter);
274
+
__GPTIMER(PERIOD, period);
275
+
__GPTIMER(WIDTH, width);
282
276
}
283
277
#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
284
278
···
351
355
__PPI(DELAY, delay);
352
356
__PPI(FRAME, frame);
353
357
}
354
-
#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
358
+
#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
355
359
356
360
/*
357
361
* SPI
···
1284
1288
D16(VR_CTL);
1285
1289
D32(CHIPID); /* it's part of this hardware block */
1286
1290
1287
-
#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
1291
+
#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1288
1292
parent = debugfs_create_dir("ppi", top);
1289
-
# ifdef PPI_STATUS
1290
-
bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
1293
+
# ifdef PPI_CONTROL
1294
+
bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1291
1295
# endif
1292
-
# ifdef PPI0_STATUS
1296
+
# ifdef PPI0_CONTROL
1293
1297
PPI(0);
1294
1298
# endif
1295
-
# ifdef PPI1_STATUS
1299
+
# ifdef PPI1_CONTROL
1296
1300
PPI(1);
1297
1301
# endif
1298
1302
#endif
···
1337
1341
D16(RSI_PID1);
1338
1342
D16(RSI_PID2);
1339
1343
D16(RSI_PID3);
1344
+
D16(RSI_PID4);
1345
+
D16(RSI_PID5);
1346
+
D16(RSI_PID6);
1347
+
D16(RSI_PID7);
1340
1348
D16(RSI_PWR_CONTROL);
1341
1349
D16(RSI_RD_WAIT_EN);
1342
1350
D32(RSI_RESPONSE0);
-79
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
-79
arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2008-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
13
-
# ifndef CONFIG_UART0_CTS_PIN
14
-
# define CONFIG_UART0_CTS_PIN -1
15
-
# endif
16
-
17
-
# ifndef CONFIG_UART0_RTS_PIN
18
-
# define CONFIG_UART0_RTS_PIN -1
19
-
# endif
20
-
21
-
# ifndef CONFIG_UART1_CTS_PIN
22
-
# define CONFIG_UART1_CTS_PIN -1
23
-
# endif
24
-
25
-
# ifndef CONFIG_UART1_RTS_PIN
26
-
# define CONFIG_UART1_RTS_PIN -1
27
-
# endif
28
-
#endif
29
-
30
-
struct bfin_serial_res {
31
-
unsigned long uart_base_addr;
32
-
int uart_irq;
33
-
int uart_status_irq;
34
-
#ifdef CONFIG_SERIAL_BFIN_DMA
35
-
unsigned int uart_tx_dma_channel;
36
-
unsigned int uart_rx_dma_channel;
37
-
#endif
38
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
39
-
int uart_cts_pin;
40
-
int uart_rts_pin;
41
-
#endif
42
-
};
43
-
44
-
struct bfin_serial_res bfin_serial_resource[] = {
45
-
#ifdef CONFIG_SERIAL_BFIN_UART0
46
-
{
47
-
0xFFC00400,
48
-
IRQ_UART0_RX,
49
-
IRQ_UART0_ERROR,
50
-
#ifdef CONFIG_SERIAL_BFIN_DMA
51
-
CH_UART0_TX,
52
-
CH_UART0_RX,
53
-
#endif
54
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
55
-
CONFIG_UART0_CTS_PIN,
56
-
CONFIG_UART0_RTS_PIN,
57
-
#endif
58
-
},
59
-
#endif
60
-
#ifdef CONFIG_SERIAL_BFIN_UART1
61
-
{
62
-
0xFFC02000,
63
-
IRQ_UART1_RX,
64
-
IRQ_UART1_ERROR,
65
-
#ifdef CONFIG_SERIAL_BFIN_DMA
66
-
CH_UART1_TX,
67
-
CH_UART1_RX,
68
-
#endif
69
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
70
-
CONFIG_UART1_CTS_PIN,
71
-
CONFIG_UART1_RTS_PIN,
72
-
#endif
73
-
},
74
-
#endif
75
-
};
76
-
77
-
#define DRIVER_NAME "bfin-uart"
78
-
79
-
#include <asm/bfin_serial.h>
+8
-8
arch/blackfin/mach-bf518/include/mach/defBF514.h
+8
-8
arch/blackfin/mach-bf518/include/mach/defBF514.h
···
36
36
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
37
37
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
38
38
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
39
-
#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
40
-
#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
41
-
#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
42
-
#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
43
-
#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
44
-
#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
45
-
#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
46
-
#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
39
+
#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
40
+
#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
41
+
#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
42
+
#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
43
+
#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
44
+
#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
45
+
#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
46
+
#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
47
47
48
48
#endif /* _DEF_BF514_H */
-79
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
-79
arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2007-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
13
-
# ifndef CONFIG_UART0_CTS_PIN
14
-
# define CONFIG_UART0_CTS_PIN -1
15
-
# endif
16
-
17
-
# ifndef CONFIG_UART0_RTS_PIN
18
-
# define CONFIG_UART0_RTS_PIN -1
19
-
# endif
20
-
21
-
# ifndef CONFIG_UART1_CTS_PIN
22
-
# define CONFIG_UART1_CTS_PIN -1
23
-
# endif
24
-
25
-
# ifndef CONFIG_UART1_RTS_PIN
26
-
# define CONFIG_UART1_RTS_PIN -1
27
-
# endif
28
-
#endif
29
-
30
-
struct bfin_serial_res {
31
-
unsigned long uart_base_addr;
32
-
int uart_irq;
33
-
int uart_status_irq;
34
-
#ifdef CONFIG_SERIAL_BFIN_DMA
35
-
unsigned int uart_tx_dma_channel;
36
-
unsigned int uart_rx_dma_channel;
37
-
#endif
38
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
39
-
int uart_cts_pin;
40
-
int uart_rts_pin;
41
-
#endif
42
-
};
43
-
44
-
struct bfin_serial_res bfin_serial_resource[] = {
45
-
#ifdef CONFIG_SERIAL_BFIN_UART0
46
-
{
47
-
0xFFC00400,
48
-
IRQ_UART0_RX,
49
-
IRQ_UART0_ERROR,
50
-
#ifdef CONFIG_SERIAL_BFIN_DMA
51
-
CH_UART0_TX,
52
-
CH_UART0_RX,
53
-
#endif
54
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
55
-
CONFIG_UART0_CTS_PIN,
56
-
CONFIG_UART0_RTS_PIN,
57
-
#endif
58
-
},
59
-
#endif
60
-
#ifdef CONFIG_SERIAL_BFIN_UART1
61
-
{
62
-
0xFFC02000,
63
-
IRQ_UART1_RX,
64
-
IRQ_UART1_ERROR,
65
-
#ifdef CONFIG_SERIAL_BFIN_DMA
66
-
CH_UART1_TX,
67
-
CH_UART1_RX,
68
-
#endif
69
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
70
-
CONFIG_UART1_CTS_PIN,
71
-
CONFIG_UART1_RTS_PIN,
72
-
#endif
73
-
},
74
-
#endif
75
-
};
76
-
77
-
#define DRIVER_NAME "bfin-uart"
78
-
79
-
#include <asm/bfin_serial.h>
+2
-2
arch/blackfin/mach-bf527/include/mach/defBF525.h
+2
-2
arch/blackfin/mach-bf527/include/mach/defBF525.h
···
185
185
#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
186
186
#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
187
187
#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
188
-
#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
189
-
#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
188
+
#define USB_EP_NI7_RXINTERVAL 0xffc03be0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
189
+
#define USB_EP_NI7_TXCOUNT 0xffc03be8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
190
190
191
191
#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
192
192
-52
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
-52
arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2006-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#ifdef CONFIG_BFIN_UART0_CTSRTS
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
# ifndef CONFIG_UART0_CTS_PIN
13
-
# define CONFIG_UART0_CTS_PIN -1
14
-
# endif
15
-
# ifndef CONFIG_UART0_RTS_PIN
16
-
# define CONFIG_UART0_RTS_PIN -1
17
-
# endif
18
-
#endif
19
-
20
-
struct bfin_serial_res {
21
-
unsigned long uart_base_addr;
22
-
int uart_irq;
23
-
int uart_status_irq;
24
-
#ifdef CONFIG_SERIAL_BFIN_DMA
25
-
unsigned int uart_tx_dma_channel;
26
-
unsigned int uart_rx_dma_channel;
27
-
#endif
28
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
29
-
int uart_cts_pin;
30
-
int uart_rts_pin;
31
-
#endif
32
-
};
33
-
34
-
struct bfin_serial_res bfin_serial_resource[] = {
35
-
{
36
-
0xFFC00400,
37
-
IRQ_UART0_RX,
38
-
IRQ_UART0_ERROR,
39
-
#ifdef CONFIG_SERIAL_BFIN_DMA
40
-
CH_UART0_TX,
41
-
CH_UART0_RX,
42
-
#endif
43
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
44
-
CONFIG_UART0_CTS_PIN,
45
-
CONFIG_UART0_RTS_PIN,
46
-
#endif
47
-
}
48
-
};
49
-
50
-
#define DRIVER_NAME "bfin-uart"
51
-
52
-
#include <asm/bfin_serial.h>
-79
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
-79
arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2006-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
13
-
# ifndef CONFIG_UART0_CTS_PIN
14
-
# define CONFIG_UART0_CTS_PIN -1
15
-
# endif
16
-
17
-
# ifndef CONFIG_UART0_RTS_PIN
18
-
# define CONFIG_UART0_RTS_PIN -1
19
-
# endif
20
-
21
-
# ifndef CONFIG_UART1_CTS_PIN
22
-
# define CONFIG_UART1_CTS_PIN -1
23
-
# endif
24
-
25
-
# ifndef CONFIG_UART1_RTS_PIN
26
-
# define CONFIG_UART1_RTS_PIN -1
27
-
# endif
28
-
#endif
29
-
30
-
struct bfin_serial_res {
31
-
unsigned long uart_base_addr;
32
-
int uart_irq;
33
-
int uart_status_irq;
34
-
#ifdef CONFIG_SERIAL_BFIN_DMA
35
-
unsigned int uart_tx_dma_channel;
36
-
unsigned int uart_rx_dma_channel;
37
-
#endif
38
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
39
-
int uart_cts_pin;
40
-
int uart_rts_pin;
41
-
#endif
42
-
};
43
-
44
-
struct bfin_serial_res bfin_serial_resource[] = {
45
-
#ifdef CONFIG_SERIAL_BFIN_UART0
46
-
{
47
-
0xFFC00400,
48
-
IRQ_UART0_RX,
49
-
IRQ_UART0_ERROR,
50
-
#ifdef CONFIG_SERIAL_BFIN_DMA
51
-
CH_UART0_TX,
52
-
CH_UART0_RX,
53
-
#endif
54
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
55
-
CONFIG_UART0_CTS_PIN,
56
-
CONFIG_UART0_RTS_PIN,
57
-
#endif
58
-
},
59
-
#endif
60
-
#ifdef CONFIG_SERIAL_BFIN_UART1
61
-
{
62
-
0xFFC02000,
63
-
IRQ_UART1_RX,
64
-
IRQ_UART1_ERROR,
65
-
#ifdef CONFIG_SERIAL_BFIN_DMA
66
-
CH_UART1_TX,
67
-
CH_UART1_RX,
68
-
#endif
69
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
70
-
CONFIG_UART1_CTS_PIN,
71
-
CONFIG_UART1_RTS_PIN,
72
-
#endif
73
-
},
74
-
#endif
75
-
};
76
-
77
-
#define DRIVER_NAME "bfin-uart"
78
-
79
-
#include <asm/bfin_serial.h>
-93
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
-93
arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2008-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later.
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
13
-
# ifndef CONFIG_UART0_CTS_PIN
14
-
# define CONFIG_UART0_CTS_PIN -1
15
-
# endif
16
-
17
-
# ifndef CONFIG_UART0_RTS_PIN
18
-
# define CONFIG_UART0_RTS_PIN -1
19
-
# endif
20
-
21
-
# ifndef CONFIG_UART1_CTS_PIN
22
-
# define CONFIG_UART1_CTS_PIN -1
23
-
# endif
24
-
25
-
# ifndef CONFIG_UART1_RTS_PIN
26
-
# define CONFIG_UART1_RTS_PIN -1
27
-
# endif
28
-
#endif
29
-
30
-
struct bfin_serial_res {
31
-
unsigned long uart_base_addr;
32
-
int uart_irq;
33
-
int uart_status_irq;
34
-
#ifdef CONFIG_SERIAL_BFIN_DMA
35
-
unsigned int uart_tx_dma_channel;
36
-
unsigned int uart_rx_dma_channel;
37
-
#endif
38
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
39
-
int uart_cts_pin;
40
-
int uart_rts_pin;
41
-
#endif
42
-
};
43
-
44
-
struct bfin_serial_res bfin_serial_resource[] = {
45
-
#ifdef CONFIG_SERIAL_BFIN_UART0
46
-
{
47
-
0xFFC00400,
48
-
IRQ_UART0_RX,
49
-
IRQ_UART0_ERROR,
50
-
#ifdef CONFIG_SERIAL_BFIN_DMA
51
-
CH_UART0_TX,
52
-
CH_UART0_RX,
53
-
#endif
54
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
55
-
CONFIG_UART0_CTS_PIN,
56
-
CONFIG_UART0_RTS_PIN,
57
-
#endif
58
-
},
59
-
#endif
60
-
#ifdef CONFIG_SERIAL_BFIN_UART1
61
-
{
62
-
0xFFC02000,
63
-
IRQ_UART1_RX,
64
-
IRQ_UART1_ERROR,
65
-
#ifdef CONFIG_SERIAL_BFIN_DMA
66
-
CH_UART1_TX,
67
-
CH_UART1_RX,
68
-
#endif
69
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
70
-
CONFIG_UART1_CTS_PIN,
71
-
CONFIG_UART1_RTS_PIN,
72
-
#endif
73
-
},
74
-
#endif
75
-
#ifdef CONFIG_SERIAL_BFIN_UART2
76
-
{
77
-
0xFFC02100,
78
-
IRQ_UART2_RX,
79
-
#ifdef CONFIG_SERIAL_BFIN_DMA
80
-
CH_UART2_TX,
81
-
CH_UART2_RX,
82
-
#endif
83
-
#ifdef CONFIG_BFIN_UART2_CTSRTS
84
-
CONFIG_UART2_CTS_PIN,
85
-
CONFIG_UART2_RTS_PIN,
86
-
#endif
87
-
},
88
-
#endif
89
-
};
90
-
91
-
#define DRIVER_NAME "bfin-uart"
92
-
93
-
#include <asm/bfin_serial.h>
-94
arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
-94
arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2007-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later.
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
11
-
defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
12
-
# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
13
-
#endif
14
-
15
-
struct bfin_serial_res {
16
-
unsigned long uart_base_addr;
17
-
int uart_irq;
18
-
int uart_status_irq;
19
-
#ifdef CONFIG_SERIAL_BFIN_DMA
20
-
unsigned int uart_tx_dma_channel;
21
-
unsigned int uart_rx_dma_channel;
22
-
#endif
23
-
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
24
-
int uart_cts_pin;
25
-
int uart_rts_pin;
26
-
#endif
27
-
};
28
-
29
-
struct bfin_serial_res bfin_serial_resource[] = {
30
-
#ifdef CONFIG_SERIAL_BFIN_UART0
31
-
{
32
-
0xFFC00400,
33
-
IRQ_UART0_RX,
34
-
IRQ_UART0_ERROR,
35
-
#ifdef CONFIG_SERIAL_BFIN_DMA
36
-
CH_UART0_TX,
37
-
CH_UART0_RX,
38
-
#endif
39
-
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
40
-
0,
41
-
0,
42
-
#endif
43
-
},
44
-
#endif
45
-
#ifdef CONFIG_SERIAL_BFIN_UART1
46
-
{
47
-
0xFFC02000,
48
-
IRQ_UART1_RX,
49
-
IRQ_UART1_ERROR,
50
-
#ifdef CONFIG_SERIAL_BFIN_DMA
51
-
CH_UART1_TX,
52
-
CH_UART1_RX,
53
-
#endif
54
-
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
55
-
GPIO_PE10,
56
-
GPIO_PE9,
57
-
#endif
58
-
},
59
-
#endif
60
-
#ifdef CONFIG_SERIAL_BFIN_UART2
61
-
{
62
-
0xFFC02100,
63
-
IRQ_UART2_RX,
64
-
IRQ_UART2_ERROR,
65
-
#ifdef CONFIG_SERIAL_BFIN_DMA
66
-
CH_UART2_TX,
67
-
CH_UART2_RX,
68
-
#endif
69
-
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
70
-
0,
71
-
0,
72
-
#endif
73
-
},
74
-
#endif
75
-
#ifdef CONFIG_SERIAL_BFIN_UART3
76
-
{
77
-
0xFFC03100,
78
-
IRQ_UART3_RX,
79
-
IRQ_UART3_ERROR,
80
-
#ifdef CONFIG_SERIAL_BFIN_DMA
81
-
CH_UART3_TX,
82
-
CH_UART3_RX,
83
-
#endif
84
-
#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
85
-
GPIO_PB3,
86
-
GPIO_PB2,
87
-
#endif
88
-
},
89
-
#endif
90
-
};
91
-
92
-
#define DRIVER_NAME "bfin-uart"
93
-
94
-
#include <asm/bfin_serial.h>
+10
-9
arch/blackfin/mach-bf548/include/mach/defBF547.h
+10
-9
arch/blackfin/mach-bf548/include/mach/defBF547.h
···
271
271
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
272
272
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
273
273
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
274
+
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
274
275
275
276
/* USB Endpoint 1 Control Registers */
276
277
277
-
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
278
278
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
279
279
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
280
280
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
···
284
284
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
285
285
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
286
286
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
287
+
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
287
288
288
289
/* USB Endpoint 2 Control Registers */
289
290
290
-
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
291
291
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
292
292
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
293
293
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
···
297
297
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
298
298
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
299
299
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
300
+
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
300
301
301
302
/* USB Endpoint 3 Control Registers */
302
303
303
-
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
304
304
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
305
305
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
306
306
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
···
310
310
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
311
311
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
312
312
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
313
+
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
313
314
314
315
/* USB Endpoint 4 Control Registers */
315
316
316
-
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
317
317
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
318
318
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
319
319
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
···
323
323
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
324
324
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
325
325
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
326
+
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
326
327
327
328
/* USB Endpoint 5 Control Registers */
328
329
329
-
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
330
330
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
331
331
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
332
332
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
···
336
336
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
337
337
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
338
338
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
339
+
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
339
340
340
341
/* USB Endpoint 6 Control Registers */
341
342
342
-
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
343
343
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
344
344
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
345
345
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
···
349
349
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
350
350
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
351
351
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
352
+
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
352
353
353
354
/* USB Endpoint 7 Control Registers */
354
355
355
-
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
356
356
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
357
357
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
358
358
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
···
361
361
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
362
362
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
363
363
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
364
-
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
365
-
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
364
+
#define USB_EP_NI7_RXINTERVAL 0xffc03fe0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
365
+
#define USB_EP_NI7_TXCOUNT 0xffc03fe8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
366
+
366
367
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
367
368
368
369
/* USB Channel 0 Config Registers */
-52
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
-52
arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
···
1
-
/*
2
-
* Copyright 2006-2009 Analog Devices Inc.
3
-
*
4
-
* Licensed under the GPL-2 or later.
5
-
*/
6
-
7
-
#include <asm/dma.h>
8
-
#include <asm/portmux.h>
9
-
10
-
#ifdef CONFIG_BFIN_UART0_CTSRTS
11
-
# define CONFIG_SERIAL_BFIN_CTSRTS
12
-
# ifndef CONFIG_UART0_CTS_PIN
13
-
# define CONFIG_UART0_CTS_PIN -1
14
-
# endif
15
-
# ifndef CONFIG_UART0_RTS_PIN
16
-
# define CONFIG_UART0_RTS_PIN -1
17
-
# endif
18
-
#endif
19
-
20
-
struct bfin_serial_res {
21
-
unsigned long uart_base_addr;
22
-
int uart_irq;
23
-
int uart_status_irq;
24
-
#ifdef CONFIG_SERIAL_BFIN_DMA
25
-
unsigned int uart_tx_dma_channel;
26
-
unsigned int uart_rx_dma_channel;
27
-
#endif
28
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
29
-
int uart_cts_pin;
30
-
int uart_rts_pin;
31
-
#endif
32
-
};
33
-
34
-
struct bfin_serial_res bfin_serial_resource[] = {
35
-
{
36
-
0xFFC00400,
37
-
IRQ_UART_RX,
38
-
IRQ_UART_ERROR,
39
-
#ifdef CONFIG_SERIAL_BFIN_DMA
40
-
CH_UART_TX,
41
-
CH_UART_RX,
42
-
#endif
43
-
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
44
-
CONFIG_UART0_CTS_PIN,
45
-
CONFIG_UART0_RTS_PIN,
46
-
#endif
47
-
}
48
-
};
49
-
50
-
#define DRIVER_NAME "bfin-uart"
51
-
52
-
#include <asm/bfin_serial.h>