Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: lynx-28g: remove LYNX_28G_ prefix from register names
Currently, in macros such as lynx_28g_lane_rmw(), the driver has
macros which concatenate the LYNX_28G_ prefix with the "val" and "mask"
arguments. This is done to shorten function calls and not have to spell
out LYNX_28G_ everywhere.
But outside of lynx_28g_lane_rmw(), lynx_28g_lane_read() and
lynx_28g_pll_read(), this is not done, leading to an inconsistency in
the code.
Also, the concatenation itself has the disadvantage that searching the
arguments of these functions as full words (like N_RATE_QUARTER) leads
us nowhere, since the real macro definition is LNaTGCR0_N_RATE_QUARTER.
Some maintainers want register definitions in drivers to contain the
driver name as a prefix, but here, this has the disadvantages listed
above, so just remove that prefix.
The only change made here is the removal of LYNX_28G_.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://patch.msgid.link/20251125114847.804961-6-vladimir.oltean@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Vladimir Oltean
and committed by
Vinod Koul
13a5f7e3
2da0b221
+117
-117
+117
-117
drivers/phy/freescale/phy-fsl-lynx-28g.c
+117
-117
drivers/phy/freescale/phy-fsl-lynx-28g.c
···
12
12
#define LYNX_28G_NUM_PLL 2
13
13
14
14
/* General registers per SerDes block */
15
-
#define LYNX_28G_PCC8 0x10a0
16
-
#define LYNX_28G_PCC8_SGMII 0x1
17
-
#define LYNX_28G_PCC8_SGMII_DIS 0x0
15
+
#define PCC8 0x10a0
16
+
#define PCC8_SGMII 0x1
17
+
#define PCC8_SGMII_DIS 0x0
18
18
19
-
#define LYNX_28G_PCCC 0x10b0
20
-
#define LYNX_28G_PCCC_10GBASER 0x9
21
-
#define LYNX_28G_PCCC_USXGMII 0x1
22
-
#define LYNX_28G_PCCC_SXGMII_DIS 0x0
19
+
#define PCCC 0x10b0
20
+
#define PCCC_10GBASER 0x9
21
+
#define PCCC_USXGMII 0x1
22
+
#define PCCC_SXGMII_DIS 0x0
23
23
24
-
#define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
24
+
#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
25
25
26
26
/* Per PLL registers */
27
-
#define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
28
-
#define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
29
-
#define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
27
+
#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
28
+
#define PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
29
+
#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
30
30
31
-
#define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
32
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
33
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
34
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
35
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
36
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
37
-
#define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
31
+
#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
32
+
#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
33
+
#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
34
+
#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
35
+
#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
36
+
#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
37
+
#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
38
38
39
-
#define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
40
-
#define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
41
-
#define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0
42
-
#define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
43
-
#define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
39
+
#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
40
+
#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
41
+
#define PLLnCR1_FRATE_5G_10GVCO 0x0
42
+
#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
43
+
#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
44
44
45
45
/* Per SerDes lane registers */
46
46
/* Lane a General Control Register */
47
-
#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
48
-
#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
49
-
#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
50
-
#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
51
-
#define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
52
-
#define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
53
-
#define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
47
+
#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
48
+
#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
49
+
#define LNaGCR0_PROTO_SEL_SGMII 0x8
50
+
#define LNaGCR0_PROTO_SEL_XFI 0x50
51
+
#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
52
+
#define LNaGCR0_IF_WIDTH_10_BIT 0x0
53
+
#define LNaGCR0_IF_WIDTH_20_BIT 0x2
54
54
55
55
/* Lane a Tx Reset Control Register */
56
-
#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
57
-
#define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27)
58
-
#define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30)
59
-
#define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31)
56
+
#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
57
+
#define LNaTRSTCTL_HLT_REQ BIT(27)
58
+
#define LNaTRSTCTL_RST_DONE BIT(30)
59
+
#define LNaTRSTCTL_RST_REQ BIT(31)
60
60
61
61
/* Lane a Tx General Control Register */
62
-
#define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
63
-
#define LYNX_28G_LNaTGCR0_USE_PLLF 0x0
64
-
#define LYNX_28G_LNaTGCR0_USE_PLLS BIT(28)
65
-
#define LYNX_28G_LNaTGCR0_USE_PLL_MSK BIT(28)
66
-
#define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0
67
-
#define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000
68
-
#define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
69
-
#define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
62
+
#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
63
+
#define LNaTGCR0_USE_PLLF 0x0
64
+
#define LNaTGCR0_USE_PLLS BIT(28)
65
+
#define LNaTGCR0_USE_PLL_MSK BIT(28)
66
+
#define LNaTGCR0_N_RATE_FULL 0x0
67
+
#define LNaTGCR0_N_RATE_HALF 0x1000000
68
+
#define LNaTGCR0_N_RATE_QUARTER 0x2000000
69
+
#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
70
70
71
-
#define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
71
+
#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
72
72
73
73
/* Lane a Rx Reset Control Register */
74
-
#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
75
-
#define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27)
76
-
#define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30)
77
-
#define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31)
78
-
#define LYNX_28G_LNaRRSTCTL_CDR_LOCK BIT(12)
74
+
#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
75
+
#define LNaRRSTCTL_HLT_REQ BIT(27)
76
+
#define LNaRRSTCTL_RST_DONE BIT(30)
77
+
#define LNaRRSTCTL_RST_REQ BIT(31)
78
+
#define LNaRRSTCTL_CDR_LOCK BIT(12)
79
79
80
80
/* Lane a Rx General Control Register */
81
-
#define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
82
-
#define LYNX_28G_LNaRGCR0_USE_PLLF 0x0
83
-
#define LYNX_28G_LNaRGCR0_USE_PLLS BIT(28)
84
-
#define LYNX_28G_LNaRGCR0_USE_PLL_MSK BIT(28)
85
-
#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
86
-
#define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0
87
-
#define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000
88
-
#define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
89
-
#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
81
+
#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
82
+
#define LNaRGCR0_USE_PLLF 0x0
83
+
#define LNaRGCR0_USE_PLLS BIT(28)
84
+
#define LNaRGCR0_USE_PLL_MSK BIT(28)
85
+
#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
86
+
#define LNaRGCR0_N_RATE_FULL 0x0
87
+
#define LNaRGCR0_N_RATE_HALF 0x1000000
88
+
#define LNaRGCR0_N_RATE_QUARTER 0x2000000
89
+
#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
90
90
91
-
#define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
91
+
#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
92
92
93
-
#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
94
-
#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
95
-
#define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
93
+
#define LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
94
+
#define LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
95
+
#define LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
96
96
97
-
#define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
97
+
#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
98
98
99
-
#define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
100
-
#define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
101
-
#define LYNX_28G_LNaPSS_TYPE_SGMII 0x4
102
-
#define LYNX_28G_LNaPSS_TYPE_XFI 0x28
99
+
#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
100
+
#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
101
+
#define LNaPSS_TYPE_SGMII 0x4
102
+
#define LNaPSS_TYPE_XFI 0x28
103
103
104
-
#define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
105
-
#define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11)
106
-
#define LYNX_28G_SGMIIaCR1_SGPCS_DIS 0x0
107
-
#define LYNX_28G_SGMIIaCR1_SGPCS_MSK BIT(11)
104
+
#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
105
+
#define SGMIIaCR1_SGPCS_EN BIT(11)
106
+
#define SGMIIaCR1_SGPCS_DIS 0x0
107
+
#define SGMIIaCR1_SGPCS_MSK BIT(11)
108
108
109
109
struct lynx_28g_priv;
110
110
···
150
150
}
151
151
152
152
#define lynx_28g_lane_rmw(lane, reg, val, mask) \
153
-
lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
154
-
LYNX_28G_##reg##_##val, LYNX_28G_##reg##_##mask)
153
+
lynx_28g_rmw((lane)->priv, reg(lane->id), \
154
+
reg##_##val, reg##_##mask)
155
155
#define lynx_28g_lane_read(lane, reg) \
156
-
ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
156
+
ioread32((lane)->priv->base + reg((lane)->id))
157
157
#define lynx_28g_pll_read(pll, reg) \
158
-
ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
158
+
ioread32((pll)->priv->base + reg((pll)->id))
159
159
160
160
static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
161
161
{
162
162
int i;
163
163
164
164
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
165
-
if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl))
165
+
if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
166
166
continue;
167
167
168
168
if (test_bit(intf, priv->pll[i].supported))
···
181
181
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
182
182
pll = &priv->pll[i];
183
183
184
-
if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
184
+
if (PLLnRSTCTL_DIS(pll->rstctl))
185
185
continue;
186
186
187
187
if (test_bit(intf, pll->supported))
···
199
199
struct lynx_28g_pll *pll,
200
200
phy_interface_t intf)
201
201
{
202
-
switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
203
-
case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
204
-
case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
202
+
switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
203
+
case PLLnCR1_FRATE_5G_10GVCO:
204
+
case PLLnCR1_FRATE_5G_25GVCO:
205
205
switch (intf) {
206
206
case PHY_INTERFACE_MODE_SGMII:
207
207
case PHY_INTERFACE_MODE_1000BASEX:
···
212
212
break;
213
213
}
214
214
break;
215
-
case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
215
+
case PLLnCR1_FRATE_10G_20GVCO:
216
216
switch (intf) {
217
217
case PHY_INTERFACE_MODE_10GBASER:
218
218
case PHY_INTERFACE_MODE_USXGMII:
···
242
242
243
243
static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
244
244
{
245
-
u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
246
245
struct lynx_28g_priv *priv = lane->priv;
246
+
u32 lane_offset = LNa_PCC_OFFSET(lane);
247
247
248
248
/* Cleanup the protocol configuration registers of the current protocol */
249
249
switch (lane->interface) {
250
250
case PHY_INTERFACE_MODE_10GBASER:
251
-
lynx_28g_rmw(priv, LYNX_28G_PCCC,
252
-
LYNX_28G_PCCC_SXGMII_DIS << lane_offset,
251
+
lynx_28g_rmw(priv, PCCC,
252
+
PCCC_SXGMII_DIS << lane_offset,
253
253
GENMASK(3, 0) << lane_offset);
254
254
break;
255
255
case PHY_INTERFACE_MODE_SGMII:
256
256
case PHY_INTERFACE_MODE_1000BASEX:
257
-
lynx_28g_rmw(priv, LYNX_28G_PCC8,
258
-
LYNX_28G_PCC8_SGMII_DIS << lane_offset,
257
+
lynx_28g_rmw(priv, PCC8,
258
+
PCC8_SGMII_DIS << lane_offset,
259
259
GENMASK(3, 0) << lane_offset);
260
260
break;
261
261
default:
···
265
265
266
266
static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
267
267
{
268
-
u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
268
+
u32 lane_offset = LNa_PCC_OFFSET(lane);
269
269
struct lynx_28g_priv *priv = lane->priv;
270
270
struct lynx_28g_pll *pll;
271
271
272
272
lynx_28g_cleanup_lane(lane);
273
273
274
274
/* Setup the lane to run in SGMII */
275
-
lynx_28g_rmw(priv, LYNX_28G_PCC8,
276
-
LYNX_28G_PCC8_SGMII << lane_offset,
275
+
lynx_28g_rmw(priv, PCC8,
276
+
PCC8_SGMII << lane_offset,
277
277
GENMASK(3, 0) << lane_offset);
278
278
279
279
/* Setup the protocol select and SerDes parallel interface width */
···
295
295
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
296
296
297
297
/* Configure the appropriate equalization parameters for the protocol */
298
-
iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
299
-
iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
300
-
iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
301
-
iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
302
-
iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
303
-
iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
298
+
iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
299
+
iowrite32(0x04310000, priv->base + LNaRGCR1(lane->id));
300
+
iowrite32(0x9f800000, priv->base + LNaRECR0(lane->id));
301
+
iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
302
+
iowrite32(0x00000000, priv->base + LNaRECR2(lane->id));
303
+
iowrite32(0x00000000, priv->base + LNaRSCCR0(lane->id));
304
304
}
305
305
306
306
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
307
307
{
308
-
u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
309
308
struct lynx_28g_priv *priv = lane->priv;
309
+
u32 lane_offset = LNa_PCC_OFFSET(lane);
310
310
struct lynx_28g_pll *pll;
311
311
312
312
lynx_28g_cleanup_lane(lane);
313
313
314
314
/* Enable the SXGMII lane */
315
-
lynx_28g_rmw(priv, LYNX_28G_PCCC,
316
-
LYNX_28G_PCCC_10GBASER << lane_offset,
315
+
lynx_28g_rmw(priv, PCCC,
316
+
PCCC_10GBASER << lane_offset,
317
317
GENMASK(3, 0) << lane_offset);
318
318
319
319
/* Setup the protocol select and SerDes parallel interface width */
···
335
335
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
336
336
337
337
/* Configure the appropriate equalization parameters for the protocol */
338
-
iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
339
-
iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
340
-
iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
341
-
iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
342
-
iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
343
-
iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
338
+
iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
339
+
iowrite32(0x10000000, priv->base + LNaRGCR1(lane->id));
340
+
iowrite32(0x00000000, priv->base + LNaRECR0(lane->id));
341
+
iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
342
+
iowrite32(0x81000020, priv->base + LNaRECR2(lane->id));
343
+
iowrite32(0x00002000, priv->base + LNaRSCCR0(lane->id));
344
344
}
345
345
346
346
static int lynx_28g_power_off(struct phy *phy)
···
359
359
do {
360
360
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
361
361
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
362
-
} while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) ||
363
-
(rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ));
362
+
} while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
363
+
(rrstctl & LNaRRSTCTL_HLT_REQ));
364
364
365
365
lane->powered_up = false;
366
366
···
383
383
do {
384
384
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
385
385
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
386
-
} while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) ||
387
-
!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
386
+
} while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
387
+
!(rrstctl & LNaRRSTCTL_RST_DONE));
388
388
389
389
lane->powered_up = true;
390
390
···
495
495
pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0);
496
496
pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1);
497
497
498
-
if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
498
+
if (PLLnRSTCTL_DIS(pll->rstctl))
499
499
continue;
500
500
501
-
switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
502
-
case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
503
-
case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
501
+
switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
502
+
case PLLnCR1_FRATE_5G_10GVCO:
503
+
case PLLnCR1_FRATE_5G_25GVCO:
504
504
/* 5GHz clock net */
505
505
__set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
506
506
__set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
507
507
break;
508
-
case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
508
+
case PLLnCR1_FRATE_10G_20GVCO:
509
509
/* 10.3125GHz clock net */
510
510
__set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
511
511
break;
···
536
536
}
537
537
538
538
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
539
-
if (!(rrstctl & LYNX_28G_LNaRRSTCTL_CDR_LOCK)) {
539
+
if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
540
540
lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
541
541
do {
542
542
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
543
-
} while (!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
543
+
} while (!(rrstctl & LNaRRSTCTL_RST_DONE));
544
544
}
545
545
546
546
mutex_unlock(&lane->phy->mutex);
···
554
554
u32 pss, protocol;
555
555
556
556
pss = lynx_28g_lane_read(lane, LNaPSS);
557
-
protocol = LYNX_28G_LNaPSS_TYPE(pss);
557
+
protocol = LNaPSS_TYPE(pss);
558
558
switch (protocol) {
559
-
case LYNX_28G_LNaPSS_TYPE_SGMII:
559
+
case LNaPSS_TYPE_SGMII:
560
560
lane->interface = PHY_INTERFACE_MODE_SGMII;
561
561
break;
562
-
case LYNX_28G_LNaPSS_TYPE_XFI:
562
+
case LNaPSS_TYPE_XFI:
563
563
lane->interface = PHY_INTERFACE_MODE_10GBASER;
564
564
break;
565
565
default: