Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
* 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6:
OMAP2xxx clock: set up clockdomain pointer in struct clk
OMAP: Fix race condition with autodeps
omap: McBSP: Fix incorrect receiver stop in omap_mcbsp_stop
omap: Initialization of SDRC params on Zoom2
omap: RX-51: Drop I2C-1 speed to 2200
omap: SDMA: Fixing bug in omap_dma_set_global_params()
omap: CONFIG_ISP1301_OMAP redefined in Beagle defconfig
+59
-40
-1
arch/arm/configs/omap3_beagle_defconfig
-1
arch/arm/configs/omap3_beagle_defconfig
+1
-1
arch/arm/mach-omap2/board-rx51-peripherals.c
+1
-1
arch/arm/mach-omap2/board-rx51-peripherals.c
···
444
444
rx51_twldata.vaux3 = &rx51_vaux3_cam;
445
445
rx51_twldata.vmmc2 = &rx51_vmmc2;
446
446
}
447
-
omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1,
447
+
omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
448
448
ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
449
449
omap_register_i2c_bus(2, 100, NULL, 0);
450
450
omap_register_i2c_bus(3, 400, NULL, 0);
+3
-1
arch/arm/mach-omap2/board-zoom2.c
+3
-1
arch/arm/mach-omap2/board-zoom2.c
···
25
25
#include <mach/keypad.h>
26
26
27
27
#include "mmc-twl4030.h"
28
+
#include "sdram-micron-mt46h32m32lf-6.h"
28
29
29
30
/* Zoom2 has Qwerty keyboard*/
30
31
static int board_keymap[] = {
···
214
213
{
215
214
omap_board_config = zoom2_config;
216
215
omap_board_config_size = ARRAY_SIZE(zoom2_config);
217
-
omap2_init_common_hw(NULL, NULL);
216
+
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
217
+
mt46h32m32lf6_sdrc_params);
218
218
omap_init_irq();
219
219
omap_gpio_init();
220
220
}
+1
arch/arm/mach-omap2/clock24xx.c
+1
arch/arm/mach-omap2/clock24xx.c
+44
-30
arch/arm/mach-omap2/clockdomain.c
+44
-30
arch/arm/mach-omap2/clockdomain.c
···
137
137
}
138
138
}
139
139
140
+
/*
141
+
* _omap2_clkdm_set_hwsup - set the hwsup idle transition bit
142
+
* @clkdm: struct clockdomain *
143
+
* @enable: int 0 to disable, 1 to enable
144
+
*
145
+
* Internal helper for actually switching the bit that controls hwsup
146
+
* idle transitions for clkdm.
147
+
*/
148
+
static void _omap2_clkdm_set_hwsup(struct clockdomain *clkdm, int enable)
149
+
{
150
+
u32 v;
151
+
152
+
if (cpu_is_omap24xx()) {
153
+
if (enable)
154
+
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
155
+
else
156
+
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
157
+
} else if (cpu_is_omap34xx()) {
158
+
if (enable)
159
+
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
160
+
else
161
+
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
162
+
} else {
163
+
BUG();
164
+
}
165
+
166
+
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
167
+
v << __ffs(clkdm->clktrctrl_mask),
168
+
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
169
+
}
140
170
141
171
static struct clockdomain *_clkdm_lookup(const char *name)
142
172
{
···
486
456
*/
487
457
void omap2_clkdm_allow_idle(struct clockdomain *clkdm)
488
458
{
489
-
u32 v;
490
-
491
459
if (!clkdm)
492
460
return;
493
461
···
501
473
if (atomic_read(&clkdm->usecount) > 0)
502
474
_clkdm_add_autodeps(clkdm);
503
475
504
-
if (cpu_is_omap24xx())
505
-
v = OMAP24XX_CLKSTCTRL_ENABLE_AUTO;
506
-
else if (cpu_is_omap34xx())
507
-
v = OMAP34XX_CLKSTCTRL_ENABLE_AUTO;
508
-
else
509
-
BUG();
510
-
511
-
512
-
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
513
-
v << __ffs(clkdm->clktrctrl_mask),
514
-
clkdm->pwrdm.ptr->prcm_offs,
515
-
CM_CLKSTCTRL);
476
+
_omap2_clkdm_set_hwsup(clkdm, 1);
516
477
517
478
pwrdm_clkdm_state_switch(clkdm);
518
479
}
···
517
500
*/
518
501
void omap2_clkdm_deny_idle(struct clockdomain *clkdm)
519
502
{
520
-
u32 v;
521
-
522
503
if (!clkdm)
523
504
return;
524
505
···
529
514
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
530
515
clkdm->name);
531
516
532
-
if (cpu_is_omap24xx())
533
-
v = OMAP24XX_CLKSTCTRL_DISABLE_AUTO;
534
-
else if (cpu_is_omap34xx())
535
-
v = OMAP34XX_CLKSTCTRL_DISABLE_AUTO;
536
-
else
537
-
BUG();
538
-
539
-
cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask,
540
-
v << __ffs(clkdm->clktrctrl_mask),
541
-
clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL);
517
+
_omap2_clkdm_set_hwsup(clkdm, 0);
542
518
543
519
if (atomic_read(&clkdm->usecount) > 0)
544
520
_clkdm_del_autodeps(clkdm);
···
575
569
v = omap2_clkdm_clktrctrl_read(clkdm);
576
570
577
571
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
578
-
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
572
+
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
573
+
/* Disable HW transitions when we are changing deps */
574
+
_omap2_clkdm_set_hwsup(clkdm, 0);
579
575
_clkdm_add_autodeps(clkdm);
580
-
else
576
+
_omap2_clkdm_set_hwsup(clkdm, 1);
577
+
} else {
581
578
omap2_clkdm_wakeup(clkdm);
579
+
}
582
580
583
581
pwrdm_wait_transition(clkdm->pwrdm.ptr);
584
582
pwrdm_clkdm_state_switch(clkdm);
···
633
623
v = omap2_clkdm_clktrctrl_read(clkdm);
634
624
635
625
if ((cpu_is_omap34xx() && v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ||
636
-
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO))
626
+
(cpu_is_omap24xx() && v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO)) {
627
+
/* Disable HW transitions when we are changing deps */
628
+
_omap2_clkdm_set_hwsup(clkdm, 0);
637
629
_clkdm_del_autodeps(clkdm);
638
-
else
630
+
_omap2_clkdm_set_hwsup(clkdm, 1);
631
+
} else {
639
632
omap2_clkdm_sleep(clkdm);
633
+
}
640
634
641
635
pwrdm_clkdm_state_switch(clkdm);
642
636
+9
-6
arch/arm/plat-omap/dma.c
+9
-6
arch/arm/plat-omap/dma.c
···
829
829
*
830
830
* @param arb_rate
831
831
* @param max_fifo_depth
832
-
* @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
833
-
* DMA_THREAD_RESERVE_ONET
834
-
* DMA_THREAD_RESERVE_TWOT
835
-
* DMA_THREAD_RESERVE_THREET
832
+
* @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
833
+
* DMA_THREAD_RESERVE_ONET
834
+
* DMA_THREAD_RESERVE_TWOT
835
+
* DMA_THREAD_RESERVE_THREET
836
836
*/
837
837
void
838
838
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
···
844
844
return;
845
845
}
846
846
847
+
if (max_fifo_depth == 0)
848
+
max_fifo_depth = 1;
847
849
if (arb_rate == 0)
848
850
arb_rate = 1;
849
851
850
-
reg = (arb_rate & 0xff) << 16;
851
-
reg |= (0xff & max_fifo_depth);
852
+
reg = 0xff & max_fifo_depth;
853
+
reg |= (0x3 & tparams) << 12;
854
+
reg |= (arb_rate & 0xff) << 16;
852
855
853
856
dma_write(reg, GCR);
854
857
}
+1
-1
arch/arm/plat-omap/mcbsp.c
+1
-1
arch/arm/plat-omap/mcbsp.c