clk: microchip: mpfs: add MSS pll's set & round rate

The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on the
FPGA occupy the other three outputs of the PLL & prevent changing
the multiplier.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com

authored by

Conor Dooley and committed by

Claudiu Beznea 3 years ago 14016e4a 356a5048

+54

1 changed file

expand all

drivers

clk

microchip

clk-mpfs.c

+54

drivers/clk/microchip/clk-mpfs.c

··· 129 129 return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); 130 130 } 131 131 132 + static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) 133 + { 134 + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 135 + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 136 + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 137 + u32 mult, ref_div; 138 + unsigned long rate_before_ctrl; 139 + 140 + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 141 + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 142 + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 143 + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 144 + 145 + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 146 + 147 + return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 148 + msspll_hw->flags); 149 + } 150 + 151 + static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) 152 + { 153 + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); 154 + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; 155 + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; 156 + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; 157 + u32 mult, ref_div, postdiv; 158 + int divider_setting; 159 + unsigned long rate_before_ctrl, flags; 160 + 161 + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; 162 + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); 163 + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; 164 + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); 165 + 166 + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; 167 + divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, 168 + msspll_hw->flags); 169 + 170 + if (divider_setting < 0) 171 + return divider_setting; 172 + 173 + spin_lock_irqsave(&mpfs_clk_lock, flags); 174 + 175 + postdiv = readl_relaxed(postdiv_addr); 176 + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); 177 + writel_relaxed(postdiv, postdiv_addr); 178 + 179 + spin_unlock_irqrestore(&mpfs_clk_lock, flags); 180 + 181 + return 0; 182 + } 183 + 132 184 static const struct clk_ops mpfs_clk_msspll_ops = { 133 185 .recalc_rate = mpfs_clk_msspll_recalc_rate, 186 + .round_rate = mpfs_clk_msspll_round_rate, 187 + .set_rate = mpfs_clk_msspll_set_rate, 134 188 }; 135 189 136 190 #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \

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